JPH0648727B2 - Method for manufacturing semiconductor integrated circuit - Google Patents

Description

The present invention particularly relates to a method for manufacturing a semiconductor integrated circuit device including an insulated gate field effect transistor (hereinafter referred to as a MOS transistor), and more specifically, it is formed parasitically between circuit elements. The present invention relates to a method for manufacturing a novel semiconductor integrated circuit device in which a so-called parasitic MOS transistor is removed.

The parasitic MOS transistor, as shown in FIG.
At least two or more second-conductivity-type semiconductor regions 2 and 3 are adjacent to each other within one main surface of the conductivity-type semiconductor substrate 1, and a gap region 4 (hereinafter referred to as a gate region) between the regions is thick. It is easily formed when the insulating layer 5 covers and the metal wiring 6 such as Al (aluminum) exists on the insulating layer 5.
That is, when a voltage exceeding the threshold voltage V _ths of the parasitic MOS transistor is applied to the metal wiring 6, the surface 4 of the semiconductor substrate of the first conductivity type below the metal wiring 6 is inverted to the semiconductor of the second conductivity type. , The second conductivity type semiconductor region 2,
A channel is formed between the semiconductor regions 2 and 3, so that the semiconductor regions 2 and 3 of the second conductivity type become conductive. This means that the MO formed on one main surface portion of the semiconductor substrate 1
It was confirmed that the S-transistors 7 and 8 are coupled to each other, which deteriorates the operating characteristics and causes an inoperability at a bad time, which greatly affects the electrical characteristics and the yield of the MOS type IC or LSI. There is.

There are mainly two typical methods that have been conventionally used to prevent the influence of the parasitic MOS transistor as described above. One of them is to increase the thickness of the insulating layer 5 at the place (parasitic MOS gate region 4) where the parasitic MOS transistor as shown in FIG. 2 is formed. Another way is
In the gate region of the parasitic MOS transistor as shown in FIG. 3, a semiconductor region of the same conductivity type as the semiconductor substrate and having a high concentration is formed.
This is a method of forming a 10 (so-called channel stopper) and cutting the channel of the MOS transistor.

However, in the method shown at the beginning, in order to completely eliminate the influence of the parasitic MOS transistor, the thickness (T _GOX ) of the insulator layer 9 in the gate region is about 700Å even if the maximum operating voltage is about 3V. The thickness (T _FOX ) of the insulating layer 5 in the gate region 4 of the parasitic MOS transistor is about 8000
It needs to be thicker than Å. As a result, there is a risk of disconnection of the metal wiring due to the step difference between the two insulating layers. Further, in the structure as shown in FIG. 2 in which the channel stopper is not provided, when the distance between the semiconductor regions 2 and 3 is narrowed, the threshold voltage V _ths of the parasitic MOS transistor sharply decreases, which is a so-called short channel effect. Occur. To avoid this effect, the semiconductor regions 2, 3 should be at least 6
Since μm needs to be separated, there is a drawback that prevents high integration.

In the method described later, the channel stopper 10
To the concentration of about 10 ¹⁸ / cm ³ or more, although a parasitic MOS transistor which can be completely prevented, a high concentration PN junction is formed between the regions 2 and 3. Therefore, this junction capacitance reduces the operating speed of the device, and
There is a drawback that current consumption increases due to charging and discharging of the junction capacitance portion. The channel stopper 10
The above-mentioned problem does not occur if the film is formed separately from the regions 2 and 3. However, there is a problem in that the degree of integration of the device cannot be improved due to the spacing and the alignment allowance of the channel stopper 10.

The present invention eliminates the above-mentioned drawbacks of the prior art, and its purpose is therefore to ensure that the parasitic M does not hinder high integration and does not reduce the operating speed and increase the current consumption.
It is to provide a manufacturing method in which the OSFET is removed.

That is, in the method for manufacturing a semiconductor device according to the present invention, the first and second active regions are provided on the semiconductor substrate, and the first active region is provided on the first active region of the semiconductor substrate by forming an opening in the insulating layer. The contact window for forming the electrode is tapered, and ion implantation is performed to utilize the thickness of the insulating layer of the tapered contact window portion to contact the first active region and the semiconductor on the second active region side. An impurity region of the opposite conductivity type having a higher concentration than the substrate concentration is formed in the substrate.

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 4 is a sectional view of an active region portion such as a source or drain region obtained by the manufacturing method of the present invention. This is obtained as follows. First, the second conductivity type semiconductor region 2 is formed in one main surface of the first conductivity type semiconductor substrate 1, and the entire surface is covered with the insulator layer 5. A part of the insulating layer 5 is removed to form the opening 11. At this time, the thickness of the insulating layer 5 around the opening of the second conductivity type semiconductor region 2 is set from the opening end 12 to the junction between the first conductivity type semiconductor substrate 1 and the second conductivity type semiconductor region 2. Taper etching is performed so as to gradually increase up to the surface of the semiconductor substrate of the first conductivity type through the partial surface 13. After that, the first conductivity type impurities are ion-implanted, so that the first conductivity type impurity is ion-implanted around the second conductivity type semiconductor region 2.
A first conductive type semiconductor region 14 (hereinafter referred to as a guard ring) having an impurity concentration higher than that of the conductive type semiconductor substrate 1 is provided. The reason why the first conductivity type guard ring 14 can be formed around the second conductivity type semiconductor region 2 in the method for manufacturing a semiconductor integrated circuit is that the range of ions in the ion implantation method with respect to the thickness of the insulator layer 5 is increased. It can be explained from the distance difference. That is, the thickness of the insulator layer 5 is set to 8000
Å, the taper angle 15 at the opening end of the insulating layer 5 is set to 2
By selecting the condition of 5 ° and the concentration of the semiconductor substrate 1 <the concentration of the guard ring <the concentration of the semiconductor diffusion region, (1) the parasitic M
In order to remove the OS transistor, it is possible to prevent disconnection of the metal wiring caused by increasing the thickness of the insulating layer on the surface of the semiconductor substrate, and (2) the guard ring 14 around the second conductivity type semiconductor region is formed. Since it can be formed by selecting appropriate ion implantation conditions, the distance between the gate regions of the parasitic MOS transistors can be shortened as much as possible.
There is an advantage that the integration degree of C or LSI is increased. Further, since the concentration of the guard ring 14 is lower than the concentration of the diffusion layer in the conventional channel stopper method by about one digit, an increase in operating speed and a reduction in current consumption can be expected.

FIG. 5 is a process sectional view according to an embodiment of the present invention. First, as shown in FIG. 5 (a), a silicon oxide film 5 is formed on a P-type semiconductor substrate (impurity concentration of about 10 ¹⁵ / cm ³ ), and a portion to be an N ⁺ diffusion layer is formed in a subsequent step. The silicon oxide film is selectively removed. Next, after forming N ⁺ diffusion layers 2, ^3, 16 and 17 (impurity concentration about 10 ¹⁹ / cm ³ ) which are active layers such as sources and drains, the entire surface of the semiconductor substrate 1 is oxidized to form the N ⁺ diffusion layers. The thickness of the oxide film 5 on the area is set to about 80
00Å (Fig. (B)). Next, using a parallel plate type plasma dry etching apparatus, gas: CF ₄ + 5% O ₂ , temperature 12
Plasma irradiation is performed under the conditions of 0 ° C., power of 200 W, and time: 10 seconds. Then, if the gate region and the contact portion between the N ⁺ diffusion layer and the metal wiring are selectively etched with an oxide film, a taper corner is formed near the opening. A 25 ° oxide film 18 is obtained (FIG. 7 (c)). Next, as shown in FIG.
The photoresist 19 is used to mask a portion where the S transistor is not formed. In this state, energy 10
By implanting boron ions of 0 to 150 keV and a dose of 2 × 10 ¹⁴ / cm ² , the N ⁺ diffusion layers 2 and 3 are formed.
A guard ring 14 having a surface concentration of 10 ¹⁶ to 10 ¹⁷ / cm ³ is formed around the periphery of the (FIG. 6 (e)). Next photoresist 1
After removing 9, the exposed portion of the surface of the semiconductor substrate is oxidized, and the thickness of the gate oxide film 9 is set to about 700Å,
Contact portions 20, 21, between the metal wiring 6 and the N ⁺ diffusion layer region,
After opening the oxide film windows of 22 and 23, a predetermined metal wiring 6 is formed ((f) of the same figure).

It should be noted that in the above embodiments, an N-channel MOS transistor is shown, but this is not meant to be limiting.

As described above, in the semiconductor region formed close to the semiconductor substrate, the parasitic MOS transistor is removed by the guard ring around the semiconductor region, and the integration degree is higher, the operation speed is higher and the current consumption is lower than that in the conventional method. MOS type IC
Alternatively, an LSI can be realized.

[Brief description of drawings]

FIG. 1 is a MOS showing the reason why a parasitic MOS transistor is generated.
FIGS. 2 and 3 are sectional views of a type IC, and are explanatory views of a conventional method for preventing the influence of a parasitic MOS transistor. FIG. 4 shows a novel semiconductor integrated circuit device for preventing the influence of a parasitic MOS transistor in the present invention, (a) is a top view of the device, and (b) is a longitudinal sectional view. 5 (a) to 5 (f) are sectional views showing the manufacturing method of the present invention in the order of steps. In the above figures, 1 ... Semiconductor substrate, 2, 3 ... Semiconductor diffusion layer, 4 ... Gate region of parasitic MOS transistor, 5 ... Thick insulator layer, 6 ... Metal wiring, 7, 8 ... ... MOS transistors,
9 ... Thin insulator layer, 10 ... Channel stopper diffusion layer, 11 ... Insulator layer opening, 12 ... Insulator layer opening end, 13 ... PN junction surface, 14 ... Guard ring, 15 ...... Taper angle, 16, 17 ・ ・ ・ Semiconductor diffusion layer, 18 ・ ・ ・ Tapered state near the insulator layer opening, 19
...... Photoresist, 20, 21, 22, 23 ...... Contact portion between metal wiring and semiconductor diffusion layer.

Claims (1)

[Claims] 1. A step of forming a semiconductor region of a second conductivity type in a semiconductor substrate of a first conductivity type, a step of forming an insulating layer having a taper portion immediately above at least one side surface of the semiconductor region, and the taper. Selectively forming a first-conductivity-type guard ring in the semiconductor base adjacent to the side surface of the semiconductor region and having a higher concentration than that of the semiconductor substrate by implanting ions through the portion. A method of manufacturing a semiconductor integrated circuit having a feature.