JPH0648815B2 - Data transmission device and method - Google Patents

Description

The present invention relates to a control device for a data bus used in a data processing device, and more particularly to a bus control method suitable for a system requiring high reliability.

[Conventional technology]

Conventionally, in data processing systems, a data bus is often used as a data transmission path. The reason is as follows.

1. High-speed and multi-bit information can be transmitted in parallel.
High throughput data transfer is possible.

2. Since the transmission line is shared by multiple pieces of hardware, there is an advantage that the amount of hardware can be small.

On the other hand, since the data bus is shared by multiple devices, in addition to the procedure related to data transfer, the procedure related to exclusive processing for avoiding data collision caused by the simultaneous use of the data bus by two or more devices. Is required.

Exclusive control in a general data bus is
EE-796 standard (IEEE796 standard) and eye
EE EE 1014 standard (IEEE P1014
As defined in (Standard), the device that actively activates the data transfer turns on the bus busy signal indicating that the data bus is being used, and while this bus busy signal is on, other devices are active. It was done by inhibiting the device from using the data bus.

The exclusive control will be described with reference to the drawings. FIG. 2 shows the configuration of the data transmission device. Data is transferred between an access activation module (hereinafter referred to as a master module) and an access passive module (hereinafter referred to as a slave module).

The master module, which intends to transfer data, turns on the bus occupancy request signal 5 in order to occupy the bus, and causes the bus occupancy control device 1 (hereinafter referred to as a bus arbiter) to issue a bus occupancy permission signal 6. wait. The bus arbiter 1 detects that the bus does not occupy any master module. This can be confirmed by the fact that the bus busy signal is off. Then, the bus occupancy permission signal 6 is issued to the module having the highest priority among the master modules issuing the bus occupancy request signal 5.

The master module that issued the bus occupation request signal 6
The bus busy signal is turned on to prevent the bus arbiter 1 from issuing a bus occupation permission signal to another master module.

Only the master module that can occupy the bus by the above procedure can transfer data with the slave module. Data transfer is performed using the address 10, the data 9, the access request signal 8 and the access response signal 7.

In the case of the READ operation, the master module that can occupy the bus turns on the address 10 to specify the slave module for data transfer, and turns on the access request signal 8. The designated slave module turns on the read data to the data 9 and turns on the access response signal. When the master module takes in the data 9, it turns off the access request signal and turns on the bus busy signal.
The FF is performed to end the data transfer.

In the case of the WRITE operation, the master module that can occupy the bus turns on the address 10, turns on the access request signal 8 and outputs the write data to the data 9.
Take N bus. Then, when the slave module fetches the write data, the access response signal is turned on, the master module turns off the access request signal and turns off the bus busy signal to terminate the data transfer.

FIG. 3 schematically illustrates the above process with the passage of time.

When the master module 21 turns on the bus occupancy request signal 5 (arrow 2100), the bus arbiter 1 detects that the bus does not occupy any master module and then sends the bus occupancy permission signal 6 to the master module 21. It issues it (arrow 1210). The master module 21 turns on the bus busy signal 4 (arrow 2101) and turns on the access request signal 8 to the slave module 31 (arrow 2102).

If the master module 22 turns on the bus occupation request signal 5 at this point (arrow 2200), the bus arbiter 1 does not issue the bus occupation permission signal 6 because the bus busy signal is turned on.

The slave module 31 sends an access response signal O
N (arrow 3102), the access is terminated, and the master module 21 turns off the bus busy signal 4 (arrow 21).
03), the master module 22 can receive the bus occupation permission signal (arrow 1220).

[Problems to be Solved by the Invention] In order to clarify the problems of the above-described conventional technology, the configuration of FIG. 4 will be described. Here, the slave module 31 is connected to the subsystem 315, and the slave module 3 is connected.
The access request for 1 is further sent to the subsystem 315 as an access request signal 316 for the subsystem 315, and the access response signal 317 becomes the access response of the slave module 31.

FIG. 5 shows the process of signals between the devices as time passes, as in FIG. When the access request signal 8 is issued from the master module 21 to the slave module 31 (arrow 2102), the slave module 31 is issued.
Access signal 316 to subsystem 315.
Is issued (arrow 3106). The access response signal 317 from the subsystem 315 is received (arrow 3107).
Then, the slave module 31 issues the access response signal 7 (arrow 3102), the master module 21 terminates the access, and turns off the bus busy signal 4 (arrow 2103).

Now, the master module 21 terminates access during data transfer due to power failure, malfunction, and other factors.
Consider the case where the Bivisi signal 4 is turned off.

In FIG. 6, consider a case where the master module 21 turns off the bi-busy signal 4 (arrow 2103) before receiving the access response signal 7 from the slave module 31 (arrow 3102).

The bus arbiter 1 issues the bus occupancy permission signal 6 to the master module 22 which has turned on the bus occupancy request signal (arrow 1220). As a result, the master module 22 issues the access request signal 8 to the slave module 32 (arrow 2202). On the other hand, when the slave module 31 receives the response signal from the subsystem 315 (arrow 3107), the access response signal 7
Is issued (arrow 3102). At this time, the master module 22 has issued the access request signal 8 (arrow 2202) and is waiting for the reception of the access response signal 7 from the slave module 32 (arrow 3202). However, since the slave module 31 precedes and issues the access response signal 7 (arrow 3102), the master module 22 erroneously receives this, terminates the access, and turns off the bus busy signal 4 (arrow 220).
3). As a result, the access response (arrow 3202) of the slave module 32 may also be erroneously received by another master module.

As described above, in the conventional method, if the master module interrupts the access during the data transfer, there is a problem that the data transfer of the subsequent bus is not normally performed.

It is an object of the present invention to provide a bus control device capable of allowing a subsequent bus operation to be normally performed even if an access is interrupted by a master module during data transfer and improving system reliability. is there.

[Means for solving problems]

The above-mentioned purpose is to turn on the bus busy for the means indicating the data bus until the master module receiving the bus occupancy permission signal fetches the response signal from the accessed slave module. This is achieved by turning on the bus busy signal during the data transfer operation from the module as well so that the bus occupation permission signal is not issued to other master modules.

[Action]

This will be described with reference to FIG. Slave module 31
When the access request signal 8 from the master module 21 is received (arrow 2102), it is further sent to the subsystem 315 (arrow 3106), and the means for indicating that the data transfer operation is in progress indicates the occupation of the data bus. The bus busy signal is turned on to the means (arrow 3101).
When the data transfer is completed (arrow 3102), the bus busy signal is turned off (arrow 3103). Accordingly, even if the master module 21 interrupts access midway and turns off the bus busy signal (arrow 2103), the bus busy signal is still in the ON state, so the bus occupation request signal (arrow 2200) of the master module 22. The bus occupancy permitting signal (arrow 1220) is suppressed until the data transfer from the slave module 31 is completed. At this time, the response signal (arrow 3102) issued by the slave module 31 is the master module 2 to be received.
1 is not received because it terminates access, but it is not accidentally received by another module and does not affect the subsequent bus operation.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. The master modules 21, 22, 23 send a bus occupation request signal 5 to the bus arbiter 1. Bus arbiter 1
After detecting that the bus busy signal is off, the bus occupation permission signal 6 is transmitted to the master module having the highest priority. That is, the bus arbiter 1 does not newly allow another master module to occupy the shared base while the bus busy signal is ON.

Here, it is assumed that the master module 21 is permitted to occupy the shared bus. When the master module 21 receives the occupancy permission, the master module 21 turns on the bus busy signal 4 for the means indicating the occupancy of the data bus, and issues the data transfer signal 8 to the slave module 31 trying to access. When the slave module 31 sends a data transfer request 316 to the subsystem 315, a flag 31 indicating that the slave module 31 is in a data transfer operation.
1 turns on the bus busy signal 4. When the slave module 31 receives the response signal 317 from the subsystem 315, the slave module 31 returns the response signal 7 to the master module 21, and the flag 31 turns off the bus busy signal 4. Upon receiving the response signal, the master module turns off the bus busy signal 4 and opens the data bus.

Next, the configuration and operation of each device will be described.

FIG. 9 shows the configuration of the bus arbiter 1. Bus occupancy request signals 521, 5 from the master modules 21, 22, 23
22, 523 are connected to the priority determination circuit 100, outputs 1001, 1002, 1003 of the priority determination circuit 100 are connected to inputs of the register 101, and outputs of the register 101 are connected to the bus occupation permission signals 621, 622, 623. Has been done. The clock input 1011 of the register 101 is turned on by the AND gate 102 at the timing when the clock 1031 of the output of the internal clock generation circuit 103 is turned on only when the bus busy signal 4 is turned off.

Of the bus occupation request signals 521, 522, 523 from the master modules 21, 22, 23, the signals 1001, 1002, 100 corresponding to the module with the highest priority.
Only 3 is output regardless of the state of the bus busy signal. At that time, when the bus busy signal 4 turns off, the clock input 1011 of the register 101 turns on and the register 101
Is set. That is, the signals 1001, 1002
The state of 1003 is bus occupation permission signals 621, 622, 6
It will be reflected in 23. Bus occupation permission signal 62
Master module 21, which received 1,622,623
Since the bus busy signal 4 is turned on in Nos. 22 and 23, the register 101 is not reset while the bus is occupied and the other module bus occupancy permission signals 621, 622 and 623 are not issued.

FIG. 10 shows the configuration of the master modules 21, 22, 23. In this figure, master module 2
Only one configuration is shown.

The control unit 210 of the master module 21 turns on the bus operation activation signal 2115 when the need for bus transfer arises. The flip-flop 2110 latches the signal 2115 at the next clock 2114 and turns on the bus occupation request signal 521. After that, the bus occupation permission signal 621
Turns on, and flip-flop 2112 turns on AND gate 2
Set by 111. Flip Flop 2112
Is connected to the input of the flip-flop 2113 and the input of the bus busy signal driver 2117.
The output of the flip-flop 2113 is connected to the access activation signal 821 and the access response signal 721 from the bus.
Is connected to the clear inputs of the flip-flops 2110, 2112, and 2113, and the control unit 210.

Upon receiving the bus occupation permission signal 621, the master module 21 immediately turns on the bus busy signal 421, and during normal operation, outputs the bus busy signal 4 to the open collector gate 2117 until the access response signal 721 is received.
Keeps on.

FIG. 11 shows the configuration of the slave modules 31, 32, 33, and here, only the configuration of the slave module 31 is shown.

The address decoder 3110 decodes the address on the address bus 10, detects the address assigned to its own module, and turns on the signal 31101. AND gate 3
1, 11 and 11 indicate that the access request signal 831 is an access to the own module.
And the flip-flop 3112 is set at the timing of the output 31171 of the internal clock generation circuit 3117. Flip Flop 3112, 311
3, 3115 and 3116 have a shift register structure and are sequentially set by the response signal 317 from the clock 31171 and the subsystem 315. When the flip-flop 3112 is set, the next clock 31
At 171, the flip-flop 3113 is set, and the access request signal 316 to the subsystem 315 is issued. The flip-flop 3115 has an access response signal 3
When 17 turns on, it is set and the next clock 31171
At this point, flip-flop 3116 is set. The output of the flip-flop 3116 is the access response signal 73.
If the flip-flop 3116 is set to 1, the access response signal 731 is turned on.

Each flip flop 3112, 3113, 3115, 3
The output of 116 is connected to the OR gate 3118, and the OR
The output of the gate 3118 is the open collector gate 311.
9 and the gate 3119 has a bus busy signal 431.
It is connected to the.

Flip-flop 311 in slave module 31
When any of 2, 3113, 3115, and 3116 is in the set state, that is, when the slave module 31 accepts an access request and is operating, the bus busy signal 43
1 is turned on.

The following cases are also possible. When the master module confirms that the bus busy signal is off, it turns on the bus busy line and sends a bus occupation request signal 5 to the bus arbiter 1. When a plurality of bus occupancy request signals are received, the bus arbiter 1 transmits the bus occupancy permission signal 6 to the master module having the highest priority. When there is one bus occupation request signal, the bus occupation permission signal 6 is transmitted to the master module which has transmitted the bus occupation request signal.

Here, it is assumed that the master module 21 is permitted to occupy the shared bus. When the master module 21 issues the data transfer signal 8 to the slave module 31 that intends to access, the master module 21 performs the same operation as that of the above-described embodiment. The master module which is not accessing does not send the access request signal to the bus arbiter 1 when the bus busy signal is ON.

The configuration and operation of each device in this case will be described.

FIG. 11 shows the configuration of the bus arbiter 1. Bus occupancy request signals 521, 5 from master modules 21, 22, 23
Of the 22 and 523, only one signal 1001, 1002, 1003 corresponding to the module with the highest priority is output, and when the bus busy signal is OFF.

FIG. 12 shows the configuration of the master modules 21, 22, 23. In this figure, the master module 21
Only the configuration of is shown.

The control unit 210 of the master module 21 turns on the bus operation activation signal 2115-a only when the bus busy signal is OFF when the need for bus transfer arises. The subsequent operation is the same as that of the above embodiment.

The configuration and operation of the slave module are the same as those in the above embodiment.

〔The invention's effect〕

According to the present invention, during the data transfer between the master module and the accessed slave module, even if the master module interrupts the access, the slave module prevents the bus from being released. Since another master module can be prevented from starting access and data transfer can be prevented from being performed between unintended modules, the system reliability can be improved.

[Brief description of drawings]

FIG. 1 is a diagram showing the points of the present invention, FIG. 2 is a conventional configuration diagram, FIG. 3 is a diagram showing a normal bus operation, and FIG. 4 is a diagram showing conventional problems. Configuration diagram used, No. 5,
6 shows the operation of FIG. 4, and FIG. 7 shows the operation for solving the problem. FIG. 8 is a block diagram of the bus arbiter, FIG. 9 is a block diagram of the master module, and FIG. 10 is a block diagram of the slave module. 11th
FIG. 12 is a block diagram of the bus arbiter, and FIG. 12 is a block diagram of the master module. 1 ... Bus arbiter, 4 ... Bus busy signal, 5 ... Bus occupation request signal, 6 ... Bus occupation permission signal, 21-23
…… Master module, 31-33 …… Slave module, 311 …… Flag, 315 …… Sub system

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshiyuki Ide 5-2-1 Omika-cho, Hitachi-shi, Ibaraki Inside the Omika Plant, Hitachi, Ltd. (56) Reference JP-A-60-97457 (JP, A) JP 62-187955 (JP, A) JP 57-73436 (JP, A)

Claims (3)

[Claims] 1. A shared bus including a data bus, an address bus and a bus busy line, a plurality of access activation modules and access passive modules connected to the shared bus, and a shared bus connected to the shared bus. In a data transmission device provided with a bus occupancy control device for controlling the occupancy of the bus, the access activation module has means for turning on the bus busy line while accessing data, and the access activation module accesses the bus busy line. The access passive module has means for turning on the bus busy line while data is being accessed, and when the bus busy line is turned on, the bus occupation control device is However, the data transmission device is characterized in that the use of the shared bus is not newly permitted. 2. A shared bus including a data bus, an address bus and a bus busy line, a plurality of access activation modules and access passive modules connected to the shared bus, and bus occupancy control connected to the shared bus. In a data transmission method for controlling occupancy of the shared bus by a device, the access activation module turns on the bus busy line while accessing data to the access passive module, and is accessed from the access activation module. The access passive module also turns on the bus busy line while data is being accessed, and when the bus busy line is on, the bus occupancy control device newly shares the bus with other access activation modules. A data transmission method characterized by not allowing the use of the bus. 3. A shared bus including a data bus, an address bus and a bus busy line, a plurality of access activation modules and access passive modules connected to the shared bus, and bus occupancy control connected to the shared bus. In a data transmission method for controlling occupancy of the shared bus by a device, the access activation module turns on the bus busy line.
Then, an access request signal is transmitted to the bus occupancy control device via the shared bus, the bus occupancy control device permits one access activation module to occupy the shared bus, and the access activation module permitted to occupy the shared bus. Continues to turn on the bus busy line until the access with the access passive module is completed, the access passive module also turns on the bus busy line while the data is being accessed, and the other access activation module uses the bus busy line. The line is O
When N, the data transmission method is characterized in that an access request signal is not transmitted to the bus occupation control device.