JPH0649936B2 - Bias spattering device - Google Patents
Bias spattering deviceInfo
- Publication number
- JPH0649936B2 JPH0649936B2 JP61029191A JP2919186A JPH0649936B2 JP H0649936 B2 JPH0649936 B2 JP H0649936B2 JP 61029191 A JP61029191 A JP 61029191A JP 2919186 A JP2919186 A JP 2919186A JP H0649936 B2 JPH0649936 B2 JP H0649936B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- dielectric loss
- bias
- bias sputtering
- adjusting member
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 37
- 238000004544 sputter deposition Methods 0.000 claims description 32
- 238000009826 distribution Methods 0.000 claims description 24
- 239000010408 film Substances 0.000 claims description 22
- 239000010409 thin film Substances 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 7
- 150000002500 ions Chemical class 0.000 claims description 4
- 229910010293 ceramic material Inorganic materials 0.000 claims 1
- 239000011368 organic material Substances 0.000 claims 1
- 238000005530 etching Methods 0.000 description 16
- 229910004298 SiO 2 Inorganic materials 0.000 description 7
- 230000008021 deposition Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- 229920001721 polyimide Polymers 0.000 description 4
- 239000009719 polyimide resin Substances 0.000 description 4
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 239000010453 quartz Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 238000000427 thin-film deposition Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- -1 argon ions Chemical class 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003779 heat-resistant material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000004071 soot Substances 0.000 description 1
- 239000013077 target material Substances 0.000 description 1
Landscapes
- Physical Vapour Deposition (AREA)
- Electrodes Of Semiconductors (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は、減圧下のグロー放電によって発生するプラズ
マのイオンのスパッタリング作用を利用して、半導体基
板などの基板上に、導電性，絶縁性の薄膜を形成するバ
イアススパッタリング装置に関する。DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention utilizes the sputtering action of ions of plasma generated by glow discharge under reduced pressure to provide a conductive or insulating material on a substrate such as a semiconductor substrate. The present invention relates to a bias sputtering apparatus for forming a thin film.
（従来技術とその問題点） バイアススパッタリングによって、基板表面にＡｌやSi
O2の薄膜を形成する技術は周知である。殊に、パターニ
ングの終った半導体基板上に、ステップカバレージ性の
良いSiO2薄膜、または更にすゝんで、ステップを完全に
埋めた、表面の平面性の良いSiO2薄膜を形成したいとき
などにバイアススパッタリング技術はすぐれた能力を発
揮し、半導体装置製造上ますます重要視されている。(Prior art and its problems) By bias sputtering, Al or Si on the substrate surface
Techniques for forming thin films of O 2 are well known. In particular, end and on a semiconductor substrate of patterning, the step coverage of good SiO 2 thin film or even a do soot, step a completely filled, bias sputtering, etc. When it is desired to form the flatness good SiO 2 thin film surfaces The technology exerts excellent capabilities and is increasingly regarded as important in semiconductor device manufacturing.
第４図に従来のバイアススパッタリング装置の概要の正
面断面図を示す。接地された真空容器１には、それぞれ
絶縁材２１，３１を介して、ターゲット５を保持し磁石
２２を内蔵する陰極２と、基板４を保持するバイアス電
極３と、が取付けられている。陰極２は、整合器９を介
して高周波電源７に接続され、バイアス電極３は、整合
器１０を介して高周波電源８に接続されている。２３，
３３は両電極のシールド板である。FIG. 4 shows a schematic front sectional view of a conventional bias sputtering apparatus. A cathode 2 that holds a target 5 and contains a magnet 22 and a bias electrode 3 that holds a substrate 4 are attached to the grounded vacuum container 1 via insulating materials 21 and 31, respectively. The cathode 2 is connected to a high frequency power source 7 via a matching unit 9, and the bias electrode 3 is connected to a high frequency power source 8 via a matching unit 10. 23,
Reference numeral 33 is a shield plate for both electrodes.
図示しないガス導入系から、所定流量の所定ガスが導入
され、図示しない排気系から排気されて、真空容器内の
圧力が所定値に保たれ、両高周波電源７，８から高周波
電力が両電極に印加されるとき、両電極間の空間にグロ
ー放電を生じ、プラズマ中のイオンによってターゲット
５がスパッタリングされ、それと同材質の薄膜が基板４
上に堆積する。A predetermined gas of a predetermined flow rate is introduced from a gas introduction system (not shown) and exhausted from an exhaust system (not shown) to maintain the pressure in the vacuum container at a predetermined value, and high frequency power from both high frequency power supplies 7 and 8 is applied to both electrodes. When applied, a glow discharge is generated in the space between both electrodes, the target 5 is sputtered by the ions in the plasma, and a thin film of the same material as the target 5 is formed on the substrate 4.
Deposit on top.
周知のように、バイアススパッタリングにおいては、上
記の薄膜の堆積はエッチングと同時に進行する。基板４
の表面への「潜在的な膜堆積量」と、表面の「エッチン
グ量」との差が、「実効的な薄膜堆積量」となるもので
ある。As is well known, in bias sputtering, the deposition of the above thin film proceeds simultaneously with etching. Board 4
The difference between the "potential film deposition amount" on the surface of the and the "etching amount" of the surface is the "effective thin film deposition amount".
（バイアススパッタリングのすぐれたステップカバレー
ジ性は、このエッチング動作によってもたらされること
は周知である）。(It is well known that the excellent step coverage of bias sputtering is provided by this etching operation).
第２図の曲線Ａは、従来の装置を用いてSiO2のバイアス
スパッタリング（従ってターゲット材料はSiO2）を行う
場合の、基板４の表面のエッチング速度分布の１例を示
す。縦軸にエッチング速度 ／min、横軸に基板４の表面の中心（第４図の中心線３
０の位置）からの距離をとっている。A curve A in FIG. 2 shows an example of the etching rate distribution on the surface of the substrate 4 when performing bias sputtering of SiO 2 (therefore, the target material is SiO 2 ) using the conventional apparatus. The vertical axis represents the etching rate / min, and the horizontal axis represents the center of the surface of the substrate 4 (center line 3 in FIG. 4).
(Position 0).
（このときのターゲット５は直径１０″，厚さ6.5mm、
基板４は直径４″のシリコンウエハ、両電極間距離は６
５mmであり、使用ガスはアルゴン、圧力は５×１０-3To
rr、陰極２には13.56ＭHzの1.9Ｗ／cm2、バスアス電極
３には13.56ＭHzの12.8Ｗ／cm2の高周波電力を投入。） この例によれば、エッチング速度の分布は直径８０mm内
で±１８％であるが、この値はほゞ一般的な従来装置の
値と言うことができる。この曲線Ａは、第４図の装置で
電源８を殺し、バイアス電極３をアース電位に落して、
電源７のみを生かしてスパッタリングを行ったときの基
板４の表面のSiO2堆積膜膜厚toから、電源８をも生かし
て正規のバイアススパッタリングを行ったときの、同様
のSiO2堆積膜膜厚ｔを差引いて得た（to-t）のグラフで
ある。(The target 5 at this time has a diameter of 10 ″, a thickness of 6.5 mm,
The substrate 4 is a silicon wafer with a diameter of 4 ", and the distance between both electrodes is 6
5 mm, used gas is argon, and pressure is 5 × 10 −3 To
rr, 13.56MHz of 1.9 W / cm 2 in the cathode 2, and high frequency power of 12.8W / cm 2 of 13.56MHz to Basuasu electrode 3. According to this example, the distribution of the etching rate is ± 18% within a diameter of 80 mm, but this value can be said to be the value of a general conventional apparatus. This curve A is obtained by killing the power supply 8 and dropping the bias electrode 3 to the ground potential in the device of FIG.
Of SiO 2 deposition MakumakuAtsu to the surface of the substrate 4 when performing sputtering utilizing only the power 7, when performing the normal bias sputtering also taking advantage of the power source 8, the same SiO 2 deposition MakumakuAtsu It is a graph of (to-t) obtained by subtracting t.
一般に、基板４の表面への「潜在的な膜堆積」の膜厚分
布の方は、「エッチング量」の分布と比較すると遥かに
良好であり、そのため、「実効的な薄膜堆積」の膜厚分
布は、「エッチング量」の分布即ち先述のＡ曲線の時間
積分に支配され、そのため、従来の装置のバイアススパ
ッタリングで得られる基板４の表面の薄膜の膜厚分布は
一般に極めて悪いものとなる。そしてもし、より良好な
膜厚分布を得ようとすれば、印加するバイアス電圧の大
きさ、基板４の直径、等の諸条件は極めて強い制約を受
け、しかも、得られる結果はあまり芳しいものでないと
いう問題を抱えている。Generally, the film thickness distribution of “latent film deposition” on the surface of the substrate 4 is much better than the distribution of “etching amount”, and therefore the film thickness of “effective thin film deposition” is large. The distribution is dominated by the distribution of the "etching amount", that is, the time integration of the above-mentioned A curve, so that the film thickness distribution of the thin film on the surface of the substrate 4 obtained by the bias sputtering of the conventional apparatus is generally extremely poor. And if a better film thickness distribution is to be obtained, various conditions such as the magnitude of the bias voltage to be applied, the diameter of the substrate 4 and the like are extremely restricted, and the obtained result is not very satisfactory. I have a problem.
（発明の目的） 本発明は、基板表面に堆積する薄膜の膜厚分布の良好な
バイアススパッタリング装置の提供を目的とする。(Object of the Invention) An object of the present invention is to provide a bias sputtering apparatus in which the film thickness distribution of a thin film deposited on a substrate surface is good.
（発明の構成） 本発明は、真空容器内に、ターゲットを保持する陰極
と、基板を保持するバイアス電極とを対向設置し、放電
で生ずるプラズマのイオンのスパッタリング作用を利用
して、該ターゲットの材料の薄膜を該基板表面に堆積す
るバイアススパッタリング装置において、該基板と該バ
イアス電極の間に、基板表面の誘電損失の分布を調整し
て該基板表面の堆積膜の膜厚分布を調整する部材であっ
てバイアス電極より高い誘電損失を生じる誘電損失調整
部材が設けられているバイアススパッタリング装置によ
って前記目的を達成したものである。(Structure of the Invention) In the present invention, a cathode for holding a target and a bias electrode for holding a substrate are installed in opposition to each other in a vacuum container, and the sputtering action of the ions of plasma generated by discharge is utilized for the target. In a bias sputtering apparatus for depositing a thin film of material on the surface of a substrate, a member for adjusting the distribution of dielectric loss on the surface of the substrate between the substrate and the bias electrode to adjust the film thickness distribution of the deposited film on the surface of the substrate. The object is achieved by a bias sputtering apparatus provided with a dielectric loss adjusting member that causes a dielectric loss higher than that of the bias electrode.
（実施例） 以下、本発明の実施例を図に基いて説明する。第１図は
本発明の実施例のバイアススパッタリング装置の概要の
正面断面図を示すものであって、第４図と同じ部材には
同じ符号を付してあり、その説明は省略する。(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 shows a schematic front sectional view of a bias sputtering apparatus according to an embodiment of the present invention. The same members as those in FIG. 4 are designated by the same reference numerals, and the description thereof will be omitted.
第１図が第４図と異なる部分は、基板４の裏面とバイア
ス電極３の表面６との間に挿入された２mm厚さの石英板
４１と誘電損失調整部材４２が存在することである。本
実施例で使用された誘電損失調整部材４２は、均一な厚
さの平板状の部材の中央部をくり貫いたような形状のも
のである。即ち、誘電損失調整部材４２は、中央部に大
きな開口を有する他は厚さの一定な環状板である。そし
て、その厚さは、0.2mm〜0.5mm程度の範囲で適宜選定さ
れるが、例えば0.3mmの厚さが好適に採用される。1 is different from FIG. 4 in that there is a 2 mm thick quartz plate 41 and a dielectric loss adjusting member 42 which are inserted between the back surface of the substrate 4 and the front surface 6 of the bias electrode 3. The dielectric loss adjusting member 42 used in this embodiment has a shape such that a flat plate member having a uniform thickness has a hollowed central portion. That is, the dielectric loss adjusting member 42 is an annular plate having a constant thickness except that it has a large opening in the center. The thickness is appropriately selected within a range of about 0.2 mm to 0.5 mm, but a thickness of 0.3 mm is preferably adopted.
第１図の装置を使って、先述したと同様にSiO2膜のバイ
アススパッタリングをした場合に得られる先述同様のエ
ッチング速度分布を、曲線Ｂとして第２図に竝記した。
曲線Ｂはエッチング速度が直径９０mmの基板上で±９％
以内に改善されることを示している。本例の装置ではポ
リイミド樹脂製の誘電損失調整部材４２の厚さを、0.2m
m〜0.5mmの間に選定するとき膜厚分布改善の効果が認め
られ、この範囲の外では、第１図の曲線Ａに示すものと
同様のエッチング速度の分布を示し、あまり効果は無か
なった。また場合によっては、エッチング速度のばらつ
きが大きくなってさらに不均一となり、逆効果を示す結
果となった。The same etching rate distribution as that obtained when bias sputtering of the SiO 2 film was performed using the apparatus shown in FIG. 1 in the same manner as described above is shown as curve B in FIG.
Curve B has an etching rate of ± 9% on a substrate with a diameter of 90 mm.
It will be improved within. In the device of this example, the thickness of the dielectric loss adjusting member 42 made of polyimide resin is set to 0.2 m.
When selected between m and 0.5 mm, the effect of improving the film thickness distribution is recognized. Outside this range, the etching rate distribution is similar to that shown by the curve A in FIG. 1, and there is not much effect. It was Also, in some cases, the variation in etching rate became larger and became more non-uniform, resulting in the opposite effect.
ポリイミド樹脂製の誘電損失調整部材４２の表面がプラ
ズマに晒されると、エッチングされて汚染物質を生じ、
基板表面の堆積膜に混入して薄膜の品質を低下させるの
で、石英板４１が環状板４２の表面を覆うようにして置
かれている。覆い用の板４１としてターゲット５と同材
質の材料を選ぶとき前記の汚染が防止される理由は説明
するまでもなく明らかである。When the surface of the dielectric loss adjusting member 42 made of polyimide resin is exposed to plasma, it is etched to generate contaminants,
The quartz plate 41 is placed so as to cover the surface of the annular plate 42 because it mixes with the deposited film on the surface of the substrate and deteriorates the quality of the thin film. The reason why the above-mentioned contamination is prevented when the material of the same material as the target 5 is selected as the cover plate 41 is obvious without explanation.
ポリイミド樹脂製の誘電損失調整部材４２を挿入すると
きに、何故エッチング速度分布が曲線Ａから曲線Ｂに改
善されるか、その理論的な理由は明らかでない。しか
し、ポリイミド樹脂の代りに、高誘電損失材料、例えば
tonδの大きい種類のアルミナ環状板の適宜厚さのもの
でも同様の改善効果が得られ、誘電損失の小さい石英板
では殆んど改善されないなどから、基板表面の誘電損失
の分布がエッチング速度分布と密接に関連することは明
らかとなっている。そして基板部のみを第３図に略示す
るように、高誘電損失で板状の誘電損失調整部材４２
の、厚さを不等厚に調整して基板裏面の誘電損失値を微
細に調節し、それによって堆積膜の膜厚分布を均一化す
ることも可能であることが判明した。The theoretical reason why the etching rate distribution is improved from the curve A to the curve B when the dielectric loss adjusting member 42 made of the polyimide resin is inserted is not clear. However, instead of a polyimide resin, a high dielectric loss material such as
A similar improvement effect can be obtained even with an alumina annular plate having a large ton δ of an appropriate thickness, and it is hardly improved with a quartz plate having a small dielectric loss.Therefore, the distribution of the dielectric loss on the substrate surface is It is clear that they are closely related. As shown in FIG. 3 only in the substrate portion, a plate-like dielectric loss adjusting member 42 having a high dielectric loss.
It was found that it is also possible to make the thickness distribution of the deposited film uniform by finely adjusting the dielectric loss value on the back surface of the substrate by adjusting the thicknesses to be unequal.
なお高誘電損失で板状の誘電損失調整部材４２は、膜堆
積工程の高周波電力で加熱されること、基板がアルゴン
イオンでエッチングされることによって高温になる。従
って、こゝには耐熱材料を使用する必要がある。The plate-shaped dielectric loss adjusting member 42 having a high dielectric loss is heated to a high temperature by being heated by the high frequency power in the film deposition process and by etching the substrate with argon ions. Therefore, it is necessary to use a heat resistant material here.
上記の構成のバイアススパッタリング装置を用いるとき
は、エッチング速度の分布を自由に調節できるため、前
記した「潜在的な膜堆積」の膜厚分布をもこれで補正
し、理想的な「実効的な膜堆積」の膜厚分布を現出する
ことができる。When the bias sputtering apparatus having the above-mentioned configuration is used, the distribution of the etching rate can be freely adjusted, so the film thickness distribution of the "latent film deposition" described above is also corrected by this, and an ideal "effective The film thickness distribution of "film deposition" can be revealed.
さらに、バイアススパッタリングにおけるバイアスの深
さ（それはバイアス電極３に印加される高周波電圧の大
きさである）を充分に大きくすることが可能となり、前
述したバイアススパッタリング特有の機能、即ちステッ
プカバレージ性のよい膜生成の機能や、ステップを完全
に埋めて更に表面の平面性を良くした膜生成を行なう機
能を、極めて高いものにすることができる。Further, it becomes possible to sufficiently increase the depth of the bias in the bias sputtering (which is the magnitude of the high frequency voltage applied to the bias electrode 3), and the function peculiar to the bias sputtering described above, that is, the step coverage property is excellent. The function of film formation and the function of completely filling the steps to further improve the planarity of the surface can be extremely enhanced.
なお、上記の実施例は電極構成が平行平面型である場合
であったが、同軸円筒型構成でも同様の効果が得られ
る。In the above embodiment, the electrode configuration is a parallel plane type, but the same effect can be obtained with a coaxial cylindrical type configuration.
（発明の効果） 本発明は、基板表面に堆積する薄膜の膜厚分布の良好な
バイアススパッタリング装置を提供する効果がある。(Effects of the Invention) The present invention has an effect of providing a bias sputtering apparatus in which the film thickness distribution of a thin film deposited on a substrate surface is good.
第１図は、本発明の実施例のバイアススパッタリング装
置の概要を示す正面断面図。 第２図は、従来及び本発明の実施例のバイアススパッタ
リング時の基板表面のエッチング速度分布を示す図。 第３図は本発明の別の実施例の、基板部の正面断面図。 第４図は従来のバイアススパッタリング装置の概要の正
面断面図。 １……真空容器、２……陰極、３……バイアス電極、４
……基板、５……ターゲット、７，８……高周波電源、
４２……誘電損失調整部材。FIG. 1 is a front sectional view showing an outline of a bias sputtering apparatus according to an embodiment of the present invention. FIG. 2 is a diagram showing the etching rate distributions on the substrate surface during bias sputtering in the conventional example and the example of the present invention. FIG. 3 is a front sectional view of a substrate portion of another embodiment of the present invention. FIG. 4 is a schematic front sectional view of a conventional bias sputtering apparatus. 1 ... vacuum container, 2 ... cathode, 3 ... bias electrode, 4
...... Substrate, 5 ...... Target, 7, 8 …… High frequency power supply,
42 ... Dielectric loss adjusting member.
Claims (6)
と、基板を保持するバイアス電極とを対向設置し、放電
で生ずるプラズマのイオンのスパッタリング作用を利用
して、該ターゲットの材料の薄膜を該基板表面に堆積す
るバイアススパッタリング装置において、該基板と該バ
イアス電極の間に、基板表面の誘電損失の分布を調整し
て該基板表面の堆積膜の膜厚分布を調整する部材であっ
てバイアス電極より高い誘電損失を生じる誘電損失調整
部材が設けられていることを特徴とするバイアススパッ
タリング装置。1. A cathode holding a target and a bias electrode holding a substrate are installed to face each other in a vacuum container, and a thin film of a material of the target is formed by utilizing a sputtering action of ions of plasma generated by discharge. In the bias sputtering device for depositing on the surface of the substrate, the bias is a member for adjusting the distribution of the dielectric loss on the surface of the substrate between the substrate and the bias electrode to adjust the film thickness distribution of the deposited film on the surface of the substrate. A bias sputtering apparatus comprising a dielectric loss adjusting member that produces a dielectric loss higher than that of an electrode.
る表面は、ターゲットと同質の材料で覆われている特許
請求の範囲第１項記載のバイアススパッタリング装置。2. The bias sputtering apparatus according to claim 1, wherein the surface of the dielectric loss adjusting member exposed to the plasma is covered with the same material as the target.
いて局在的である特許請求の範囲第１又は２項記載のバ
イアススパッタリング装置。3. The bias sputtering apparatus according to claim 1, wherein the dielectric loss adjusting member is localized on the surface of the substrate.
て不等厚である特許請求の範囲第１又は２項記載のバイ
アススパッタリング装置。4. The bias sputtering apparatus according to claim 1, wherein the dielectric loss adjusting member has an unequal thickness on the back surface of the substrate.
特許請求の範囲第１又は２項記載のバイアススパッタリ
ング装置。5. The bias sputtering apparatus according to claim 1, wherein the dielectric loss adjusting member is an organic material.
である特許請求の範囲第１又は２項記載のバイアススパ
ッタリング装置。6. The bias sputtering apparatus according to claim 1, wherein the dielectric loss adjusting member is a ceramic material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61029191A JPH0649936B2 (en) | 1986-02-13 | 1986-02-13 | Bias spattering device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61029191A JPH0649936B2 (en) | 1986-02-13 | 1986-02-13 | Bias spattering device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62188777A JPS62188777A (en) | 1987-08-18 |
| JPH0649936B2 true JPH0649936B2 (en) | 1994-06-29 |
Family
ID=12269306
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61029191A Expired - Lifetime JPH0649936B2 (en) | 1986-02-13 | 1986-02-13 | Bias spattering device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0649936B2 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0772344B2 (en) * | 1988-06-23 | 1995-08-02 | 帝人株式会社 | Opposed target type sputtering system |
| JPH0788575B2 (en) * | 1991-06-14 | 1995-09-27 | 株式会社芝浦製作所 | Sputtering equipment |
| JPH0788574B2 (en) * | 1991-06-14 | 1995-09-27 | 株式会社芝浦製作所 | Reactive high frequency sputtering equipment |
| JPH0816267B2 (en) * | 1991-06-14 | 1996-02-21 | 株式会社芝浦製作所 | Reactive high frequency bias sputtering system |
| JPH0943929A (en) * | 1995-05-19 | 1997-02-14 | Matsushita Electric Ind Co Ltd | Electrophotographic copying machine |
| JP2002004042A (en) * | 2000-06-21 | 2002-01-09 | Semiconductor Leading Edge Technologies Inc | RF sputtering equipment |
| CN104947048A (en) * | 2015-05-14 | 2015-09-30 | 宁波时代全芯科技有限公司 | Coating device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0243824B2 (en) * | 1985-02-22 | 1990-10-01 | Hitachi Ltd | SUPATSUTARINGUSOCHI |
-
1986
- 1986-02-13 JP JP61029191A patent/JPH0649936B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62188777A (en) | 1987-08-18 |
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