JPH0650429B2 - Electrochromic matrix display - Google Patents

Description

The present invention relates to an electrochromic matrix display device.

[Outline of disclosure]

In the electrochromic matrix display device disclosed in the present specification, the display electrode is supported by the substrate of the corresponding one of the transistors arranged at the intersection of the gate line and the drive line, and each transistor is connected to the corresponding drive line. It can be switched by a signal supplied to the corresponding gate line for passing a current through the display electrode. During a line-by-line write operation, the drive lines are alternately selected from their ends.

[Prior art]

A conventional electrochromic matrix display device has an electrochromic cell that surrounds a matrix of display electrodes, an electrolyte, a counter electrode, and a reference electrode that senses the potential of the electrolyte. The display electrode is a transistor located at the intersection of multiple gate lines and multiple drive lines.
Supported by the substrate of the corresponding one of the switches. The conventional display device further includes a gate selection unit that selects a gate line and a drive line selection unit that includes a shift register that receives data for selecting a drive line. These selection means cooperate to select the transistor / display electrode pair. Each transistor has a control electrode and can be switched by a signal applied to the control electrode of each gate line to provide the current of each drive line to the corresponding display electrode. The conventional display device further includes a write current source and the above-mentioned 2
It has means for applying a write current from the write current source to a selected one of the drive lines in order to write to the display electrode selected by the one selection means.

[Problems to be solved by the invention]

Since the above-described conventional display device is provided with only one drive line selecting means including a shift register, when the display is switched, new display cannot be performed unless the contents of the shift register are rewritten, and high-speed display is performed. There was a problem that switching could not be performed.

The present invention has been made to solve such conventional problems, and an object of the present invention is to provide an electrochromic matrix display device capable of performing display switching at high speed.

[Means for solving problems]

In order to achieve the above object, the present invention provides first and second groups of switches connected to a plurality of drive lines and selectively energizing the switches of the first and second groups, respectively. Two drive line selection means are provided so that the write drive currents are alternately supplied to the switches of the first group and the second group, and the first and second drive line selection means alternately provide an output to the switches. It is what constitutes.

Generally, the gate lines are row lines and the drive lines are column lines, but they can be reversed.

In the preferred embodiment, it is a semiconductor substrate on which a matrix of transistors is integrated. At least the drive line is formed as a conductive diffusion region in the substrate. The invention is particularly advantageous when the resistance of the lines formed by diffusion is relatively high.

Also, in the preferred embodiment, the drive line selection means comprises two select registers on either side of the drive line, each register being capable of complete line selection.

A register such as a shift register is preferred for line selection, but a decoder could be used instead.

When writing, there is no practical advantage of providing a constant write current across the drive lines simultaneously. This is because the maximum allowable current is predetermined by the physical structure of the transistor matrix and the address line, and is restricted by the electrochemical characteristics of the display device. Therefore, the write current is preferably supplied to only one of the groups of drive line switches at a time.

[Action]

Since the first and second drive line selection means alternately provide outputs to the switches connected to the drive line,
While one drive line selecting means is involved in the current writing, the other drive selecting means can prepare for the next writing, so that the next writing is performed immediately after the end of the current writing. You can

〔Example〕

The display of FIG. 1 comprises a sealed cell 10 containing an aqueous solution of an electrochromic material such as a viologen. A preferred solution is 1,1'-di-heptyl-4, as described in European Patent Application Publication No. 0083668-A1.
4'bipyridinium phosphate (1, 1'di-heptyl-
4,4'bepyridinium phosphate) and a mixture of sulfites and thallium ions. Within the cell 10 are a double reference electrode 12, a platinum black counter electrode 13 connected to a voltage source for generating a voltage Vc, and an array of identification matte silver display electrodes 14 each constituting one pixel of the display. included. For ease of explanation, only 16 display electrodes arranged in a 4 × 4 array are shown in the figure. In practice, too many electrodes are used.

The display electrodes 14 are formed for a corresponding array of field effect transistors 15, each electrode being metallurgically connected to the drain of the associated field effect transistor 15. The field effect transistor 15 is formed on a silicon substrate, and an inorganic or organic passivation layer is formed thereon. A method of manufacturing such a display device using conventional N-channel FET technology is disclosed in European Patent Application No. 82306866.3.

The writing and erasing operations of the display cell 10 are controlled by the associated display device driving circuit according to the control signal supplied from the outside. The write operation is a constant current process, and the erase operation is potentiostatic.

The constant current writing has an advantage in terms of speed, and applying the current at a constant interval corresponds to giving a constant charge to the display electrode, and thus can be easily synchronized with the line scanning operation.

Electrochromic displays store a charge as large as ² mCcm ^-2 . Leakage occurs relatively slowly because the charge is generally provided in the form of a low conductive physical deposit. Therefore, the charges accumulated in the electrodes of the electrochromic display device must be positively removed by applying a reverse current. To do this, the potentiostatic erase technique is preferred. This technology, as is well known,
It requires a reference electrode in contact with the electrolyte of the electrochromic cell. The erase voltage source monitors the potential of the reference electrode with respect to the solution and produces a defined erase voltage with respect to the reference electrode potential. The erase electrode corresponds to the potential of the non-write display electrodes in the solution, is applied to the display electrodes to be erased, and an erase current flows to remove the charge on these electrodes until the display electrodes reach the erase voltage. This technique does not overdrive the display electrodes and cause bad side reactions (eg, anodisation). Addressing for erasure is simplified by the use of potentiostatic techniques. This is because there is no harm even if the electrode that is not written is connected to the erase voltage source. This allows block erase, which erases all or part of the display by selecting a large number from each set of orthogonal lines.

Such an electrochromic matrix display device using constant current writing and potentiostatic erase is disclosed in European Patent Application Publication No. 0042893-.
It is shown in A1.

As will be described below with reference to FIG. 2, the double electrode 12 is in the "reference" mode and the "refresh" mode under the control of the reference control circuit, but these modes alternate.
The control circuit controls such that one of these two electrodes is always in the reference mode. In normal mode, the electrode is coated with sufficient viologen to stabilize its potential on the solution. While one of the electrodes 12 is in the reference mode, the other of the electrodes is erased and rewritten. The erasing of the electrodes to be refreshed is preferably done so that the amount of viologen to be rewritten next can be precisely controlled.

In FIG. 1, each electrode 14 can be individually selected for writing by the associated field effect transistor 15 acting as a switch. Electrodes 14 are identified by row and column data loaded into row select shift register 17 and dual column select shift registers 18 and 19. The row select shift register 17 controls the associated row driver 20 and the column select shift registers 18 and 19 to activate the selected row and column lines 23 and 24 connected to the corresponding gates and sources of the FET matrix. It controls the associated column drivers 21 and 22. Therefore, when the row line 23 is energized, the gate of the FET of a particular row opens (becomes conductive), and the write or erase current flowing in the column line 24 is supplied to the electrode 14 of the row.

The row lines 23 are aluminum, but the column lines 24 are conductively diffused silicon substrates.

The row driver 20 includes row selection shift registers 17 respectively.
Enhancement mode device 25 and depletion mode device 26 connected to one stage of
, Including a series of transistor pairs such as. These two devices form a line drive inverter that isolates the shift register from the row select line loading. The action of the row line 23 is basically a gate action.

The column driver 21 is more complicated in that it must supply both the erase current and the write current to the column line 24. Connecting the column line 24 to perform either operation is accomplished by a transistor switch 27 operating according to the contents of the associated shift register stage.

The write operation is selected by supplying a write drive current WDA, which is a reference current, to the gate of the transistor 29 via the write line 28. As a result, the transistor 29
Acts as a constant current source that produces a current I _W. Line 2
The multiple transistors 30 gated by 8 act as current mirrors. If the select transistor 27 is on, the constant current I _W is drawn from the associated column line 24. What is the writing process? One column of display is written at a time to turn on only one field effect transistor 15 in a particular column at a given time.

Also provided in the column driver 22 is a current source and a current mirror formed by the transistors 31 and 32. Also, a similar write drive signal WDB can be applied to line 33.
However, if the line 33 is grounded as shown by the broken line in FIG. 1, it is possible to prevent the write drive signal WDB from being applied. In this case, the current sources and current mirrors in the column driver 22 are not used.

The potentiostatic erase operation is also controlled by the row and column drivers 20 and 21 and can perform a block operation. In other words, all of the display electrodes 14 in the area to be erased, whether written or not, have the appropriate data pattern in the row select shift register 17 and the column select shift registers 18 and 19. Selected by loading. In this case, both column drivers 21 and 22 are energized. Transistor switch 27 and similar transistor switch 34 are turned on according to the contents of column select column shift registers 18 and 19, respectively.

An externally generated erase signal is applied to the gates of transistors 35 and 36 in another row connected to lines 37 and 38, and the erase drive signal, which is the potentiostatic erase voltage applied to these transistors, is selected. Given on both sides of the marked line at the same time. The potentiostatic erase voltage is the same as the above European Patent Application Publication No. 00.
Reference electrode 1 as disclosed in 42893-A1
Generated by an offset amplifier in the reference control circuit based on the solution potential sensed by 2. The offset amplifier acts as a voltage source and supplies the current necessary to maintain its output at a constant offset voltage with respect to the working reference electrode. The potentiostatic erasing operation is performed in a self-limiting manner, and no damage occurs even if the erased drive signal is applied by selecting the display electrodes that have been written and the display electrodes that have not been written.

The erase drive signal is applied to the column drivers 21 and 22 via the pair of lines 40 and 41 and the pair of lines 42 and 43. Line 40 is connected to transistor 35 and line 42 is connected to transistor 36. Lines 40, 41, 42
Every other pair of transistors and 43 is connected to a transistor, which does not make any particular difference to the operation, but merely to allow testing of the display device.

All the circuit elements shown on the right side of the broken line 44 have been described above except the counter electrode 13 on which the silicon substrate is integrated. The electrical connection to the outside is made by means of a connector provided at the terminal portion of the substrate extending from the sealed portion of the cell 10, for example indicated by reference numeral 45. The external printed connector card has the effect of creating some integrated lines in common as shown by the connection to the right of dashed line 44 in FIG.

Thus, lines 37 and 38 of dual drivers 21 and 22 are only supplied with a single erase signal and four lines 4
A common erase drive signal is applied to all of 0 to 43. In the mode of operation of the display device described above, the inputs of the shift registers 18 and 19 for column A and column B can be common, but the inputs are independent and the two registers are loaded with identification data during a normal erase operation. This improves flexibility.

Combining the display and circuitry of FIG. 1 with the interface and auxiliary circuitry of FIG. 2, the two shift registers 18 and 19 are loaded identically during a write operation.
However, if line 33 is grounded, the upper column driver 22
Since it cannot get write current, this driver remains inactive.

The erase and erase drive signals applied to lines 37 and 41 of FIG. 1 are generated by a combination of off-chip auxiliary circuitry and microprocessor interface 49 as shown in FIG. The erase drive signal, which is a potentiostatic erase voltage, is alternately derived from the two reference electrodes 12. The A reference potential and the B reference potential obtained from these two reference electrodes 12 are applied to the switch 52 via lines 50 and 51. The switch 52 always connects one reference electrode to the offset amplifier 53. The output of the offset amplifier 53 is maintained at a predetermined voltage different from the potential of the connected reference electrode 12. Therefore, the offset amplifier 53 acts as a voltage source and produces an erase current on line 54.

The reference electrode 12 alternately performs the writing operation and the erasing operation under the control of the signal on the line 55 so that the switch 52 always obtains a stable reference potential. Such a circulating operation of the reference electrode is disclosed in European Patent Application Publication No. 0042893-A1. The only difference that is disclosed in this application is that the reference cycle signal is a microprocessor
Is provided by the interface 49.

The erase current flow on line 54 is described in European Patent Application No. 83.
Monitored by current monitor circuit 56 as disclosed in 303794.8. When the current rapidly drops to zero, indicating that the potentiostatic erase process is complete, the erase complete signal is fed back to the microprocessor interface 49 via line 57, freeing the microprocessor for the next display application. You can start at.

A microprocessor when the erase operation begins with the completion of the initial reference electrode write cycle controlled by line 55 to ensure stable reference initial availability after power is initially applied to the display. Interface 49 generates an erase signal on line 62. Under the same conditions, microprocessor interface 49 provides switch 59 with an erase drive connect signal. As a result, an erase signal is generated from the current monitor 56 on the line 60, and the erase signal is supplied to the display device via the line 61 as an erase drive signal.

The write operation begins in response to a write signal provided on line 63 from interface 49. When the write signal is generated, the switch 64 is closed. As a result, the constant current source 6
5 is connected to the line 66, and a write drive signal which is a write reference current is supplied to the display device.

The write current also controls the potential Vc applied to the counter electrode via line 67 by a counter electrode control circuit 68, shown schematically as a 2-tap potentiometer.
In order to accommodate the resistance drop of the display chip and electrolyte without limiting the current, the voltage on the counter electrode rises during the writing operation and drops when writing is not done.

The data and clock signals for row shift register 17 and column shift registers 18 and 19 are provided from microprocessor interface 49 via lines 70, 71, 72 and 74.

The independence of the top and bottom column select drivers allows alternate use of these devices during line-by-line writing of the display device. In this case, line 33 is not grounded but is connected to receive write drive current WDB which is a reference current. While the row selected by the row select shift register is being written according to the data stored in the column A select shift register 18, the column B select shift register 19 loads the data to be written to the next row by the microprocessor. To be done.

Such a configuration can be obtained by combining the display device and circuit shown in FIG. 1 with the modified interface and auxiliary circuit shown in FIG. In such a configuration, line 33 is not grounded but connected to receive write drive current WDB.

Among the components shown in FIG. 3, the same components as those in FIG. 2 are designated by the reference numbers added to the reference numbers given to the components in FIG.

The difference between the configuration of FIG. 2 and the configuration of FIG. 3 is that another output line 175 is provided from the microprocessor interface 149, and the outputs are write drive currents WDA and WDB which are reference currents. A pair of switches 176 and 177 is provided. When the data on line 170 is loaded into the column A select shift register 18 of FIG. 1, the switch 17 is activated by the A / B select signal on line 175.
A reference current pulse WDA appears on line 166 via 7. The reference current W of the line 178 is changed by the same A / B selection signal.
DB flows through switch 176 to ground.

Therefore, when the data is alternately loaded into the two column selection shift registers 18 and 19, the write driving currents WDA and WDA are changed.
DB is also alternately supplied to the two column drivers 21 and 22 in the opposite phase to the data load operation.

〔The invention's effect〕

According to the present invention, when one drive line selection means is involved in the current writing, the other drive line selection means can prepare for the next writing, so that the next writing is performed as the current writing. Immediately after the end, the display can be switched at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an electrochromic matrix display device and related integrated circuits according to the present invention, and FIG. 2 is a block diagram showing an example of an auxiliary circuit and a microprocessor interface for the display device of FIG. 3A and 3B are block diagrams showing examples of preferred auxiliary circuits and microprocessor interfaces for the display device of FIG. 10 ... Electrochromic cell, 12 ... Reference electrode, 13 ... Counter electrode, 14 ... Display device, 15 ... Transistor, 21, 22 ... Column driver, 23 ... Row line, 24 ... Column line , 27, 34 ... Transistor switches, 164, 176, 177 ... Switches, 165 ...
… Constant current source.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Frank Timothy Moss 21 Hampshire, Chandraders Ford, Hocom Wood Drive, United Kingdom (56) References JP 59-178487 (JP, A) Special Kai 59-177588 (JP, A) JP 57-17926 (JP, A) JP 59-58479 (JP, A)

Claims (1)

[Claims] 1. An electrochromic cell comprising a matrix of display electrodes, an electrolyte, a counter electrode, and a reference electrode for sensing the potential of said electrolyte, a plurality of gate lines and a plurality of drive lines, said display comprising: The electrodes are supported on the substrate of corresponding ones of the transistors arranged at the intersections of the gate lines and the drive lines, and each of the transistors has a control electrode for passing the current of the drive lines to the corresponding display electrode. In an electrochromic matrix display device switchable by a signal applied to a control electrode from a corresponding gate line, a first group of switches connected to the plurality of drive lines, and a switch connected to the plurality of drive lines. A second group of switches and a first drive line selection connected to the first group of switches for selectively energizing the first group of switches A second drive line selection means connected to the second group of switches for selectively energizing the second group of switches; and writing alternately on the first and second groups of switches. Means for supplying a built-in drive current, and the first and second drive line selecting means have the first
The switches of the first group or the second group are alternately driven in response to the supply of the write drive currents to the switches of the second group and the second group, and the switches of the first group or the second group drive the first or second drive. An electrochromic circuit characterized in that the write drive current is supplied to the drive line in accordance with the output of the line selection means.
Matrix display device.