JPH0650475B2 - Semiconductor integrated circuit - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit configured by combining many functional blocks designed in advance so as to meet various specification requirements. .

[Prior Art] In recent years, semiconductor integrated circuits, particularly LSIs (large-scale integrated circuits) such as microcomputers and memories, have been widely used in various fields and are used in various fields. However, as the fields of application have expanded, conventional general-purpose LSIs are not always sufficient for constructing an efficient system, and dedicated LSIs having optimal functions for the respective fields of application have been required. To meet such demands, so-called semi-custom LSIs such as gate arrays and standard cell arrays are becoming popular.

These semi-custom LSIs are located between the full-custom LSIs intended for mass use and the general-purpose LSIs, but the manufacturing cost cannot be reduced so much with the current design technology, but the short delivery time, which is a feature of them, is utilized. It is applied to small-quantity products.

Therefore, a full custom L is also available for the above semi-custom LSI.
New technologies have come to be applied in pursuit of efficiency close to SI.

One of them is a method called a micro cell or a mega cell. This is an LSI that combines logic gates as in the past.
Instead of configuring the above, the function of one general-purpose LSI or other specific functions is treated equivalently to the basic block, and these are combined to configure the LSI. According to this method, a functional block having a specific function is configured in advance by using an optimal logic circuit that is integrated into a circuit, and the mask pattern on the integrated circuit of this functional block takes time if necessary. It is possible to design and increase the degree of integration.

One of the important problems for the semi-custom LSI that continues to develop in this way is a test method for determining whether the LSI has a normal function or performance.

Even though the semiconductor manufacturing process is advancing, the yield problem still exists. This means that some manufactured LSIs always have defects, and
It has been shown that it is essential to remove I after it has been manufactured. And, until now, similar efforts to the design and manufacture of semiconductor integrated circuits have been accumulated in the development of test methods and test equipment. However, in the case of the above-mentioned semi-custom LSI, the design related to the test cannot be started unless the specification of the LSI is determined by the user and the design of the LSI for realizing the LSI is advanced to some extent. For this reason, test design often becomes a bottleneck, delays in LSI development, or simply prepares a test input / output signal series (hereinafter referred to as a test pattern) for executing a simple functional test. As a matter of course, this kind of test method has also been devised. The method considered to be the most effective is not to consider the test pattern for testing this entire function after the functional specifications of the entire semi-custom LSI are determined, but to use the test pattern for each prepared functional block in advance. Be prepared,
Depending on which functional block the user selects
This is a method of synthesizing these prepared test patterns to obtain the entire test pattern. In order to apply such a test method, the LSI must have a function for that purpose. This conventional example will be described below.

FIG. 5 is a chip schematic diagram of a conventional semi-custom LSI devised so as to facilitate the test. As shown in the figure, this LSI chip 100 is a microcell A10.
Functional blocks 1, B102 and C103 are arranged on a semiconductor substrate, and metal wires are provided between probe electrodes (or bonding electrodes) of each functional block according to required specifications. With this configuration, as a test method of this LSI, for each functional block,
The test pattern prepared in advance can be tested by bringing the probe into contact with the probe (bonding) electrode of each functional block.

[Problems to be solved by the invention]

However, the above-mentioned conventional example has the following problems. First, a decisive drawback is that this LSI may not exert its effect at all when packaged. For example, in the case of FIG. 5, only a part of the probe electrodes prepared in each functional block is connected to the package electrode as the terminal of the LSI. Therefore, in this example, the effective test method can be applied to this LSI.
Is only a semiconductor test stage, that is, a wafer test stage. Looking at the LSI manufacturing process, it is necessary to go through a considerable process from wafer testing to packaging, and during this
It is highly conceivable to cause performance defects. In other words, in this example, an effective test method can be applied only in a very limited form.

Further, in this example, each functional block is provided with a probe electrode for testing, respectively, but since these must satisfy the mechanical accuracy, the area occupied by these is considerably large. Along with this, the fact that the number of terminals required for the test is much larger than the number of terminals of an actual integrated circuit reduces the integration degree of the entire LSI, which is one of the drawbacks.

The object of the present invention is to solve the above-mentioned problems, and when testing a specific functional block, test the terminals other than the terminals that are directly connected to the functional block. It is to provide a semiconductor integrated circuit capable of independently testing each functional block required for a semi-custom LSI by using it for transmitting and receiving various signals for.

[Means for solving problems]

A semiconductor integrated circuit of the present invention is a semiconductor integrated circuit configured by combining a plurality of predesigned functional blocks on a semiconductor substrate, and determines whether or not the functional block is being tested in a functional block including terminals. It comprises a discriminating means and a switching means for switching a terminal in the functional block to a test terminal of another functional block in accordance with a control signal from the discriminating means.

〔Example〕

 Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a system configuration diagram showing an entire embodiment of the present invention. In FIG. 1, an LSI 10 is a functional block CPU 20 prepared in advance, a serial transmission / reception unit 3
0, parallel input / output unit 40, interrupt control unit 5
0, a timer unit 60 and a bus interface unit 70 are connected to each other by an I / O bus 80 and a control bus 90. Further, as an inter-functional block signal, an interrupt request signal 61 from the timer unit 60 to the interrupt control unit 50 when the time is up, and the serial transmission / reception unit 30 to the interrupt control unit 50.
To the serial transmission / reception unit 30 and the interrupt request signal 31 at the end of the serial transfer to the serial transmission / reception unit 30 and the interrupt control unit 50 to C
An interrupt control signal 51 to the PU 20 is provided.

Therefore, in order to test each functional block individually, various signals between the I / O bus 80, the control bus 90 and the functional blocks are required. The signals of the I / O bus 80 and the control bus 90 can be supplied or monitored from the bus terminal 75 via the bus interface unit 70. Regarding various signals between the functional blocks, the interrupt request signals 31 and 61 are input to the interrupt control unit 50 as shown in FIG.
It is also entered in 0. Similarly, the interrupt control signal 51
Is input to the parallel input / output unit 40 as well as the CPU 20.

Next, the details of the configuration in the functional block will be described to clarify the operation during the test.

FIG. 2 is a block diagram of the serial transmission / reception unit 30, and FIG. 3 is a block diagram of the parallel input / output unit 40. In FIG. 2, 301 is a transmission buffer, 302 is a reception buffer, 304 is a transmission serial register, 305 is a reception serial register, 306 and 307 are transmission and reception control units, respectively, and 308 is a baud rate generator. Reference numeral 303 denotes a control register that stores information for controlling the overall operation of the unit, which has a configuration necessary for a general serial transmission / reception unit. Here, the block number data is written to the block number register 311 via the I / O bus 80 before testing this unit. This is determined by the comparator 312.
If the written block number data does not indicate this serial transmission / reception unit 30 and it is in the test state, it is not necessary to operate this unit, and the terminals of this unit can be used for testing other functional blocks. Is. This state is obtained by the AND gate 313. At this time, the terminals TXD, RXD, ▲ ▼, ▲ of this unit
▼ switches to the terminal for testing other blocks.
In this embodiment, the ▲ ▼ terminal is used as a terminal for monitoring the time base signal 62 from the time unit 60. The other signal 315 is further output to a terminal to be a spare for a signal that needs to be monitored, and 316 and 317 are spares as test signals to be supplied to other blocks. Naturally, when this unit is selected or when it is not in the test state, each terminal functions as the original terminal of the serial transmission / reception unit.

Next, in the block diagram of the parallel input / output unit 40 of FIG. 3, 401 and 411 are mode registers for designating the input / output direction of data, 402 and 412 are output latches for storing output data, and 403 and 413 are input buffers. 40
4, 414 are output buffers. This unit also has a block number register 421 and a comparator 422 for determining whether or not the own unit is selected, as in FIG. If the AND gate 430 extracts the case where the unit is not selected and is in the test state, the terminal of the unit is switched to the test terminal. For example, when the serial transmission / reception unit 30 described above is independently tested, since the parallel input / output unit is not selected, the signal applied to the terminal 416 is the AND gate 4
After passing through 15, the signal 41 is given to the baud rate generator 308 in the serial transmission / reception unit 30.
This indicates that the time base signal required for the operation test of the serial transmission / reception unit 30 can be supplied from the terminal 416 without operating the timer unit 60.
Normally, the parallel input / output unit 40 has a multi-bit terminal, but in FIG. 3, only one bit is shown as the output terminal and the input terminal in the test. The time-up interrupt request signal 61 from the timer unit 60, the transfer end request signal 31 from the serial transmission / reception unit 30, and the interrupt control signal 51 from the interrupt control unit 50 also generate respective signals, when the unit is under test operation, Terminal 40 of parallel input / output unit 40
6 and other bits having the same configuration can be output to the output terminals to monitor the operation.

Although the various interrupt request signals are output to the terminals of the parallel input / output unit 40 in the embodiment, the serial transmission / reception unit 30 shown in FIG. 2 has a spare output or input as shown in the block diagram. Since it has signal connection points, the connections between the units are changed so that the wiring can be minimized in consideration of the actual arrangement of each unit on the semiconductor substrate. For example, the time-up interrupt request signal 61 shown in FIG. It can be connected to the spare output signal line 315 and output to the TXD terminal.

FIG. 4 is a diagram showing another embodiment of means for determining whether or not the own unit in the serial transmission / reception unit 30 shown in FIG. 1 is selected. In FIG. 4, 31
5, 352 and 353 are a transmission buffer address decoder, a reception buffer address decoder and a control register address decoder, respectively. 354 is a data latch,
PALE is one of the signals included in the control bus 90, and is a timing signal indicating a period during which device addresses of various peripheral devices are transferred on the I / O bus 80. In order to operate the serial transmission / reception unit 30, the transmission buffer 301 must operate the reception buffer 302 or the control register 303 without fail. When operating these, the address transferred to the I / O bus 80 is transferred to the decoder 35.
1 to 353, the logical sum of the output signals of these decoders is calculated, and the data latch 3 is generated by the timing signal PALE.
By latching at 54, a signal indicating that the serial transmission / reception unit 30 is operating can be obtained. The AND gate 313 and other circuit blocks are constructed in exactly the same way as in FIG.

[Effects of the Invention] As described above, the present invention provides a functional block including a terminal, which is a predesigned functional block, for determining whether or not the functional block is being independently tested, and thereby the functional block. Has a means to use the terminal of its own block as a terminal for testing other functional blocks when not testing independently, so each functional block is configured in the LSI configured by combining these functional blocks. When testing independently, sufficient test terminals can be secured. Further, there is an effect that mutual wiring between the respective functional blocks for this purpose can be optimized.

[Brief description of drawings]

FIG. 1 is a system configuration diagram showing an embodiment of the present invention, and FIG.
FIG. 3 and FIG. 3 are detailed block diagrams of the serial transmission / reception unit 30 and the parallel input / output unit 40 of FIG. 1, respectively. FIG. 4 is a block diagram showing another embodiment of the present invention, and FIG. It is a figure. 10 ... LSI, 20 ... CPU, 30 ... Serial transmission / reception unit, 40 ... Parallel input / output unit, 50 ... Interrupt control unit, 60 ... Timer unit, 80 ... I / O bus,
90 ... Control bus, 100 ... LSI chip, 10
1, 102, 103 ... Microcells A, B, C, 301
... transmission buffer, 302 ... reception buffer, 303 ... control register, 304 ... transmission serial register, 305 ... reception serial register, 306 ... transmission control unit, 3
07 ... Reception control unit, 308 ... Baud rate generator, 311, 421 ... Block number register, 31
2, 422 ... Comparator, 401, 411 ... Mode register, 402, 412 ... Output latch, 403, 413 ... Input buffer, 404, 414 ... Output buffer, 351 ...
Transmission buffer address decoder, 352 ... Reception buffer address decoder, 353 ... Control register address decoder, 354 ... Data latch.

Claims (1)

[Claims] 1. A semiconductor integrated circuit configured by combining a plurality of pre-designed functional blocks on a semiconductor substrate, wherein a functional block including a terminal of the semiconductor integrated circuit among the plurality of functional blocks is provided with the terminal. A semiconductor integrated circuit characterized by having a discriminating means for discriminating whether or not a functional block including the above is under test, and a switching means for switching the terminal to a test terminal of another functional block in accordance with a control signal from the discriminating means. circuit.