JPH0650481B2 - Data processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] According to the present invention, in a LAM (Load Access Multiple) instruction, the number of the spatial register specified in the base field and one of the spatial register groups to be changed are the same number. In this case, the present invention relates to a data processing device that shortens the instruction processing time.

[Prior art]

Data processing by the multiple virtual space address method in which the contents of the space register (AR) specified by the base field of the instruction are changed to the base address (segment table origin: STO) for performing the real address conversion by the space address conversion mechanism. Schemes are known (for example,
Japanese Patent Application 63-244398).

[Problems to be Solved by the Invention]

In the data processing method as described above, when a LAM instruction for changing a plurality of consecutive ARs is executed, the base address register (STO register) holding the STO corresponding to the changed AR is also rewritten.

At this time, for example, if one of the changed AR numbers and the ARR number designated by the base field are the same number, the following problem occurs.

That is, in reading the operand data for rewriting, the segment table to be used is designated by the STO in the STO register corresponding to the space of the AR designated by the base field, and the address converted into the real address using the table is designated. However, there is a problem that the contents of the STO register having the same number as the base field are rewritten in the middle of the instruction because the AR, that is, the STO register is rewritten by the instruction.

Hereinafter, such a case will be referred to as a base change case.

Therefore, in such a base change case, in order not to rewrite the STO register in the middle of the instruction, regarding the STO register having the same number as the base field,
The end of a series of STO registers to be modified must be written.

Therefore, for that purpose, data is read from the main memory for rewriting the AR, and finally, data for writing to the AR having the same number is read again from the main memory to rewrite the STO register having the same number as the base field. Since it is necessary to obtain the data, the main data needs to be accessed twice for the same data, and there is a problem that it takes time to process the instruction.

The present invention has been made to solve the above problems.

It is an object of the present invention to provide a data processing device that shortens the instruction processing time for the LAM instruction in the base change case.

[Means for Solving the Problems]

To achieve the above object, when an instruction that changes the contents of a spatial register is executed, it is detected that the spatial register specified by the base field of the instruction is the same as the spatial register whose contents are changed. And a saving means for temporarily saving the base point address to be written in the base point address register corresponding to the space register designated by the base field by the output of the detecting means.

[Work]

According to the means described above, when the base of the LAM instruction is changed,
S corresponding to the space register with the same number as the base field
The TO register is adapted to write at the end of the STO register group corresponding to the continuous space register to be changed.

Therefore, it is detected whether or not there is a spatial register with the same number as the number specified in the base field in the consecutive spatial register groups, and when a case of base change is detected, it is written in the STO register. The STO to be stored is temporarily saved, and the saved STO is read out at the end of the series of STO register groups to be changed and written to the STO register.

〔Example〕

An embodiment of the present invention will be specifically described below with reference to the drawings.

FIG. 1 is a system configuration diagram showing an embodiment of the present invention, in which 1 is an instruction register and 2 is a general-purpose register group (GP).
R), 3 is a space register group (AR), 4 is a base address register group (STO register) that holds a base address (segment table origin: STO), 5 is a base change detection circuit, and 6 is an ALB reference address generation. circuit,
7 is a space register index buffer (ARTranslation Look
aside Buffer: ALB), 8 is an address calculator, 9 and 10
Is a control register (CR), 11 is a real address translation mechanism, 12
Space address translation mechanism, 13 is ALB hit detection circuit, 16
Is an STO save register.

When the LAM instruction is executed, the numbers of the R ₁ , R ₂ and B fields designated by the LAM instruction are fetched into the base change detection circuit 5 through the lines 19 to 21 and designated by the R ₁ and R ₂ fields. It is detected whether or not there is an AR having the same number as the B field number in the AR group to be changed.

On the other hand, a main storage device in which the contents of the AR group to be changed are stored
An operand address for accessing 18 is generated by the real address translation mechanism 11. That is, the contents of the general-purpose register 2 designated by the B field of the instruction and the D field are input to the address calculator 8 to calculate the address and generate a virtual address.

Then, in order to convert the virtual address into a real address, the STO register 4 usually having the same number as the B field is used.
The virtual address is translated into a real address by reading the base address (STO) from the input address and inputting it to the real address translation mechanism 11 via the line 29.
When the V bit of the O register 4 is "1", the STO register 4 is valid, the STO is read from the STO register 4, converted into the real address as described above, and the operand data is read from the main memory device 18. Read out. The read operand data is written into the corresponding AR3 starting from the R ₁ field number of the instruction and ending with the R ₂ field number.

On the other hand, the V of the STO register 4 which is about to be read
If the bit is "0" and invalid, the AR having the same number as the B field registered before the execution of the LAM instruction
3 is read out via the line 34 and the control register 9 or
The ALB reference address is generated by inputting it together with 10 into the ALB reference address generation circuit 6. Then, the ALB 7 is referred to by the address, and if the data including the STO is registered in the ALB output to the ALB hit detection circuit 13, the STO is read from the ALB read register 14 and the real address conversion mechanism is executed via the line 28. Enter in 11.

Further, when the ALB hit detection circuit 13 detects that the STO is not registered in the ALB when referring to the ALB 7, the AR having the same number as the B field is read out via the line 33, and the AR is read via the line 35. The STO is generated by inputting it to the space address translation mechanism 12 together with the control register 9 or 10 described above, and the STO is input to the real address translation mechanism 11 via the line 30.

Although the AR is rewritten as described above, the LAM instruction must also rewrite the STO register corresponding to the AR as described above.

The method of registering the STO register by the LAM instruction will be described below.

It is assumed that the B field specifies the mth, and the R ₁ and R ₂ fields specify the nth and the 15th, respectively. As described above, when the ARn to AR ₁₅ of the AR group 3 are rewritten by the LAM instruction, the ALB reference address generation circuit 6 is used by the ARB reference address generation circuit 6 by the data of each rewritten AR and the control register 9 or 10. To generate. ALB7 is referred by the generated ALB reference address,
The ALB hit detection circuit 13 detects whether or not data including STO is registered in ALB7. ALB7
Registered in the ALB read register 14, ST
The STO is read into the O write register 15, and the read STO is written into the STO registers from the nth to the 15th through the selector circuit 17 and the line 38.

However, when the base change detection circuit 5 detects the base change, the STO read from the ARm having the same number as the B field is saved in the STO save register 16, and at the same time, the selector circuit 17 saves the STO register in the m-th STO register. Suppress writing.

Then, the designated S other than the m-th STO register
When the registration of the STO in the TO register is completed, the base change detection circuit 5 causes the selector circuit 17 via the line 36.
Is controlled and saved in the STO save register 16
The TO is read and registered in the mth STO register, whereby the processing of the LAM instruction is completed.

When referring to the ALB7, if the data including the STO is not registered in the ALB7, the ALB hit detection circuit 13 sets “0” to the V bit of the corresponding STO register in the STO register group via the line 37. Write the ST
Disable the O register. When an invalid STO register is used in the base field of a subsequent instruction,
Perform spatial address conversion and re-register.

Further, in the case of changing the base, the V bit added to the STO save register 16 is set to "0" without directly changing the V bit in the STO register group, and when the STO save register 16 is used, V Write bit '0' to the STO register.

〔The invention's effect〕

As described above, according to the present invention, even if the number designated in the base field of the LAM instruction and one of the spatial register groups to be changed have the same number, the spatial address can be erroneously calculated when the operand address is calculated. Not again, LA
The processing time of the M instruction can be shortened.

[Brief description of drawings]

FIG. 1 is a system configuration diagram which is an embodiment of the present invention. In the figure, 1 ... Instruction register, 2 ... General-purpose register group, 3
...... Space register group, 4 …… Base point address register group,
5 ... Base change detection circuit, 6 ... ALB reference address generation circuit, 7 ... Spatial register index buffer, 8 ... Address calculator, 9, 10 ... Control register, 11 ... Real address translation mechanism, 12 ... … Spatial address translation mechanism, 13 …… A
LB hit detection circuit, 16 ... STO save register

Front page continuation (72) Inventor Katsumi Hayashida 1 Horiyamashita, Hadano-shi, Kanagawa Hitachi Computer Engineering Co., Ltd. (72) Inventor Fujio Wakui 1 Horiyamashita, Hadano City, Kanagawa Prefecture Hitachi Computer Engineering Co., Ltd.

Claims (1)

[Claims] 1. A space address conversion mechanism for converting the contents of a space register specified by a base field of an instruction into a base address for performing real address conversion, and the base address provided corresponding to the space register. In a data processing device of a multiple virtual space address system having a base point address register for holding, when a command for changing the contents of the space register is executed, the space register specified by the base field of the command is A means for detecting that it is the same as the space register to be changed, and a saving means for temporarily saving the base address to be written in the base address register corresponding to the space register designated by the base field by the output of the detecting means. And a data processing device provided with.