JPH0650593B2 - Bi-phase code demodulator - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a bi-phase code demodulation device in a digital magnetic recording / reproducing device using a magnetic tape or the like as a recording medium.

2. Description of the Related Art In recent years, a magnetic recording / reproducing apparatus using a magnetic tape, which is a large-capacity and low-cost recording medium, has made remarkable progress.

However, the essential problem of the magnetic tape is the difficulty of high-speed access caused by the winding time. To solve this problem, a method often used is to record an address signal of the magnetic tape such as a time code on a specific track on the magnetic tape, which is reproduced even when the magnetic tape is running at various speeds. Then
It is used as control information for access.

For example, an SMPTE time code or the like in a VTR corresponds thereto, and digital data such as the time code is recorded by bi-phase code modulation (also called Bi-φ, FM modulation). It is necessary for these recorded signals to be demodulated stably and reliably by following a wide tape speed of 100 times or more from low speed running to high speed running of the tape.

For this reason, many demodulation circuits for bi-phase code recording signals have been provided (for example, Take Ogawa "Video Editing Technology" (Sho 57. 4.20), Kenrokukan Shuppan, PP57-6.
0).

The main process of bi-phase code demodulation is to measure the basic period of the recorded signal with a high-frequency clock to determine the clock interval, compare the value of 3/4 of the clock interval of the previous value with the next clock interval, This is a method of extracting a clock component and detecting a "1" component in the data (for example, Japanese Patent Laid-Open No. 56-106421).

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention However, in the conventional configuration, a high-frequency clock having a constant frequency is used to measure the clock interval from the basic period of the recorded signal, regardless of the running speed of the tape. The higher the traveling speed is, the narrower the reproduction clock interval becomes, and the measurement accuracy deteriorates, which makes it difficult to obtain a stable demodulation operation. Conversely, if the frequency of the high-frequency clock is increased to improve the measurement accuracy, the measured value of the clock interval during low-speed running of the tape becomes large and the number of bits must be increased to prevent overflow of the counter and other circuits. When the tape speed changes rapidly due to acceleration, the previous clock cycle and the next clock cycle differ greatly, and the reproduction clock synchronized with the biphase code-modulated signal cannot be extracted well. However, there was a problem that normal demodulation could not be performed.

In view of the above problems, the present invention provides a bi-phase code demodulating device that follows the tape speed, maintains the same measurement accuracy at any speed, and at the same time requires a small circuit scale.

In order to achieve this object, a bi-phase code demodulating device of the present invention is a tape speed detecting means for detecting the tape speed by dividing it into N stages, and N kinds of tape speed detecting means corresponding to the output. High-frequency clock generating means for generating a high-frequency clock having a frequency of, first and second measuring means for extracting the clock from the reproduced signal, clock period value holding means, 1/4 and 1/2 value setting means, first and second It comprises a second comparing means, a reproduction clock generating means, and a "1" component detecting means for detecting a "1" component from the reproduction signal.

Operation With this configuration, the frequency of the high-frequency clock for measuring the clock interval is changed in N steps according to the tape speed, and the same number of digits (with the same accuracy) can be measured from low speed running to high speed running. The circuit can be simplified without increasing the number of digits to be measured, and the followability to abrupt changes in tape speed is improved.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a bi-phase code demodulation device according to an embodiment of the present invention.

In FIG. 1, 11 is a tape speed N stage detection circuit, 1
2 is a high frequency clock N-stage switching circuit, 13 is a first clock cycle measuring circuit, 14 is a clock cycle value holding circuit, 15 is a clock cycle 1/4 value setting circuit, 16 is a clock cycle 1/2 value setting circuit, 17 is A first comparison circuit, 18 is a second clock cycle measurement circuit, 19 is a second comparison circuit, 20 is a reproduced clock generation circuit, and 21 is a "1" detection circuit.

The operation of the bi-phase code demodulation device configured as described above will be described below.

FIG. 2 shows the timing of each part.

First, a reproduction signal edge b that captures the edge of the reproduction signal a
And a reproduction clock i output from the reproduction clock generation circuit 20 and a clock width edge c obtained by excluding the inversion edge of the "1" section is a first clock cycle measurement composed of an n-bit binary counter. It is input to the circuit 13. The first clock cycle measuring circuit 13 measures the clock cycle by the high frequency clock f output from the high frequency clock N-stage switching circuit 12 while resetting the n-bit binary counter at the clock width edge c for each clock cycle.
At this time, the clock width measurement value d obtained by the n-bit binary counter immediately before the reset is carried out by the clock cycle value holding circuit 14 also made up of an n-bit flip-flop.
To memorize.

Next, the clock cycle value T _i of the clock width holding value e stored by the clock cycle value holding circuit 14 is set to the clock cycle.
1/4 value setting circuit 15 and clock cycle 1/2 value setting circuit 16
Are set to Ti / 4 and Ti / 2, respectively, and the respective set values are input to one of the first comparison circuit 17 and the second comparison circuit 19. The first input to the other input of the first comparison circuit 17
The clock width measurement value d by the clock cycle measurement circuit 13 is input, and a 1/4 value comparison output g that matches at the position of the previous clock cycle 1/4 is obtained.

The other input of the second comparison circuit 19 has an n-bit 2
The measurement value of the second clock period measuring circuit 18 including a binary counter is input. Here, the second clock cycle measuring circuit 18 is reset by the 1 / 4-value comparison output g, and the N-stage high-frequency clock f is used for measurement, and the coincidence output of the second comparison circuit 19 is a 1/2 value. As in the comparison output h, it comes out at a position after Ti / 2 from Ti / 4 of the previous clock cycle T _i .

The reproduction clock generation circuit 20 composed of a flip-flop circuit sets the initial value to "1" and outputs 1/4 comparison output g and 1/2.
Each time the value comparison output h is input, the output state is inverted and the reproduced clock i is output.

The "1" detection circuit 21 detects the "1" component in the reproduced signal from the reproduced signal edge b and the reproduced clock i, and outputs the demodulated data j.

Here, when the tape speed changes, the tape speed N-stage detection circuit 11 detects the tape speed in a predetermined N stages from low speed to high speed, and the high-frequency clock N-stage switching circuit 12 inputs the tape speed. The high-frequency clock N-stage switching circuit 12 is adapted to generate an N-stage high-frequency clock f having an N-stage frequency according to the N-stage tape speed. Here, assuming that there is a tape speed change of 1 to 110 times, the tape speed N stage detection circuit 11 is
When the speed detection signal at each stage is set to be generated when the speed becomes 5 times, 5 times, 10 times, etc., the high frequency clock N-stage switching circuit 12 makes 1 time, 5 times, 10 times ... Corresponding to the speed detection signal at each stage, 1x, 5x, 10x ...
Generates a high frequency clock with a frequency of. Therefore, since the demodulation operation described above is performed using this high frequency clock, the tape speed tracking range of the demodulation operation is 1 to 5 at each stage.
Double, 5-10 times, 10-15 times ... Also, if the width of each speed detection step is the same, the clock cycle measurement value in each step is in the same range, and the number of digits of the counter or the like can be reduced.

Also, when the tape speed such as rising and falling suddenly changes at an accelerating rate, by setting the width of the speed detection stage according to the change, it is possible to immediately switch to the high frequency clock according to the speed. There is no large difference between the cycle value hold value and the next clock cycle measurement value, and the recovered clock can be extracted successfully.

According to the present invention, a speed detecting means for detecting a tape speed in N steps, a high frequency clock generating means for generating a high frequency clock having an N step frequency corresponding to its output, and a clock are extracted from a reproduced signal. The first and second measuring means, the clock period holding means, the 1/4 value and the 1/2 value setting means, the first and second comparing means, the reproduction clock generating means, and the reproduction signal, By providing "1" component detecting means for detecting "1" component for detecting 1 "component,
For each tape speed divided into N stages, the clock cycle measurement value can be stored in the same range, the number of digits of the counter can be reduced, and the followability when the tape speed rapidly changes with acceleration is also improved. Further, since the frequency of the high-frequency clock is variable, it is possible to realize an excellent bi-phase code demodulation device capable of coping with a wider range of tape speed changes than before.

[Brief description of drawings]

FIG. 1 is a block diagram of a bi-phase code demodulator according to an embodiment of the present invention, and FIG. 2 is a timing chart of each part of FIG. 11 ... Tape speed N-stage detection circuit, 12 ... High-frequency clock N-stage switching circuit, 13 ... First clock cycle measuring circuit, 14 ... Clock cycle value holding circuit, 15 ... Clock cycle 1/4 value setting circuit , 16 ... Clock cycle 1/2 value setting circuit, 17 ... First comparison circuit, 18 ... Second clock cycle measurement circuit, 19 ... Second comparison circuit, 20 ... Regenerated clock generation circuit, 21 ... "1" detection circuit.

Claims (3)

[Claims] 1. A tape speed detecting means for detecting the tape speed by dividing the tape speed into a plurality of stages, and a high frequency clock generating means for generating high frequency clocks of different frequencies corresponding to respective outputs of the tape speed detecting means. Means, first measuring means for measuring the clock cycle of the biphase code modulated signal by the count number of the high frequency clock, and the output of the first measuring means is the clock cycle of the biphase code modulated signal. The clock period value holding means for holding the output value immediately before being reset by the clock cycle value holding means, and the m-times value setting means for setting the values of m times and n times the clock cycle value held by the clock cycle value holding means, respectively. n-times value setting means, first comparing means for comparing the output value of the m-times value setting means and the output value of the first measuring means, and the first ratio Second measuring means reset by the comparison coincidence output of the means and counting the number of the high frequency clocks, and second comparing means comparing the output value of the n-fold value setting means with the output value of the second measuring means. Means, clock generating means for generating the clock of the biphase code modulated signal by inputting the respective comparison match outputs of the first comparing means and the second comparing means, and the clock generating means for biphase code modulating with the clock. And a "1" component detecting means for detecting "1" component from the signal and outputting "0" and "1" data synchronized with the clock. 2. The bi-phase code demodulating device according to claim 1, wherein the tape speed detecting means detects the number of rotations of the reel motor by dividing it into a plurality of stages. 3. A 1/4 times value setting means and a 1/2 times value setting means are used as the m times value setting means and the n times value setting means, respectively. The bi-phase code demodulator according to item 2.