JPH0650762B2 - Semiconductor integrated circuit - Google Patents

Description

The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit that handles analog signals.

[Prior Art] In recent years, in order to deal with diversification of control targets and optimization of control,
Programmable control devices are widely used, and in particular, these control devices have recently been integrated into one chip for the purpose of incorporating them into devices.

[Problems to be Solved by the Invention] However, in these control devices, all internal processes are performed as arithmetic and logical operations by digital amounts, and analog / digital conversion is performed externally to handle analog amounts. There was a problem that had to be done. For example, considering the case of controlling an actuator such as a motor based on the output of a sensor or the like, usually, the output of the sensor is converted into a digital amount by an A / D converter, and a control output value (digital Amount) was calculated, and this was digital-analog converted and output to the actuator. For this reason, there is a problem that the conversion unit between the analog amount and the digital amount becomes large in size, the mounting space increases, and it takes time to perform the processing such as the conversion and the operating speed decreases.

Therefore, the present invention has been made for the purpose of solving these problems, and provides a completely new semiconductor integrated circuit capable of handling analog signals in a programmable manner.

Structure of the Invention [Means for Solving Problems] In order to achieve the above object, the present invention has the following structures as means for solving the problems. That is, as illustrated in FIG. 1, it has a plurality of inputs DIN and an output DOUT, and the input D
In a semiconductor integrated circuit including a decoder DCD capable of setting a state of an output DOUT with respect to IN, and an encoder ECD having as inputs a plurality of outputs DOUT of the decoder DCD and capable of setting a state of a plurality of outputs EOUT with respect to the inputs , An analog signal ANIN input from the outside is converted into a digital signal, and the digital signal is converted into the decoder DCD.
And an analog output section AOUTP that generates an analog signal ANOUT based on the state of at least a part of the encoder output EOUT and outputs the analog signal ANOUT to the outside. This is the configuration of the characteristic semiconductor integrated circuit.

Here, the decoder DCD is a decoder having a plurality of unique outputs that can be set for a plurality of inputs, and is, for example, an AND array, a NAND array or a NOR (NAND) array in a programmable logic array (PLA). NOR) array.

The encoder ECD is an encoder that generates a code that can be set for a plurality of inputs, and is, for example, an OR (or) array or a NOR (NO) in a programmable logic array.
R) array or NAND array.

The decoder DCD and the encoder ECD are, for example, PR
OM, mask ROM, PN junction ROM, EEPROM
Alternatively, it can be realized by a fuse ROM or the like.

The analog input section AINP converts an analog signal input from outside the semiconductor integrated circuit into a digital signal,
This is a part of the input of the decoder DCD,
Various well-known modes such as a configuration in which an analog signal is binarized by a one-stage or multi-stage comparator can be considered.

In this case, the EC of the encoder is added to the analog input section AINP.
A plurality of reference units for generating a reference value based on a state of a part of the output of D, and a plurality of comparison units for comparing the generated reference value with the input analog input signal; By configuring a plurality of comparison results as the digital signal, it is possible to make the function more precise, for example, by adding hysteresis to the handling of the analog signal.

The analog output unit AOUTP is for generating an analog signal based on the state of at least a part of the output of the encoder ECD and outputting it to the outside of the semiconductor integrated circuit, and is a so-called digital-analog converter (hereinafter referred to as D / A conversion). Called a vessel). For example, the encoder ECD output can be realized by a weighted resistor or a configuration in which a resistor group forming a ladder network is connected.

In addition, as a part of the input of the decoder DCD, the encoder E
A configuration in which the output obtained by converting the state of a part of the output of the CD is used may be used. In this case, processing as a kind of microprogram can be added to the processing of the analog amount. Such conversion of a part of the encoder ECD output can be configured by using, for example, a flip-flop, a delay circuit, an exclusive OR (EOR) circuit, a counter, or the like.

[Operation] In the semiconductor integrated circuit of the present invention having the above configuration, an analog signal input from the outside is converted into a digital signal by the analog input section AINP, and the digital signal is input to the decoder DCD. The output decoded by the decoder DCD is the encoder E.
The signal is input to the CD and encoded, and at least a part of the output of the encoder ECD is converted into an analog signal by the analog output unit AOUTP and output to the outside. Moreover, the decoder DCD and the encoder ECD decode the
Since the encoding can be set (programmable), the semiconductor integrated circuit of the present invention works to determine the analog signal output based on the input analog signal under the condition according to the setting.

[Embodiment] In order to further clarify the configuration of the present invention described above, a preferred embodiment of the present invention will be described with reference to the drawings.
FIG. 2 is a block diagram showing the overall structure of a semiconductor integrated circuit as an embodiment of the present invention, and FIG. 3 is a circuit diagram showing the relationship between one set of inputs and outputs.

As shown in the figure, the semiconductor integrated circuit 1 of this embodiment is formed as a dual in-line package chip having input terminals I1 to In for inputting analog voltage signals and output terminals T1 to Tm for outputting analog voltage signals. . Inside the semiconductor integrated circuit 1, there are provided an AND plane 3 which is formed as a programmable logic array (PLA) and serves as a decoder, and two OR planes 5 and 7 which also serve as encoders. N comparators C1 to Cn, a feedback circuit 9, n D / A converters DR1 to DRn and m D / A converters DAC1
To DACm are connected.

The input terminals I1 to In are connected to the positive side inputs of the comparators C1 to Cn, respectively, and are configured to be compared with the reference voltages Vref1 to Vrefn of the negative side inputs. The two outputs of the comparators C1 to Cn which are inverted from each other and the feedback circuit 9 i
The sum of the output of the book, that is, (2n + i) becomes the input of the AND plane 3.

The k outputs of the AND plane 3 are prepared and input to the two OR planes 5 and 7, respectively. On the other hand, the OR plane 5 has n sets of v sets, that is, a total of nv outputs.
The output of the book is connected to each of the n D / A converters DR1 to DRn. D / A converters DR1 to DRn
Is connected to the minus side inputs of the above-mentioned comparators C1 to Cn, and outputs the reference voltages Vref1 to Vrefn according to the output of the OR plane 5.

The other OR plane 7 has h outputs to the feedback circuit 9 and m sets of t sets, that is, a total of mt outputs.
Of these, the output of each of the latter t lines is m D / A converters D.
It is connected to AC1 to DACm. The respective outputs of the D / A converters DAC1 to DACm are output terminals T1.
To Tm, and outputs voltage signals Vout1 to Voutm corresponding to the output of the OR plane 7 to the outside.

As briefly described above, the semiconductor integrated circuit 1 of the present embodiment inputs n analog signals, processes the analog signals, and
It has a configuration for outputting a book analog signal. this house,
In this embodiment, the output of the output terminal T1 is determined by the inputs of the input terminals I1 and I2. This part will be described in detail. Of course, the configuration of the AND plane 3 is programmable, and it goes without saying that any input / output correlation can be set.

FIG. 3 is a circuit diagram showing in detail only the portion related to the input / output. As described above, the comparators C1 and C2 have input voltages V1 and V2 as analog signals input to the input terminals I1 and I2 and reference voltages Vref1 and Vref2.
And each of its outputs n11,
As shown in FIG. 3, n10 and the outputs n21 and n20 are connected to the output terminal Q of the RS flip-flop 11 of the feedback circuit 9 and are connected to the outputs i1 and i2 together with the AND plane 3.
Form part of the input to. This input n11, n10, n21,
Product term lines k1 to k6 as outputs are prepared for n20, i1 and i2, and are configured to take a logical product (AND) at points indicated by ● in FIG.

On the other hand, the product term line k1 or a part of the output of the AND plane 3
k6 is input to OR planes 5 and 7, and outputs v11 and v1
2, v21, v22 together with a part of the OR plane 5, while output t1, t
2, t3, t4 and outputs h1, h2 each form part of an OR plane 7.

The outputs v11, v12 of the OR plane 5 are also output v21, v to the resistors R11, R12 of the resistance values r, 2r which form the D / A converter DR1.
22 is connected to resistors R21 and R22 having resistance values r and 2r, respectively, which constitute the D / A converter DR2. In this OR plane 5, output v11, v12, v21, for the product term lines k1 to k6
v22 is the logical sum (OR) at the points ● shown in Fig. 3, respectively.
Is configured to take.

In the other OR plane 7, the outputs h1, h2 and the outputs t1,
The t2, t3, and t4 are configured to take the logical sum (OR) with respect to the product term lines k1 to k6 at the point ● shown in FIG. Further, the outputs h1 and h2 are supplied to the set S and reset R terminals of the RS flip-flop 11 forming a part of the feedback circuit 9, while the outputs t1, t2, t3 and t4 are D / A converted. Resistor Rt1, which has resistance values r, 2r, 4r, 8r, which form the DAC1
It is connected to each of Rt2, Rt3, and Rt4. The power supply voltage Vdd of the entire circuit is 6 [V].

In the semiconductor integrated circuit 1 of this embodiment having the above circuit configuration, the output voltage Vout of the output terminal T1 is controlled as follows by the input voltages V1 and V2 to the input terminals I1 and I2.

First, when the semiconductor integrated circuit 1 is powered on, the flip-flop 11 is reset and the output i1 goes low.
Output i2 is set high.

[A] When the input voltage V2 of the input terminal I2 is 0 ≦ V2 <4, (1) When the input voltage V1 of the input terminal I1 is 0 ≦ V1 <2, both outputs of the comparators C1 and C2 are output n10. , n2
Since 0 becomes active high, the product term line k6 is selected. Therefore, in the OR plane 5, the outputs v11 and v21
Becomes high level, and the reference voltages Vref1 and Vref2 of the comparators C1 and C2 remain 4 [V], respectively. At this time,
In the OR plane 7, output h2 and output t4 are selected,
The flip-flop 11 of the feedback circuit 9 remains in the state immediately after the power is turned on, and the output voltage Vout of the D / A converter DAC1 is Vout = Vdd · f (r, 2r, 4r) / {8r + f (r, 2r, 4r)}. However,
Here, f (a, b, c ...) means 1 / (1 / a + 1 / b + 1 / c + ...). Since the power supply voltage Vdd is 6 [V], Vout =
It becomes 0.8 [V].

(2) The input voltage V1 of the input terminal I1 rises and 4
When it exceeds [V], the output of the comparator C1 is inverted, the output n11 becomes high level (the output n10 is low level), and the product term line k4 is selected in place of the product term line k6 on the AND plane 3. Therefore,
On the OR plane 7, the output h1 is selected instead of the output h2, the flip-flop 11 of the feedback circuit 9 is set, and the output i1 is at the high level (the output i2 is at the low level).
Flipped to. As a result, the active-high product term line is switched from the product term line k4 to the product term line k5 on the AND plane 3, and accordingly, the output is performed on the OR planes 5 and 7.
v12, v21 and outputs t2, t3 are selected respectively.

Thus, the outputs Vref1, Vref of the D / A converters DR1, DR2
2 is set to 2 [V] and 4 [V], respectively. Therefore, the input voltage V1 is judged to have the hysteresis HT of 2 [V] to 4 [V]. on the other hand,
The output voltage Vout of the D / A converter DAC1 is Vout = Vdd · f (r, 8r) / {f (2r, 4r) + f (r, 8r)}, that is, 2.4 [V] here. Becomes

[B] When the input voltage V2 of the input terminal I2 is 4 ≦ V2, (3) When the input voltage V1 of the input terminal I1 is 0 ≦ V1 <2, the output n10 of the comparator C1 becomes high level. The output n21 of the comparator C2 becomes high level.
Therefore, the product term line k3 is selected on the AND plane 3, the outputs v11, v21 are selected on the OR plane 5, and the outputs h2, t3, t4 are selected on the OR plane 7. As a result, the comparators C1 and C2 which are the outputs of the D / A converters DR1 and DR2
The reference voltages Vref1 and Vref2 of are respectively held at 4 [V]. On the other hand, the flip-flop 1 of the feedback circuit 9
1 is reset and the output i2 is set to high level.

At this time, the output voltage Vout of the output terminal T1 is Vout = Vdd · f (r, 2r) because the outputs t3 and t4 connected to the resistors Rt3 and Rt4 of the D / A converter DAC1 are selected. / {f (4r, 8r) + f (r, 2r)}, that is, 1.2
[V].

(4) The input voltage V1 of the input terminal I1 rises to 4 [V]
When it exceeds, the output of the comparator C1 is inverted and the output n11 becomes high level (the output n10 is low level). Therefore, in the AND plane 3, the product term line k1 is selected instead of the product term line k3, and accordingly, the output h1 is selected in the OR plane 7. As a result, the flip-flop 11 of the feedback circuit 9 is set and the output i1 is inverted to the high level (the output i2 is the low level), and the product term line on the AND plane 3 is selected from the product term line k1 to the product term line k2. Can be switched to.

When the product term line k2 becomes high level, output v12, on the OR plane 5
In v21, the outputs t2, t3, and t4 are selected on the OR plane 7, respectively. Therefore, the reference voltage Vref1 of the comparator C1 that is the output of the D / A converter DR1 changes from 4 [V] to 2 [V], and the hysteresis HT from 2 [V] to 4 [V] is set for the input voltage V1. The judgment to have will be made.

On the other hand, the output voltage Vout of the D / A converter DAC1 is Vout = Vdd · 2r / {f (r, 4r, 8r) + 2r}, that is, 4.4 in this case.
[V].

As described above, the four cases have been described. Between the input voltages V1 and V2 of the input terminals I1 and I2 and the output voltage Vout of the output terminal T1 of the semiconductor integrated circuit 1 according to the present embodiment, FIG. As shown in, the processing for outputting an analog signal for a predetermined analog input and its combination is realized. Therefore, with a simple configuration, it is possible to obtain an analog signal output after performing a predetermined process such as a determination having a hysteresis HT on the analog signal.
Further, the AND plane 3, the OR plane 5, 7 and the like can be freely set, and the programmable semiconductor integrated circuit 1 that handles analog signals can be easily obtained. Furthermore,
Since processing by software is not required, I / O response time is shortened (100 [nsec] or less in this embodiment).
Has been realized. In the semiconductor integrated circuit 1 of this embodiment, since only a comparator is used as an analog input section, the chip area is smaller than that of a control processor equipped with a normal A / D converter and D / A converter. Reductions in manufacturing processes and costs have also been achieved.

As described above, the semiconductor integrated circuit 1 of the present embodiment is
Since the output voltage can be controlled by the input voltages V1 and V2 as analog signals, it can be widely applied to construct a control device for electronic equipment that controls a motor or the like at high speed according to an input from a sensor or the like. .

Although the embodiment of the present invention has been described above, the present invention is not limited to such an embodiment, and a configuration in which a multi-stage comparator is provided as an analog input section for negative input and more precise control or The analog input unit and the analog output unit handle analog amounts other than voltage, for example, current, frequency, duty ratio, etc., or a delay element such as a timer is used as the feedback circuit 9 and a time element is included in the control. Needless to say, the present invention can be implemented in various modes without changing the gist of the present invention.

Effects of the Invention As described in detail above, the semiconductor integrated circuit of the present invention has an excellent effect that an analog amount can be input / processed and the analog amount can be output with an extremely simple configuration. Moreover, the relationship between the input and output of the analog quantity is programmable, and the applicable range can be made extremely wide. Furthermore, the response between input and output is extremely high. In addition, the semiconductor integrated circuit of the present invention can easily reduce the size of the device / structure, reduce the number of manufacturing steps, and reduce the cost.

As described above, the semiconductor integrated circuit of the present invention has a completely different idea and is superior to the conventional semiconductor integrated circuit that processes analog amounts, and is not only used for controlling actuators such as motors, but also for industrial wide use. It can be applied in various fields.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the basic configuration of the present invention, FIG. 2 is a schematic configuration diagram of a semiconductor integrated circuit as an embodiment of the present invention, and FIG. 3 is an input terminal I of the same semiconductor integrated circuit.
1, I2 and a circuit diagram showing a portion related to the output terminal T1, FIG. 4 is a graph showing an example of control in the embodiment,
Is. 1 ... Semiconductor integrated circuit 3 ... AND plane 5,7 ... OR plane 9 ... Feedback circuit 11 ... Flip-flop C1, C2, ... Cn ... Comparator DAC1, DAC2, ... DACm ... D / A converter DR1, DR2, ... DRn ... D / A converter I1, I2, ... In ... input terminal T1, T2, ... Tn ... output terminal

Claims (3)

[Claims] 1. A decoder having a plurality of inputs and outputs and capable of setting an output state for the input, and an encoder having a plurality of outputs of the decoder as inputs and capable of setting a plurality of output states for the input. In a semiconductor integrated circuit comprising: an analog input section that converts an analog signal input from the outside into a digital signal and uses the digital signal as a part of the input of the decoder; and at least a part of the encoder output. A semiconductor integrated circuit, comprising: an analog output section that generates an analog signal based on a state and outputs the analog signal to the outside. 2. The analog input section compares a plurality of reference sections that generate a reference value based on a state of a part of the output of the encoder with the generated reference value and the input analog signal. 2. The semiconductor integrated circuit according to claim 1, further comprising a plurality of comparison units that perform the comparison, and the plurality of comparison results are the digital signals. 3. The semiconductor integrated circuit according to claim 1, wherein the decoder uses an output obtained by converting a state of a part of the encoder output as a part of a decoder input.