JPH0650766B2 - Semiconductor memory device - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor memory device in which one transistor and one capacitive element are combined to form a memory cell, and in particular, a groove formed by punching the capacitive element on the surface of a semiconductor substrate. The present invention relates to a semiconductor memory device formed inside.

[Technical background of the invention and its problems]

Generally, a memory cell of a dynamic RAM (hereinafter referred to as a DRAM) is an MO for accumulating charges and holding information.
Switch transistor (transfer transistor) for exchanging the charge between the S capacitor and the external circuit
It is composed of and.

FIG. 3 is an element sectional view showing the structure of a memory cell used in such a conventional semiconductor memory device. In this memory cell, a MOS having a first-phase silicon gate electrode 13 provided on a semiconductor substrate 11 via a gate insulating film 12 as an upper electrode and an impurity layer 14 having a conductivity type opposite to that of the semiconductor substrate 11 as a lower electrode is used. Capacitor and gate insulating film 15
Second-phase polysilicon gate electrode 16 disposed via
Is used as the gate electrode, the substrate 11 and the high-concentration impurity diffusion region 17 of the opposite conductivity type are used as the drain region, and the impurity layer 14 is used as the source.

The memory cells are electrically isolated from each other by a thick insulating film 18 for element isolation. The amount of charge that can be stored in the MOS capacitor in such a memory cell is determined by the thickness and area of the gate insulating film 12 forming the MOS capacitor.

The size of the signal read when reading information is
It is determined by the amount of accumulated charge. Therefore, in order to increase the amount of accumulated charge, it is necessary to reduce the thickness of the gate insulating film 12 and increase its area.

When a planar MOS transistor as shown in FIG. 3 is used, the thickness and area of the gate insulating film 12 are naturally limited, which hinders high density.

An improved essential element structure for solving such a problem is proposed in, for example, Japanese Patent Laid-Open Nos. 52-148385 and 52-149989.

The MOS capacitors disclosed in these publications are called trench capacitors, and have a structure in which a hole is formed on the surface of a semiconductor substrate and the inner surface is oxidized to be used as a capacitor.

FIG. 4 shows a plan view of a conventional so-called groove type capacitor, and FIG. 5 shows a sectional view thereof.

A hole 202 is formed in the substrate 201 of the cell capacitor, an oxide film 206 is formed on the inner wall surface of the hole, and a cell plate 203 is formed on the surface of the cell plate 203 by using polysilicon or the like. A groove type capacitor having the lower electrode of the impurity diffusion layer 207 diffused on the surface is formed.

Due to the formation of the hole 202, a large unevenness is formed on the surface of the semiconductor substrate 201, and due to the step due to the gate wiring 204 of the transfer transistor of the cell plate 203 and other memory cells passing therethrough, it passes over them. A break in the bit line 205 is likely to occur.

FIG. 6 shows a sectional view of a conventional groove type capacitor having a groove buried therein. A filling material 208 such as polysilicon is formed in the hole 202 to fill the hole 202. However, several steps, such as oxidation diffusion and etching, are required to carry out such burying, and this has a drawback that this leads to an increase in the cost of the memory device.

[Object of the Invention]

The present invention has been made in consideration of the above circumstances, and by increasing the capacity of a MOS capacitor sufficiently, reducing the area occupied by memory cells, enabling high density, and facilitating the manufacturing process, An object of the present invention is to provide a semiconductor memory device capable of reducing the yield and the turnaround time.

SUMMARY OF THE INVENTION In a semiconductor memory device of the present invention, a groove of one memory cell is filled with a gate wiring film of a transfer transistor of another memory cell, and the gate wiring film flattens the entire opening of the groove. It is characterized in that it is configured to cover.

Example of Invention

1 and 2 are a sectional view and a plan view of a semiconductor memory device according to an embodiment of the present invention.

The sectional view shown in FIG. 1 is a sectional view of a portion cut along a line BB 'in FIG.

The hole 102 formed in the substrate 101 of the cell capacitor is configured to be located only directly under the gate wiring 104 of the transfer transistor of another memory cell passing over the cell plate electrode 103 forming the upper electrode. Has been done.

That is, the hole 102 is covered with the gate wiring 104. With such a structure, the step difference of the underlying layer with respect to the bit line 105 passing over the gate wiring 104 can be significantly reduced.

That is, the semiconductor substrate 10 formed by forming the holes 102
The unevenness of the surface of No. 1 is also filled by using the cell plate electrode 103 and the film of the gate wiring 104 of the transfer transistor of another memory cell passing therethrough. The increase in capacitance due to the groove thus formed is such that the ratio of the opening area of the groove to the area of the cell capacitor is approximately 20 to 30% and the depth of the groove is 1.0 to 1.
If it is designed to be 5 μm, it will be about 50 to 70%.

Further, if the degree of integration is improved and the area of the cell capacitor is reduced, the ratio of the opening area of the groove is relatively increased, and thus the rate of increase in capacitance is improved.

Although polysilicon is usually used as the wiring material for the cell plate electrode 103 and the gate wiring 104, a refractory metal such as molybdenum or tungsten can be used. In this case, the present invention is also applicable. Applicable.

〔The invention's effect〕

As described above, according to the present invention, the opening of the groove type capacitor of one memory cell is buried and entirely covered by the gate wiring film of the transfer transistor of another memory cell. Since the closet is effectively filled, there is an advantage that unevenness on the surface of the semiconductor substrate is reduced and disconnection of wiring is prevented.

Further, since the groove type capacitor can be configured without increasing the number of manufacturing processes, there is an advantage that the density of the memory device can be increased and the manufacturing cost can be prevented from increasing.

[Brief description of drawings]

FIG. 1 is a sectional view of a cell portion of a memory device according to an embodiment of the present invention, FIG. 2 is a plan view thereof, FIG. 3 is a sectional view of a cell portion of a conventional semiconductor memory device, and FIG. FIG. 5 is a plan view of the groove type capacitance of FIG. 5, FIG. 5 is a sectional view taken along the line AA ′, and FIG. 6 is a sectional view of a conventional groove type capacitance in which a groove is buried. 101 ... Semiconductor substrate, 102 ... Groove (hole) formed in capacitor part, 103 ... Cell plate electrode, 104 ... Gate wiring of transfer transistor of other memory cell, 105 ...
Bit line.

Claims (1)

[Claims] 1. A semiconductor memory device in which a capacitive element formed in a groove formed on a surface of a semiconductor substrate and a transfer transistor formed on the surface of the semiconductor substrate adjacent to the capacitive element are combined to form a memory cell. In the above, the groove of one memory cell is filled with a gate wiring film of a transfer transistor of another memory cell, and the entire opening of the groove is flatly covered by the gate wiring film. Semiconductor memory device.