JPH0650835B2 - Data processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to time division multiple access (TDMA).
n Multiple Access) Among common TDMA terminal equipment provided in ground stations such as satellite communication by communication system, compression / expansion, combination / separation, scramble / decompression of transmission / reception data
The present invention relates to a data processing device that performs processes such as adding a descramble and a preamble.

[Conventional technology]

FIG. 13 shows a conventional example of common TDMA terminal station equipment of a ground station to which a TDMA communication system for transmitting and receiving digital data is applied according to a defined frame and burst structure. Regarding the TDMA communication system and the terminal equipment shown in FIG. 13, the similarity is similar to “Digital Satellite Signal” published by Sangyo Tosho Publishing by Kazuhiro Miyauchi and Kunifumi Nosaka.
Since it is described in Chapters 3.1 to 4.3.3, etc., description of each is omitted here.

In the figure, 1 is a data processing device, 2 is an input terminal for inputting transmission data, and 3 is conversion after converting serial serial transmission data input from the input terminal 2 into parallel data, and then temporarily storing the data and again. A compression buffer which reads out this intermittently at a faster speed than at the time of store (input), 4 is a parallel / serial converter for converting the parallel data output of the compression buffer 3 into serial data, and 5 is energy transmission for transmission. , A preamble adder 6 adds the preamble bit string generated by the preamble generator 7 to the front part of the output data string of the scrambler 5, and 8 sends the transmission-processed data string to the modulator 9. Is an output terminal for giving a gate signal to the modulator 9 for turning its output ON / OFF.

Further, 11 is a demodulator, 12 is an input terminal for inputting the output of the demodulator 11 to the receiving side of the data processing device 1, 13 is a descrambler for removing the scramble applied on the transmitting station side, and 14 is a serial / serial A parallel converter, 15 is an expansion buffer that temporarily stores the intermittent parallel output data of the serial / parallel converter 14, and then reads these as continuous serial data, 16 is an output terminal thereof, 1
Reference numeral 7 is a unique word detector, 18 is a synchronization control unit that creates a time reference of a transmission / reception frame based on the detection pulse from the unique word detector 17, and controls burst synchronization of transmission / reception of the station, and 19 is a synchronization control unit. It is a timing generator that gives timing and gate signals to each circuit based on the output signal of 18.

Before explaining the operation, the TDMA frame structure and burst structure peculiar to the TDMA communication system will be briefly described (the details are also described in Chapter 4.3.1 of the above-mentioned book).

In the TDMA communication system, radio waves are transmitted to a time slot to which each station is assigned at regular intervals. For example, in the case of passing through a communication satellite, each station can connect to it on a predetermined frequency in a time-division manner so that radio waves can be communicated with each other without interference. One unit of this cycle is called a frame, and one unit of the radio wave transmitted by each station is called a burst. A gap called a guard time is provided between the bursts. FIG. 2 shows an example of a frame and burst configuration.

The data processing device shown in FIG. 13 forms continuous transmission data of the input terminal 2 into a burst form of a predetermined format shown in FIG. 2 and sends the burst data to the modulator 9 or reproduced by the demodulator 11. The data portion required by the station is separated from the bit string, converted into continuous data, and output to the output terminal 16.

Next, the process steps will be described in the order of data processing on the transmitting side and data processing on the receiving side.

First, for example, continuous transmission data on the ground station side, which is connected to the input terminal 2, is sequentially stored in the compression buffer 3 constituted by a memory element. The stored data is sequentially read out by the parallel / serial converter 4 in accordance with the burst transmission time of the station by the bits transmitted in one burst at the satellite clock. The read data string is sequentially input to the scrambler 5 and scrambled. The output bit is then input to the preamble adder 6. In the preamble adder 6, a predetermined preamble generated in the preamble generator 7 corresponding to the preamble transmission time of the time slot of the station (for example, as shown in FIG. 2, for example, a bit string CBRS for carrier reproduction / timing reproduction) And uw) are output, and both bit strings are combined at the timing at which the previous scrambled bit string is output following the end thereof. That is, the output bit string of the preamble adder 6 is the second bit string.
It corresponds to the burst in the figure. The bit string corresponding to the transmission burst thus formed is sent to the modulator 9 through the output terminal 8.

The above is an example of the data processing on the transmission side, but the timing of such a series of operations, that is, the timing of reading the transmission data from the compression buffer, the gate signal for starting or ending the generation of the bit string of scramble or preamble Are supplied from the timing generator 19. The timing generator 19 also supplies the ON / OFF gate to the modulator 9 through the output terminal 10. This gate signal is synchronized with the bit string corresponding to the transmission burst at the output terminal 8, and the modulator corresponding to the predetermined time slot of the station, that is, while the bit string corresponding to the transmission burst is input to the modulator 9. The output of 9 is turned on and turned off otherwise (this signal is hereinafter referred to as carrier ON / OFF signal).

Next, the data processing on the receiving side will be described. Demodulator 11
The bit string reproduced in 1 is input to the descrambler 13 through the input terminal 12 and descrambled. Then, of the bit string of the descrambler output, the portion necessary for this receiving station is sequentially stored in the expansion buffer 15 through the serial / parallel converter 14. Then, the stored received data in the decompression buffer 15 is continuously read by the clock on the output side and is sent to the ground side through the output terminal 16, for example.

The above is an example of the data processing on the receiving side. Similar to the transmitting side, the timing and gate signals for controlling a series of operations are supplied from the timing generating section 19 to the individual circuits.

The unique word detector 17 detects a unique word of each reception burst and outputs the detection pulse to the synchronization control unit 1.
Give to eight. The synchronization control unit 18 creates a time reference for the received frame and the transmitted frame based on the timing of these pulses, and supplies this to the timing generation unit 19.

The above is the description of the data processing device 1 shown in FIG. 13 and its peripheral circuits. Although a simple example is shown here, depending on the applied communication method, two bit sequences are processed at the same time, an encoder for encoding for error correction, and an encoded received data A decoder for decoding may be provided, and multiple compression / decompression buffers may be provided for multiplexing data of multiple channels in one burst.

[Problems to be solved by the invention]

As described above, the conventional data processing device is provided with a dedicated circuit for performing each action for each action, and
The start and end of the operation of these circuits have been controlled by the timing signal and gate signal from the timing generator. For this reason, it is difficult to change the circuit when changing the system parameter, for example, changing the preamble length or its contents or changing the time slot. Alternatively, individual circuits (hardware)
Even if it was devised to be able to deal with the change, its range of freedom was narrow. Further, since each circuit is controlled by the timing signal from the timing generator, various kinds of accurate timing signals are required, and it is necessary to change the relationship between these timing signals at the same time as changing the parameters. That is, there are drawbacks that the device becomes complicated and the allowable range for changing the parameters is narrow.

The present invention provides a data processing device which solves the above problems, has high versatility, can easily cope with a change in system parameters, and has a simple configuration.

[Means for solving problems]

A data processing device according to the present invention has two storage areas, and alternatively writes the transmission data in area units in the two areas based on a first reference timing signal,
Based on the first storage means for storing the written transmission data and the first reference timing signal, the transmission data is selectively read out from the two storage areas of the first storage means and read out. It has a conversion means for transmitting the transmission data and outputs it in a format corresponding to the burst, and a plurality of storage areas, and writes it in the plurality of storage areas based on the first reference timing signal, and writes the written data. Second storage means for storing, and the first and second
The first reference timing signal supply means for supplying the first reference timing signal to the storage means and the conversion means based on the received data in burst form, and the second reference timing signal. , Above second
Of the storage means of the storage means for selectively reading the transmission data processed corresponding to the burst, modulating the read transmission data, and outputting the modulated transmission data. A second reference timing signal supplying means for supplying a second reference timing signal having the same cycle as the first reference timing signal is provided.

[Action]

According to the present invention, since the apparatus is configured as described above, the hardware processing has conventionally required real-time processing, and the transmission / reception data processing, which has a small degree of freedom of change to correspond to the change of the system parameter, has been performed. Since this is executed by the conversion means and the first and second storage means realized by the conversion means and the memory provided so as to sandwich the conversion means, the versatility is high and the system parameters can be easily changed. It is possible to obtain a device that can be used and that can be configured easily.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. First
In the figure, 1 is a data processing device of the present invention, 100 is a CPU that executes transmission / reception data processing by program instructions, 101 is a program memory that mainly stores programs, and 102 is a work memory that stores data during processing. 2 is an input terminal for transmitting data from the ground side, 103 is a serial / parallel converter for converting the serial data of the input terminal 2 into a parallel system,
Reference numeral 104 denotes a compression memory capable of writing data from the serial / parallel converter 103 and reading the already stored data onto the data bus 105. Reference numeral 106 denotes a transmission bit corresponding to a burst processed for transmission by the CPU 100 and Transmit memories, 107 and 108, capable of reading these already stored data while writing the corresponding carrier ON / OFF bits
Among the output bits read from the transmission memory 106, the transmission bit corresponding to the burst and the carrier ON
It is a parallel / serial converter that converts the bit corresponding to / OFF into a serial system and sends it to the modulator 9 which is a peripheral device of the data processing device 1 through the output terminals 8 and 10.

It should be noted that the compression memory 104 has two storage areas, and the transmission data is alternatively written in the two areas based on the first reference timing signal, and the written transmission data is stored. The first storage means has a plurality of storage areas by the transmission memory 106, writes into the plurality of storage areas based on the first reference timing signal, and stores the written data. Each storage means is configured. Further, the CPU 100 alternatively reads the transmission data from the two storage areas of the first storage unit based on the first reference timing signal, performs transmission processing on the read transmission data, and supports burst. The conversion means for outputting in this format is configured. In addition, the CPU1
00 and the modulator 9 read out the transmission data processed selectively corresponding to the burst from a plurality of storage areas of the second storage means on the basis of the second reference timing signal, and read this out. Both of the modulating means for modulating and outputting the transmission data are respectively configured.

Further, 11 is a demodulator as a peripheral device of the data processing device 1, 12 is a bit from the demodulator 11
An input terminal for inputting to the input terminal 109, a serial / parallel converter for converting the bit string from the input terminal 12 into a parallel system, and 110 for writing output bits of the serial / parallel converter 109, while storing already stored data on the data bus. Receiving memory that can be read above, 111 is a decompressing memory that can read received processing data while writing received processing data, and 112 is a serial system bit string that is the output read from the decompressing memory 111 The parallel / serial converter 16 converts the data into a serial data and continuously reads the data, and 16 is an output terminal of the parallel / serial converter 112, for example, to the ground side. Also, 11
3 is controlled by the CPU 100, and the CPU of each memory
Side (side of input / output terminals that is connected to data bus 105)
Bus, 114, 11 for giving the address of the area
5, 116 and 117 control the addresses of the areas on the external side of the compression memory, the transmission memory, the reception memory, and the expansion memory (the side of the input / output terminals that is connected to the serial / parallel converter or the parallel / serial converter). The first to fourth address counters 118 and 118 are toggle control counters that output an address control signal for switching the read area and the write area of the four memories.

Further, 17 and 18 are a unique word detector as a peripheral device of the data processing device 1 which detects a unique word of the output of the demodulator 11 and creates a frame reference timing signal for transmission / reception of the station, and a synchronization control unit. Therefore, both the unique word detector 17 and the synchronization control unit 18 supply the first reference timing signal to the first and second storage means and the conversion means based on the received burst-like received data. And a second reference timing signal supply means for supplying a second reference timing signal having the same period as the first reference timing signal to the modulation means.

Next, the operation will be described. Now, for the sake of concrete explanation, in FIG. 2, the frame length is converted into 25 bits.
60 bits, 4 bursts, each 632
Bits, guard time between them is 8 bits, carrier wave and bit timing reproduction bit (CBRS) are 1 in total
It is assumed that 28 bits, a unique word (uw) are 16 bits, a data portion is 488 bits, a burst transmitted by the station is burst 2, and a burst received by the station is burst 4.

The operation of the CPU in the following description, and detailed connection diagrams and terms relating to the operation will be described in detail, for example, in "Microcomputer User's Manual MCS-85" 1983 issued by Intel Japan Co., Ltd. Therefore, the description is omitted here. Further, although an example of a processing method by the CPU is shown in the description, since the present invention is not characterized by these individual processing methods (contents of the program), it is possible to grasp the flow of the entire operation in these descriptions. Stop to a degree.

The CPU uses the received frame reference pulse output by the synchronization control unit 18 which is a peripheral device of the data processing device 1 (here, it coincides with the leading bit position of the received frame reproduced by the demodulator 11). The internal program counter is reset and the program memory 10
Execution of the instruction starts from address 0 of 1.

First, the processing by the CPU in an arbitrary received frame will be described. Now, at the time when the CPU is reset by the reference pulse of any Mth received frame, one burst of transmission data 488 bits input through the input terminal 2 in the M−1th received frame section is stored in the compression memory 104. Minutes, and the reception memory 110 has M-
It is assumed that 2560 bits of all reproduction bits of the first reception frame section are stored.

First, the transmission side processing will be described.

FIG. 3 shows an example of a memory map of the compression memory 104 configured by using an 8-bit / word memory. The compression memory 104 has two areas C-1 and C-2 for storing the transmission data for one frame of the station. The CPU causes the contents S _{0 to} S of the compression memory 104 to be instructed by the program.
₄₈₇ is read, and scramble processing is performed on this. Here, S _{0 to} S ₄₈₇ are bits corresponding to the order of the transmission data input through the input terminal 2. FIG. 14 shows an example of a circuit of a conventional scrambler (conventional drawing, reference numeral 5 in FIG. 13).
Corresponding to). In FIG. 14, 55 is a data input terminal, and 56 is a scrambled data output terminal. Configure the scramble pattern generator 5
The output logic of the D-flip / flop 51 of the stage is initialized to "1" by the set pulse 54 every time when a new burst data string arrives from the data input terminal 55. In the configuration of the present invention, such an operation can be executed by the CPU as follows, for example. That is, a scramble pattern for one burst similar to that generated at point A in FIG. 14 is stored in the area of the program memory 101 in advance, and the transmission data read from the compression memory 104 and the scramble corresponding to that position are stored. An exclusive logic (EX-OR) operation may be performed on the pattern by an arithmetic unit in the CPU. The scrambled data is stored in a predetermined address of the transmission memory 106. In Figure 4, 8
An example of a memory map of the transmission memory 106 using a bit / word memory is shown. Transmission memory 106 is TDM
It has three areas, TX-1, TX-2, and TX-3, which are S areas and C areas corresponding to all bits on the A frame. Also, B1, B2, B3, B4 in the figure correspond to each burst.

Since the transmission burst is now burst 2, the scrambled data is stored in the positions S _{0 to} S _{487 in} the area S-B2 in FIG. 4 in the order of transmission. The above is the scramble process.

Next, an example of adding a preamble will be described. The preamble of the burst example shown in FIG. 2 is CBRS and u.
It consists of w. The CBRS is usually composed of a continuous pattern of "1" and a repeating pattern of 0-1-0-1 ... Therefore, the CPU uses a predetermined number of "1" and "1".
"-0-1-0 ..." Is stored in a predetermined address of the transmission memory 106 shown in Fig. 4. In addition, uw is the current bit u ₀ ...
Although it is a special pattern composed of u ₁₅ , it is a fixed pattern, so that it is stored in advance in a predetermined address of the program memory 101 as in the case of scrambling, and this is stored in a predetermined address of the transmission memory 106, that is, Transfer to the positions of u _{0 to} u ₁₅ shown in FIG.

Next, processing of the carrier ON / OFF signal will be described. The carrier ON / OFF signal supplies this to the modulator 9. For example, when the logic is "1", the output of the modulator 9 is turned on, and when it is "0", it is turned off. . That is, it is a signal for turning on the modulator 9 only while the station transmits a burst in the frame. The corresponding bit is stored in the area C of the transmission memory 106. Now, since the burst in the frame transmitted by that station is burst 2, "1" is added to the portion excluding the bit corresponding to the guard time of C-B2 shown in FIG. “0” for C-B1, C-B3, C-B4
To store.

The above is an example of the role played by the CPU in the data processing of transmission.

Next, the processing on the receiving side will be described.

FIG. 5 shows an example of a memory map of the reception memory 110 using an 8-bit / word memory. Reception memory 11
0 is RX- corresponding to all bits on the TDMA frame.
1 and RX-2. Also, in the figure, B1,
B2, B3 and B4 correspond to each burst. As assumed above, all the reproduced bits in the (M-1) th received frame are already stored in this receiving memory 110 in units of 8 bits from the beginning of the received frame. this house,
The data required by the station are bits S _{0 to} S ₄₈₇ stored in the area of B4 by assumption. The CPU reads out these bits and outputs the descramble pattern and E
X-OR logical operation and descrambling. The descramble pattern is equal to the scramble pattern of the station that has transmitted S _{0 to} S ₄₈₇ , but it is usually also equal to the scramble pattern of the station that receives it. In this case, the scramble pattern described in the previous transmission process is used. be able to. The descrambled bits corresponding to S _{0 to} S ₄₈₇ are sequentially stored in the expansion memory 111. FIG. 6 shows an expansion memory 111 using an 8-bit / word memory.
An example of a memory map of is shown. The decompression memory 111 stores the received data for one frame required by the station.
It has two regions, -1 and E-2.

The above is an example of the role of the CPU in the received data processing.

The processing performed between the CPU and the memory in the Mth received frame has been described above. In the above description, the transmission process and the reception process have been described in this order, but this is merely the order of description and not the order in which they should be processed. It is not necessary for each circuit to operate in sequence along the signal flow as in the conventional example, and it suffices if the above processing is completed within the Mth received frame. That is, by the time the M + 1th received frame reference pulse resets the CPU next time, the transmission memory 106 stores M at the predetermined address shown in FIG.
The bit corresponding to the transmission burst created based on the transmission data input in the -1st reception frame section and the bit corresponding to the carrier ON / OFF signal are stored, and in the M-1th reception frame Among the received reproduction bits, the reception-processed data required by the station may be stored in a predetermined address of the decompression memory 111.

Next, the structure of the compression memory 104, the expansion memory 111, the reception memory 110, and the transmission memory 106, and the input / output terminals of these, through the serial / parallel converter or parallel / serial converter, the ground side and the modulator / demodulator side. Address counter 11 for controlling the address of the area connected to
4,117,116,115 and toggle control counter 11
The operation of 8 and the like will be described.

For specific description, an example of realizing each of these circuits under the above assumption is shown in FIGS. 7, 8, 9, and 10. FIG. 7 (a) is the compression memory 104 and its peripheral circuits, FIG. 7 (b) is a main time chart thereof, and FIG. 8 (a).
Is a transmission memory 106 and its peripheral circuits, (b) is a main time chart for them, and FIG. 9 is a toggle control counter 11
8 and FIG. 10 (a) show a compression memory 104 and an expansion memory 11
1st and 4th address counters 114 and 117,
(b) is the third address counter 11 of the reception memory 110
6 (c) is the second address counter 115 of the transmission memory 106.

Among these memories, the compression memory 104, the reception memory 110, and the decompression memory 111 are shown in FIG. 3, FIG. 5, and FIG.
C-1 and C-2, RX-1 and RX-2, E- shown in the figure
It is used by dividing the area into two such as 1 and E-2. In these figures, the shaded area is an unused portion for improving the division of the memory and does not relate to the principle of the present invention.

In addition, these memories are configured to be able to read data stored in one area while writing data in the other area. A memory circuit having such a configuration is conventionally called a toggle memory, and there is a circuit that uses two memory elements. Recently, a circuit that is commercially available as an LSI under the name of Dual Port Memory ( For example, IDT7130 and IDT7 from IDT
M134 etc.) can be used. FIGS. 7 (a) and 7 (b) show a concrete example of the compression memory 104 and its peripheral circuits and their main time charts when an 8-bit × 1024-word dual port memory is used. In the figure, the input / output ports marked with L of the compression memory 104 have their addresses controlled by the address signals of the address terminals marked with L, and the input / output ports marked with R have their addresses controlled by the address signals of the address terminals marked with R. Controlled.

The upper addresses of these three memories are controlled by the output signal of the toggle control counter 118, and the writing area and the reading area are alternately switched for each reception frame reference pulse. For example, in the compression memory of FIG. 3, the area C- shown in FIG.
When 1 is used as a write area whose address is controlled by the first address counter 114, the area C-2 becomes a read area whose address is controlled by the address signal of the address bus 113 on the CPU side. Then, these relationships are reversed by the next reception frame reference pulse.

The expansion memory 111 and the reception memory 110 are also controlled by the output signal of the toggle control counter 118.
The circuit example of the decompression memory 111 is the case of the compression memory 104, and the circuit example of the reception memory 110 is that the third address counter 116 on the writing side uses A _6L ,
Compressed memory 104 except that A _7L and A _8L are also controlled
Since it is the same as the case of, the description thereof is omitted here.

The first address counter 114 uses the address in the write area of the compression memory 104 as the third address counter 1
16 is an address in the writing area of the receiving memory 110, and the fourth address counter 117 is an expanding memory 11
The address in the read area of 1 is controlled.

Examples of these circuits using a commercially available synchronous hexadecimal counter are shown in FIGS. 10 (a) and 10 (b). (a) is an address counter for the compression memory and decompression memory, and (b) is an address counter for the reception memory. Further, the counter (a) counts up with the clock 1 which is a transmission clock for transmission / reception data on the ground side. The counter in (b) is demodulator 1
It counts up by the clock 2 which is the transmission clock of the reproduction bit from 1. Further, these clocks are synchronized with the reception frame reference pulse generated at the head of the reception frame, whereby the counter is reset every reception frame. Then, the first address counter 1
Reference numeral 14 stores the serial serial data string input to the input terminal 2 in order in the compression memory 104, so that the addresses are set in order at a cycle of eight times the clock. This is a serial / parallel converter 1 for input data.
This is because the data is converted into a parallel system in units of 8 bits through 03 and stored. The fourth address counter 117 reads the reception processing data stored in the decompression memory 111 in a continuous serial manner through the parallel / serial converter 112 and the output terminal 16, so that the fourth address counter 117 also has a cycle eight times the clock on the ground side. The addresses are set in order. If the transmission burst and the reception burst have the same configuration as assumed here, the first address counter 114 and the fourth address counter 117 can be used together.

The third address counter 116, which controls the write address of the receiving memory 110, receives the reproduction output bit string of the serial demodulator 11 from the input terminal 12 through the serial / parallel converter 109 in order from the beginning of the frame. Since it is stored in 110, the address is set in order at a cycle of 8 times the clock.

According to the above description, the transmission data input through the input terminal 2 in the M-1th reception frame period is transmitted in the Mth reception frame period and stored in the transmission memory 106 in a form corresponding to the burst configuration. , M-
Of the reproduced bits from the demodulator 11 input through the input terminal 12 in the first reception frame section, the reception data valid for that station is received within the Mth reception frame section and stored in the decompression memory 111. The output terminal 16 is continuously output throughout the M + 1th reception frame period.
It can be understood that is output by.

Next, the operation of the transmission memory 106 and the second address counter 115 and the like around it will be described.

The transmission memory 106 is different from the above three memories in that
It is used by being divided into at least three areas like TX-1, TX-2, and TX-3 shown in the figure. Each area is assigned to one of writing, storing, and reading, and this role is switched and circulated in the frame period.

Next, the reason why only the transmission memory is divided into three areas will be described. In satellite communication by the TDMA system, each station sends out each burst so that each burst is aligned on the satellite as shown in FIG. On the other hand, it takes about 120 msec from the ground station to reach the satellite.
Therefore, it is necessary for the ground station to transmit the burst after allowing for this time delay. Normally, the ground station creates a transmission frame reference pulse in the station corresponding to the reception frame reference pulse, and sends out a burst in accordance with the burst position to which the station is assigned based on this. That is, it is assumed here that the transmission frame reference pulse is created at a timing corresponding to the leading bit position of the frame on the satellite if the radio wave is transmitted at the pulse position. In addition,
Such a transmission / reception frame reference pulse is created from the unique word detector 17 and the synchronization control unit 18,
Since the method is not relevant to the present invention, it is assumed here that such a reference pulse is obtained at the output of 18.

The timing relationship between the reception frame reference pulse and the transmission frame reference pulse differs depending on the position of the earth station on the earth, and even in the same station, it slowly changes due to the orbital fluctuation of the satellite.

In the present data processing device, since the transmission / reception processing is collectively performed by the processor, as described above, the reset timing of the CPU and the toggle timing of the compression memory, the expansion memory, and the reception memory are all performed by the reception frame reference pulse. If the reception frame reference pulse and the transmission frame reference pulse are always the same, the transmission memory also has a toggle structure composed of two regions like the three memories above.
If this is toggled by a reception frame reference pulse and the address counter that controls the address on the read side is reset by this pulse, it is input through the input terminal 2 in the M-1th reception frame, and the Mth reception frame section The bit corresponding to the burst of the predetermined format stored in the transmission memory at 1 is sent to the modulator 9 through the output terminal 8 at the correct timing within the reception (or transmission) frame section of the M + 1th memory. However, normally, the timings of the received frame reference pulse and the transmitted frame reference pulse do not match as described above. In such a situation, the transmission memory is divided into three areas in order to satisfy both the batch processing of transmission and reception and the transmission of burst at the correct timing. The writing area from the CPU side is TX-1 → TX-2 → TX-3 for each received frame reference pulse.
→ TX-1 → Set cyclically as shown. On the other hand, the area on the read side is set in the same manner for each transmission frame reference pulse.

FIGS. 8 (a) and 8 (b) show specific transmission memories and their peripheral circuit examples and their main time charts when an 8-bit × 4096-word dual port memory is used. Further, FIG. 10 (c) shows a circuit example of the second address counter 115 constituted by a hexadecimal counter.

This counter is reset by the transmission frame reference pulse generated at the beginning of the transmission frame, and counts up at the clock 3 which is the transmission clock of the bits sent to the modulator 9.

Now, start with the Mth received frame reference pulse, M
It is assumed that the L-th transmission frame reference pulse starts the L-th transmission frame period in the th reception frame period (see FIG. 8 (b)). Then, for example, in the Mth reception frame section, the address in the TX-1 area of the transmission memory shown in FIG. 4 is controlled from the CPU side through the address bus 113, and the bit corresponding to the transmission burst is transmitted there by the transmission processing. , The area on the read side is set to TX-2 before the L-th transmission frame reference pulse, and the contents stored and stored in the M-2th reception frame section are read. Be done. Further, after the pulse, the read area is switched to TX-3, and the contents stored and stored in the M-1th reception frame section are read out. In other words, by the M + 1th received frame reference pulse,
When the write area from the CPU side is switched from TX-1 to TX-2, the read area has already been moved from TX-2 to TX-3. In this way, the address of the transmission memory is controlled by dividing the area into three so that the writing area and the reading area do not overlap.

The second address counter 115 is the transmission memory 106.
Control the address in the read area. The counter 115 is reset by the transmission frame reference pulse, and the contents of one frame in the transmission memory 106 are sequentially read from the address where the bit corresponding to the beginning of the frame is stored. However, in the transmission memory 106, as shown in FIG. 4, in addition to the bit corresponding to the transmission burst (area S in the figure), there is also a bit corresponding to the carrier ON / OFF signal (area C in the figure). It is stored. Therefore, the second address counter 115 time-divisionally sets two kinds of addresses corresponding to the area S and the area C in FIG. 4 within a cycle corresponding to eight symbols of the clock. This is done by a signal from the second address counter 115 to A _{9L of the} transmission memory 106. Then, the output data corresponding to the area S corresponds to the output terminal 8 through the parallel / serial converter 107 in order to convert to the serial method in units of 8 bits and to correspond to the area C. Similarly, the output data is output to the output terminal 10 through the parallel / serial converter 108. The output bits of the output terminals 8 and 10 are respectively connected to the modulation bit input terminal and the carrier ON / OFF signal input terminal of the modulator 9 which is a peripheral device of the present device.

FIG. 9 shows an example of the circuit of the toggle control counter 118 which controls the toggle and circulation of these four memory areas. As shown in this figure, the counter 118 is composed of two synchronous counters 118a and 118b which count up every reception frame reference pulse and a synchronous counter 118c which counts up every transmission frame reference pulse. The counter 118c for controlling the read side area is reset by the inverted signal of G2 which is the write side address signal so that the phase relationship between the write area circulation and the read area circulation of the transmission memory becomes a predetermined relationship.

The time chart of the signals related to FIG. 9 is (b) of FIG.
Shown in.

Further, the received frame reference pulse and the transmitted frame reference pulse are the unique word detector 17 as a peripheral circuit of this device.
It is created by the synchronization control unit 18 and supplied to this device.

Note that the control signal of each memory, such as a write signal or an output enable signal, has a lower bit of each address counter on the side whose address is controlled by the address counter.
For example FIG. 10 (a), prepared by using the signal of the Q _B terminal of the hexadecimal counter of the first stage in the case of Qc terminal of the hexadecimal counter the first stage addition, (c) in the case of (b) Also, those from the CPU side are usually supplied to the memory through the control bus of the CPU, etc., but these methods are well known in general circuits using the CPU and the memory, and the operation intended by the present invention. Since it is not directly related to the above, the description of each serial / parallel converter and parallel / serial converter will be omitted here for the same reason.

In the embodiment, scrambling, descrambling, addition of a preamble, separation of data, and the like have been described as an example of transmission / reception processing, but the type of processing is not limited to this. Processing such as encoding and encryption is also performed depending on the need and possibility.

The above is the description of FIG. 1 shown as an embodiment of the present invention. However, in the description, for example, the number of transmission bits and the numbers in the memory map corresponding thereto are values for the virtual parameters shown above in order to make the description concrete, and the present invention is essentially It is not related to these numbers.

Although the basic configuration of the present invention has been described in the above embodiment, in some cases, as shown in FIG. 11, in order to improve performance for high-speed processing or to add other functions, etc. Generally, a digital signal processor (DSP) 119 capable of performing a data calculation process at a higher speed than a CPU, and a DMA controller 120 for directly transferring data between the DSP 119 and each memory or between memories.
And an interface memory 121 for exchanging data with a host processor that controls the entire common TDMA terminal equipment including this device, and the phase relationship between the reception frame reference pulse and the transmission frame reference pulse is bad. In some cases, the first delay circuit 122, the second delay circuit 123, or the like that eliminates this may be used.

Next, the function and effect of the embodiment shown in FIG. 11 will be described.

First, the addition of the DSP 119 and the DMA controller 120 provided together with the DSP 119 will be described. CP to DSP119
The method of positioning it as an input / output device of U and using it together with the CPU, and providing a DMA controller accordingly is a method often found in the circuit configuration using the CPU. That is, this modified example does not have novelty in the modified part, but is on the extension of FIG. 1 that enables batch processing of transmission and reception processing by using the CPU.

The effect and action are as follows. The DSP is a processor especially adapted for high-speed arithmetic processing of digital data, and can achieve high-speed transmission / reception processing. That is, in FIG. 1, the scramble / descramble processing executed in the CPU and, if necessary, the encoding processing can be executed in the DSP at high speed. On the other hand, the DMA controller 120 used together with this is mainly used for high-speed data transfer between the I / O port of the DSP 119 connected to the data bus and each memory. In the DMA controller 120, the transfer start address of the memory, the number of transfers, etc. are set by the CPU. Then, when a direct memory transfer request is received from the DSP 119, instead of the CPU,
An address signal is sent out on the address bus according to the set parameters, and data transfer between the memory and the DSP is executed at high speed. As described above, the combined use of both is a modified example in the case where high-speed processing is required. Since the DSP and the DMA controller can both be commercially available, a detailed description of the operation will be omitted here.

Next, the operation and effect of the interface memory 121 will be described.

In the example of FIG. 1, the case where the CPU executes a certain process for each received frame according to the program stored in the program memory 101 has been described. By the way, in the actual transmission / reception processing, there are cases where it is desired to change processing parameters in units of frames. For example, TDMA
In the satellite communication method, when the burst is transmitted to the satellite for the first time (at the time of initial acquisition), the burst is transmitted in a slot dedicated to the initial acquisition on the frame,
It also does this with short bursts for initial acquisition (see Section 4.3.3 of the above document). Such an instruction is normally given by the common T of the ground station including this device.
It is performed by another processor (herein referred to as a host processor) that manages and controls the entire DMA terminal equipment. One of the roles of the interface memory 121 is to receive such an instruction from the host processor and enable the transmission / reception processing according to the instruction at any time. That is, the CPU program is configured to determine the processing parameters at a predetermined time, for example, at the beginning of the data processing of each frame, by looking at the contents of the interface memory 121, that is, the instruction from the host processor. Flexible processing can be performed according to the instruction in frame units.
If a dual port memory is used as the interface memory 121, information can be transferred from the device 1 side to the host processor. For example, in the burst structure shown in FIG. 2, in some cases, in addition to data from the ground side, inter-station control information (referred to as OW signal) and the like are multiplexed in the data portion. The OW signal from the host processor is received through the interface memory 121, and this is combined (multiplexed) in the burst by the transmission process, or conversely, the OW signal included in the burst from the partner station is separated by the reception process to obtain the interface. It can also be transferred to the host processor through the memory 121.

Furthermore, the information is also received from the host processor side in the following cases.

In the explanation of FIG. 1, it is assumed that each reception burst is correctly aligned at a predetermined position with the reception frame reference pulse at the head according to the frame structure of FIG. The relative positional relationship with respect to may fluctuate within an allowable slot including guard times on both sides of a predetermined position of the burst. When the reproduced bits of the output of the demodulator for such a burst are directly input to the present apparatus through the input terminal 12, the bits S _{0 to} S ₄₈₇ to be received in the memory map of the receiving memory shown in FIG. It will be stored at a bit position.

The amount of such a shift is detected by the unique word detector 17, and a kind of shift register which is usually called an elastic buffer provided at the exit of the demodulator 11 is controlled according to the amount of the shift. The position of the playback bit is corrected to the nominal position.

On the other hand, in FIG. 11, the amount of the above deviation is notified from the interface memory 121 to the present apparatus through the host processor, so that even if the reproduction bit which is still deviated from the nominal position is stored in the reception memory. , Can handle this correctly.

As described above, the interface memory 121 serves as a communication port for information relating to transmission / reception processing between this device and the host processor, and information multiplexed or multiplexed in a burst.

Next, the operation of the first delay circuit 122 and the second delay circuit 123 will be described.

Referring to FIG. 1, in the TDMA system in satellite communication, the timing relationship between the received frame reference pulse and the transmitted frame reference pulse varies depending on the position of the station on the earth, and the relationship (timing difference) varies depending on the orbital variation of the satellite. Said to do. Now, let us consider a case where the timing of the received frame reference pulse corresponding to the nominal position of the satellite (center position of the orbit) and the timing of the transmitted frame reference pulse are substantially the same. In such a station, the context of both timings changes depending on the orbital fluctuation of the satellite. This disturbs the processing in consideration of the fixed relationship, and also hinders the stable operation of the toggle of each memory. The first delay circuit 122 makes such a station have a difference in timing between the reception frame reference pulse and the transmission frame reference pulse used in the apparatus in advance so that the relationship between them does not change. It is for. On the other hand, the second delay circuit 123 is the first delay circuit 1
The same delay amount as 22 is applied to the reproduced bit string, and the output bit string holds the correct timing relationship with the delayed received frame reference pulse.

Further, another embodiment will be described. In FIG. 1, the case where the output system of the transmission channel from the device 1 to the modulator 9 is one system and the input system of the reproduction channel from the demodulator 11 to the device 1 is one system has been described. By the way, in the TDMA communication system using a communication satellite, a four-phase phase modulation system (in the above-mentioned "digital satellite communication") in which modulation is performed in two channels (herein, each channel is referred to as I channel and Q channel) is used. (Explained in Chapter 3.3) is often used. In such a case, the number of outputs of the transmission channel from this device to the modulator is two. Similarly, the number of input channels from demodulators is 2
In some cases, it becomes a system (explained in Chapter 3.3 above).

An embodiment based on FIG. 1 corresponding to such a case is shown in FIG. In FIG. 12, reference numeral 124 denotes a newly provided parallel / serial converter, which converts the bits corresponding to the parallel transmission burst from the transmission memory 106 into the serial system and outputs the converted signal to the modulator 9 through the output terminal 126.
Connect to. Here, 8 is, for example, an I channel output terminal, while 126 is a Q channel output terminal. Again 1
Reference numeral 25 denotes a newly provided serial / parallel converter which converts the input bit string from the input terminal 127 into a parallel system and stores it in the reception memory. Here, 12 is, for example, an I-channel input terminal, and 127 is a Q-channel input terminal.

FIG. 12 will be briefly described. Input data from the input terminal 2 is read out to the CPU side through the compression memory 104, divided into two systems in a predetermined format, scrambled, and added with a preamble and stored in a predetermined area of the transmission memory 106. To be done. Now T
If the DMA frame structure and its symbol rate are the same, the number of bits that can be transmitted in one burst is doubled, so that the number of data read per frame through the input terminal 2 is doubled. However, for example, convolutional coding processing with a coding rate of 1/2 (also described in Chapter 3.2, etc.) is added to the transmission processing described as an example in FIG. Even if the number of input bits per frame from the terminal 2 is the same, there may be two channels of output channels.

On the other hand, the transmission memory 106 has the TX-1,
In each of the TX-2 and TX-3 regions, B
Areas for storing transmission processing bits of new channels are provided corresponding to 1, B2, B3, B4. Then, these bits are output from the output terminal 126 in a serial manner through the parallel / serial converter 124.

Similarly, the serial type bit string from the input terminal 127 added on the receiving side is converted into the serial / parallel converter 125.
Is converted into a parallel system and stored in the reception memory 110. For this purpose, B1 and B are further added to the RX-1 and RX-2 areas of the receiving memory 110 shown in FIG. 5, respectively.
Areas for storing reproduction bits of new channels are provided corresponding to 2, B3 and B4. The reception bits for two systems stored in the reception memory 110 are processed for each system, combined in a predetermined format, stored in the expansion memory 111, and output from the output terminal 16 through the parallel / serial converter 112. The number of output bits per frame is twice that in the case described with reference to FIG.

Incidentally, it is necessary to appropriately change the configuration of each address counter in response to the change of the memory map.

The above is 2 bits for transmission processing bit output and reproduction bit input.
12 is an explanation of the embodiment shown in FIG. 12 when it becomes a system. Of course, in FIG. 12, it is possible to add the constituent elements described in FIG. 11 as a modification from FIG.

Further, in FIG. 1, FIG. 11 and FIG. 12, compression memory and decompression memory, and corresponding input / output terminals with the ground side, serial / parallel converter, parallel / serial converter are added as necessary. However, it is possible to increase the number of channels with the ground side.

At this time, those address counters are appropriately added or shared.

〔The invention's effect〕

As described above, according to the data processing device of the present invention, it has two storage areas, and alternatively, the transmission data is written in the area unit on the basis of the first reference timing signal, and these are written. The first transmission means for storing the transmission data, and the transmission data read out by selectively reading the transmission data from the two storage areas of the first storage means based on the first reference timing signal. Has a plurality of storage areas and a converting means for transmitting the data in a format corresponding to the burst and writing the plurality of storage areas on the basis of the first reference timing signal, and storing the written data. The first reference timing signal is supplied to the second storage means and the first and second storage means and the conversion means based on the received data in burst form. Based on the first reference timing signal supplying means for supplying and the second reference timing signal, the transmission data processed corresponding to the burst alternatively from the plurality of storage areas of the second storage means. A second reference timing signal for reading, modulating the read transmission data, and outputting the modulated reference data, and a second reference timing signal having the same period as the first reference timing signal to the modulating means. Since the supply means is provided, conventionally, real-time processing is required by hardware, and the transmission and reception data processing, which has a low degree of freedom of change in order to correspond to the change of the system parameter, is converted to the conversion means. A conversion means, a modulation means, and a first and a second realized by a memory provided so as to be sandwiched therebetween.
The storage means can execute this, is highly versatile, can easily respond to changes in system parameters, and has an effect that the device can be configured easily.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a data processing device and its peripherals according to an embodiment of the present invention, and FIG. 2 is a configuration example of a frame and a burst used in a TDMA communication system to be processed by the data processing device. FIG. 3 is a diagram showing an example of a memory map of a compressed memory in the embodiment apparatus of FIG. 1,
Similarly, FIG. 4 is a diagram showing a memory map example of the transmission memory,
Similarly, FIG. 5 is a diagram showing a memory map example of the receiving memory,
FIG. 6 is a diagram showing a memory map example of the decompression memory,
FIG. 7 (a) is a diagram showing an example of the configuration of a compression memory of the device and its peripheral circuits, FIG. 7 (b) is a time chart diagram of its main part, and FIG. 8 (a) is a diagram of the device. FIG. 8B is a diagram showing a configuration example of a transmission memory and its peripheral circuits, FIG. 8B is a time chart diagram of its main part, FIG. 9 is a diagram showing a configuration example of a toggle control counter of the device, and FIG. a), (b), and (c) are diagrams showing a configuration example of an address counter, respectively, and FIGS. 11 and 12 are circuit configuration diagrams of the present device and its periphery showing another embodiment of the present invention, respectively. FIG. 13 is a diagram showing a configuration example of a circuit corresponding to the conventional device and its peripheral circuits, and FIG. 14 is a diagram showing a circuit example of a conventional scrambler. 1 ... Data processing device, 2, 12, 127 ... Input terminal, 8, 10, 16, 126 ... Output terminal, 100 ...
Microprocessor, 101 ... Program memory, 1
02 ... work memory, 103, 109, 125 ... serial / parallel converter, 104 ... compression memory, 10
5 ... Data bus, 106 ... Transmission memory, 107, 1
08,112,124 ... Parallel / serial converter,
110 ... Reception memory, 111 ... Expansion memory, 113
...... Address bus, 114 to 117 ...... First to fourth address counters, 118 ...... Toggle control counter, 11
9 ... Digital signal processor, 120 ... DMA controller, 121 ... Interface memory, 12
2, 123, ... First and second delay circuits. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (4)

[Claims] 1. The transmission data is converted into a burst signal,
In a data processing device for a TDMA communication system that performs time division multiple access communication based on the converted burst-shaped transmission data, the data processing device has two storage areas and these two areas are based on a first reference timing signal. Alternatively, the transmission data is written in units of areas, and the first storage means for storing the written transmission data and the storage area of the first storage means based on the first reference timing signal are selected. The transmission data is read out, the read transmission data is transmitted, and a conversion means for outputting the transmission data in a format corresponding to a burst and a plurality of storage areas are provided, and the plurality of storage areas are output based on a first reference timing signal. To the second storage means for writing the written data in the storage area and storing the written data, and the first and second storage means and the conversion means. In contrast,
Based on the received data in burst form, the first reference timing signal supplying means for supplying the first reference timing signal, and the plurality of second storage means based on the second reference timing signal. Alternately, from the storage area, the transmission data processed corresponding to the burst is read out, the read transmission data is modulated and output, and the first reference timing signal is supplied to the modulation means. And a second reference timing signal supply means for supplying a second reference timing signal of the same cycle as the above. 2. The data processing apparatus according to claim 1, wherein the second storage means has three storage areas. 3. The second reference timing signal is the first reference timing signal.
The data processing device according to claim 1, wherein the data processing device has different phases with respect to the reference timing signal. 4. The data processing apparatus according to claim 1, wherein the conversion means is composed of a CPU.