JPH0650855B2 - Digital signal phase difference absorption circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention is applied to transfer data between two digital systems operating in different phases even if the system clock frequencies are exactly the same. The present invention relates to a phase difference absorption circuit for digital signals.

[Outline of Invention]

The present invention provides a phase difference absorption circuit for a digital signal, which receives input digital data and an external clock synchronized with the input digital data and forms output digital data synchronized with an internal clock having the same frequency as the upper external clock. , By connecting a plurality of sets of latches and gate circuits in cascade, and controlling the gate circuits so that the corresponding one of the plurality of latches is turned off when performing a latch operation, without using a memory, It is designed to absorb the phase difference between digital signals.

[Conventional technology]

Data transfer between digital devices such as digital video signal processing devices will be described with reference to FIGS.

As shown in FIG. 5, when data is transferred between the two digital systems 71 and 72, a clock is transmitted from the systems 71 to 72 together with the data. Clock CK1 running system 71 and system 72
It is assumed that the clock CK2, which is used for moving the clocks, has the same frequency but different phase.

The system 72 cannot simply latch the data sent from the system 71 with the clock of the system 72. Therefore, if the system 72 is moved by the clock CK1 sent together with the data instead of the clock CK2, the data is delivered to the system 72 without being mis-latched.

However, when the transmitted clock CK1 is used as the clock of the system 72, the following problems occur.

Firstly, during the long-distance transmission of the clock CK1, interference with data causes a lot of jitter in the clock, resulting in malfunction. Secondly, as the number of stages of the system increases, the waveform of the clock deteriorates and it becomes necessary to shape the clock pulse width.

Further, even if the above-mentioned problems are solved, the connection shown in FIG. 6 cannot be dealt with. FIG. 6 shows a connection in which data and clocks are transmitted from the system 81 to the systems 82 and 83, respectively, and data and clocks are transmitted from these systems 82 and 83 to the system 84.

In this connection, generally system 81 to system 8
2 cable distance and system 81 to system 83
The distance of the cable to will be different. Therefore, the phases of the received clocks are different in system 82 and system 83. Since the systems 82 and 83 are operated by the clocks having different phases, the system 8
2 and the clocks generated from the system 83 have phases different from each other. As a result, system 84 cannot determine which clock, system 82 or system 83, should be used as the system clock.

Conventionally, in the case of the connection of the digital equipment shown in FIG. 6, each system was allowed to operate by itself with a stable clock without jitter. Therefore, a memory such as a FIFO memory capable of asynchronous read / write is provided in the data input section of the system to absorb the relative phase difference between the external system clock and the internal system clock.

[Problems to be solved by the invention]

In the case of high-speed data such as a digital video signal having a sampling frequency of 14 MHz, it is necessary to parallelize two memories to form a phase difference absorbing memory. Therefore, there is a drawback that the circuit scale increases.

Therefore, an object of the present invention is to provide a phase difference absorbing circuit that can absorb the phase difference between an external clock and an internal clock without using a memory. The present invention can realize a phase difference absorption circuit having a small circuit scale even in the case of high-speed data such as a digital video signal.

[Means for solving problems]

According to the present invention, the input digital data and the external clock CKW synchronized with the input digital data are input, and the internal clock CKR having the same frequency as the external clock CKW.
In a phase difference absorption circuit for digital signals that is adapted to form output digital data in synchronization with the above, at least three latch means (3 to 6) to which input data are supplied in parallel, and latch means from the external clock CKW. Means (7, 9, 10) for forming latch control signals in phases corresponding to the number of latch means (3-6) in synchronism with an external clock CKW for sequentially latching input data at (3-6); Each of the latch means (3 to 6) is supplied with the output of the gate means (23 to 26) which sequentially turns on one cycle of the internal clock CKR by the gate control signal, and one of the latch control signals. 1 latch control signal and this first latch control signal
Alternatively, a means (31) for selecting either the second latch control signal whose phase is changed by 1/2 cycle of the external clock CKW based on the selection signal, or the signal selected by the selection means (31). Jitter detection means for detecting whether or not jitter is present, and selection for instructing to select the second latch control signal if jitter is detected, and select the first latch control signal if jitter is not detected. The signal generating means (50, 51) and the latch control signal selected by the selecting means (31) are delayed in synchronization with the internal clock CKR, and the latch means (3 to 6) corresponding to the gate means perform the latch operation. And a means (42, 27) for generating a gate control signal for controlling the gate means so that the jitter detecting means is turned off when performing the shift detection. The selected latch control signal provided between the input terminals of the shifter (41, 42, 43) and the shift registers (41, 42, 43) is delayed for a time sufficiently shorter than the cycle of the internal clock CKR. It is characterized by comprising delay means (35-36) and comparison means (47, 48, 49) for comparing outputs of different stages in each of the plurality of shift registers (41, 42, 43). This is a phase difference absorption circuit for digital signals.

[Action]

A gate control signal is generated from a signal that defines the timing of the latch control signal. The gate control signal has a predetermined phase difference with respect to the latch control signal. Therefore, when the latch means 3 to 6 are performing the latch operation, the corresponding gate means is prevented from turning on.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, for example, 8-bit parallel input data is supplied to the input terminal 1 represented by INDATA. In FIG. 1, CKW represents an external clock supplied together with input data, and CKR represents an internal clock on the system side which receives the data. Input data is supplied to the latch 2 and sequentially latched by the external clock CKW.

On the output side of the latch 2, four latches 3, 4, 5, 6 are provided in parallel. An external clock CKW and a clock enable signal from the shift register 7 are supplied to these latches 3 to 6. The output signal of the multiplexer 8 is supplied to the shift register 7 as an input.

NAND gate 1 is connected to one input terminal of multiplexer 8.
An output signal of 0 is provided. The NAND gate 10 has
The parallel output of the 2-bit counter 9 is supplied. The counter 9 counts the external clock CKW, and the NAN
At the output of the D gate 10, a pulse that becomes'L '(low level) is generated every four clocks. The clock from the input terminal 12 indicated by SWIN is supplied to the other input terminal of the multiplexer 8 via the latch 11.

An external clock CKW is supplied to the shift register 7 as a shift pulse, and a clock enable signal which becomes “L” sequentially is generated at each of four outputs of the external clock CKW. Each of the clock enable signals is supplied to the latches 3-6. Each of the latches 3 to 6 can latch the input data only during the period of “L” of the clock enable signal. Further, the clock enable signal supplied from the shift register 7 to the latch 4 is taken out to the output terminal 16 indicated by SWOT via the latch 15.

Gate circuits 23 and 24 are provided on the output side of the latches 3 to 6, respectively.
25 and 26 are provided. These gate circuits 23-2
An output control signal from the shift register 27 is supplied to 6. The gate circuits 23 to 26 are turned on only when the output control signal is'L '. An internal clock CKR is supplied to the shift register 27 as a shift pulse, and an output control signal is formed in synchronization with the internal clock CKR.

The output control signal supplied from the shift register 27 to the gate circuit 24 is SR via the latch 28.
It is taken out to the output terminal 29 indicated by OT. Gate circuit 2
Output data 3 to 26 are supplied to the latch 22 and sequentially latched by the internal clock CKR. This latch 22
Output data is taken out to the output terminal 21 indicated by OTDATA.

The timing at which each of the gate circuits 23 to 26 is turned on needs to avoid a period during which a latch corresponding to each gate circuit is performing a latch operation. That is, latch 2
This is to prevent 2 from receiving data in the process of changing. For example, during the period in which the latch 3 is latching, the gate circuit 25 that is farthest away in time is controlled to be turned on. The relationship between the latch performing the latch operation and the gate circuit turned on is shown as follows.

(Latch) → 3 → 4 → 5 → 6 → 3 → 4 ... (Gate circuit) → 25 → 26 → 23 → 24 → 25 → 26 .. The gate circuits 23 to 26 are controlled to turn on due to the time relationship. In order to perform this control, the timing of the output control signal generated by the shift register 27 is defined to have a predetermined relationship with the timing of the clock enable signal generated by the shift register 7.

The output signal of the NAND gate 10 is supplied to one input terminal of the multiplexer 31 via the latch 14. At the same time, the output signal of the latch 14 is supplied to the other input terminal of the multiplexer 31 via the latch 32. The latch 32 has an internal clock C via an inverter 33.
KR is supplied. The multiplexer 31 is a JK described later.
It is controlled by the output of the flip-flop 51.

An external clock CK is sent to the latch 32 via an inverter 33.
W may be supplied.

The output of the multiplexer 31 is supplied to the shift register 41 and the inverters 34, 35, 36, 37 connected in series. The inverters 34 to 37 form a delay circuit, and the output signal of the connection point of the inverters 35 and 36 is supplied to the input terminal of the shift register 42. The output signal of the inverter 37 is supplied to the input terminal of the shift register 43.

An internal clock CKR is supplied as a shift pulse to these shift registers 41, 42 and 43. The output of the multiplexer 31 is latched by the internal clock CKR and taken into the shift registers 41, 42, 43.

The output of the second stage of the shift register 42 is supplied to one input terminal of the multiplexer 30. Multiplexer 3
The other input terminal of 0 is the input terminal 38 indicated by SRIN.
Is supplied via the latch 39. The output signal of the multiplexer 30 is supplied to the shift register 27.

The terminal 13 in which the states of the multiplexers 8 and 30 are indicated by MD
It is controlled by the mode setting signal from. This mode setting signal has a data parallel bit number of 8 bits, and when the configuration shown in FIG. 1 is used independently and when the data parallel bit number is more than 8 bits, the configuration shown in FIG. This is a signal for switching between when connecting and when connecting. When the circuit shown in FIG. 1 is used as the second and subsequent unit configurations of the parallel connection, the multiplexers 8 and 30 respectively select the signals from the terminals 12 and 38.

The output of the first stage of the shift registers 41 and 42 is EX.
-Is supplied to the OR gate 44. The output of the first stage of the shift registers 41 and 43 is supplied to the EX-OR gate 45. The output of the first stage of the shift registers 42 and 43 is EX-
It is supplied to the OR gate 46. The delay time due to the inverters 34 to 37 is short, and the output of the latch 14 is synchronized with the external clock CKW. Therefore, EX
-E In the OR gates 44, 45, 46, the two inputs do not match and their outputs are'H '(high level).
When the X-OR gate is present, the phases of the external clock CKW and the internal clock CKR are extremely close to each other, which means that the shift register 42 may erroneously latch the output of the multiplexer 31.

Further, the output of the first stage of each of the shift registers 41, 42 and 43 and the output of each of the fifth stage of each of the shift registers 41, 42 and 43 are the EX-OR gate 4.
7,48,49. Since the signal from the multiplexer 31 is a signal that becomes'L 'every four clock cycles, if there is no jitter in this signal,
The first stage output of each shift register 41, 42, 43 and the fifth
The output of the second stage becomes the same, and the EX-OR gates 47, 4
Each output of 8 and 49 becomes'L '.

However, when the phases of the external clock CKW and the internal clock CKR are close to each other and there is jitter, the output of the first stage of each shift register 41, 42, 43 does not match the output of the fifth stage, and EX- OR gates 47, 48, 49
At least one output of is'H '. 6 EX-O
The outputs of the R gates 44 to 49 are supplied to the OR gate 50.

The output of the OR gate 50 is the J of the JK flip-flop 51.
The inverted signal of the output of the OR gate 50, which is supplied to the input terminal, is supplied to the K input terminal of the JK flip-flop 51. The internal clock CKR is supplied to the clock terminal of the JK flip-flop 51. When the output of the OR gate 50 is'H ', (J =' H ', K =' L '),
The output of the JK flip-flop 51 is the internal clock CKR.
Invert from the previous state in synchronization with. When the output of the OR gate 50 is'L ', (J =' L ', K =' H '), and the output of the JK flip-flop 51 remains in the previous state. The multiplexer 31 is controlled by the output of the JK flip-flop 51.

Therefore, with the multiplexer 31 selecting the output of the latch 14, the external clock CKW and the internal clock C
The phase of KR approaches and the output of OR gate 50 becomes'H '.
Then, the output of the JK flip-flop 51 is inverted. As a result, the pulse signal generated at the output of the multiplexer 31 has its phase shifted by 1/2 cycle of the internal clock CKR. Therefore, the internal clock CKR
When the phase of the external clock CKW is close to that of the external clock CKW, the phase of the pulse supplied to the shift register 27 is forcibly changed by 1/2 cycle of the internal clock CKR. In this case, the latch 32 may be supplied with the external clock CKW.

The operation of the above-described embodiment of the present invention will be described with reference to FIGS. 2 and 3.

FIG. 2 shows the operation when the external clock CKW (FIG. 2A) and the internal clock CKR (FIG. 2F) are out of phase, for example, when the phases are different by 180 degrees. FIG. 2B shows
The output signal of the NAND gate 10 is shown. The output signal of the NAND gate 10 becomes'L 'every four cycles of the external clock CKW.

The output signal of the NAND gate 10 is supplied to the shift register 7 via the multiplexer 8, and four-phase clock enable signals are generated at the four output terminals of the shift register 7 as shown in FIG. 2C. Therefore, the input data S0, S1, S2, S3, S4, S5, ... From the latch 2 are sequentially latched in the latches 3, 4, 5, 6 as shown in FIG. 2D.

FIG. 2E shows the output signal of the NAND gate 10 latched by the latch 14. As shown in FIG. 2, when the phase difference between the external clock CKW and the internal clock CKR is large, the multiplexer 32 selects the output signal of the latch 14 (E in FIG. 2).

The output signal of the latch 14 is supplied to the shift register 42 via the inverters 34 and 35, and the shift register 4
The output signal shown in FIG. 2G is generated in the first and second stages of No.2.

The output signal of the second stage of the shift register 42 is supplied to the shift register 27 via the multiplexer 30. Therefore, the four-phase output control signals shown in FIG. 2H are generated from the shift register 27. Each phase of this output control signal is applied to the gate circuits 23 to 26.
Is supplied to. The output signals of the gate circuits 23 to 26 are latched by the latch 22, and the output signal of the latch 22 shown in FIG.

For example, in the gate circuit 23, at the top in FIG.
Is supplied with the listed output control signals,
It is turned on during the'L 'period of this output control signal. At this time, the input data from the latch 3, for example, S0, is taken out from the output of the gate circuit 23. This period corresponds to the period in which the latch 5 latches the input gater S2, as shown in FIG. 2D.

FIG. 3 shows the operation when the external clock CKW (FIG. 3A) and the internal clock CKR (FIG. 3F) are very close in phase. Similarly to FIGS. 2B, 2C, 2D, and 2E, each of FIGS. 3B, 3C, 3D, and 3E has a NAND gate. 10 output signals, four-phase clock enable signals generated at the four output terminals of the shift register 7, output signals of the latches 3, 4, 5, 6 and the output signal of the NAND gate 10 latched by the latch 14. . Further, FIG. 3G shows an output signal of the latch 32. The output signal of the latch 32 is 1 / the internal clock CKR.
It has a delay of two cycles with respect to the output signal of the latch 14.

As shown in FIG. 3, when the phase difference between the external clock CKW and the internal clock CKR is extremely small, the multiplexer 31 selects the output signal of the latch 32 (G in FIG. 3).

The output signal of the multiplexer 31 is the inverters 34 and 35.
To the shift register 42, and the output signal shown in FIG. 3H is generated at the first stage and the second stage of the shift register 42.

The output signal of the second stage of the shift register 42 is supplied to the shift register 27 via the multiplexer 30. Therefore, the four-phase output control signals shown in FIG. 3I are generated from the shift register 27. Each phase of this output control signal is applied to the gate circuits 23 to 26.
Is supplied to. The output signals of the gate circuits 23 to 26 are latched by the latch 22, and the output signal of the latch 22 shown in FIG. 3J is taken out to the output terminal 21.

For example, the gate circuit 23 is supplied with the output control signal described at the top in FIG. 3I, and is turned on during the'L 'period of this output control signal. At this time, the input data S0 from the latch 3 is taken out from the output of the gate circuit 23. This period is the third
As shown in FIG. D, this corresponds to the period in which the latch 5 starts to latch the input data S2.

As described above, the external clock CKW and the internal clock CK
The latch 22 can reliably latch the data regardless of whether the relative phases of R are close to each other or separated from each other.

One embodiment of the present invention has a configuration capable of processing input data having a parallel bit number of more than 8 bits.
FIG. 4 shows the configuration when the number of parallel bits of input data is 32 bits. In FIG. 4, 61, 62, 63,
Blocks indicated by 64 are phase difference absorption circuits similar to those in FIG.

In the phase difference absorption circuit 61, for example, the upper 8
Bits are provided. The lower 8 bits of the input data are supplied to the respective input terminals of the phase difference absorption circuits 62, 63, 64. The timing signal related to the clock enable signal from the phase difference absorption circuit 61 and the timing signal related to the output control signal are supplied to the phase difference absorption circuit 62. Similarly, the phase difference absorption circuit 62
To 63 are supplied with these timing signals, and the phase difference absorption circuits 63 to 64 are supplied with these timing signals.

Further, the mode setting signal of the phase difference absorption circuit 61 is set to “L”, and the multiplexers 8 and 3 in the phase difference absorption circuit 61 are set.
A 0 is set to select the internally generated signal.
The mode setting signals of the other phase difference absorbing circuits 62, 63, 64 are set to "H", and the multiplexers 8 and 30 in these phase difference absorbing circuits select the timing signal from the other phase difference absorbing circuits. Set to state.

That is, the other phase difference absorption circuits 62, 63, 64 operate at the same timing with reference to the operation timing of the phase difference absorption circuit 61. The input terminal of the signal from the outside of the phase difference absorption circuit and the output terminal of the signal to the outside,
Latches 11, 15, 28, 39 are provided for delay compensation, respectively.
Is provided. The 8-bit output data of each of the phase difference absorption circuits 61 to 64 is collected and output as 32-bit output data.

〔The invention's effect〕

According to the present invention, digital signals can be transferred between asynchronous systems without using a memory. Therefore, unlike the case where the buffer memory is used when processing high-speed data such as a digital video signal, it is possible to prevent the circuit scale from increasing. Further, according to the present invention, the jitter is detected not based on the external clock CKW itself but on the latch control signal (in the above embodiment, the latch control signal becomes "L" every four cycles). Even in the case of a short period jitter within a period, it is possible to reliably detect this by detecting the period of four cycles. Further, for detecting the jitter, a plurality of shift registers are provided, a delay circuit sufficiently shorter than the clock period is inserted in the input terminal thereof, and a comparison means for comparing outputs of different stages of each shift register is provided. Therefore, by opening the gate corresponding to the latch which is being latched, it is possible to reliably prevent the data in the process of being changed.

[Brief description of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, FIGS. 2 and 3 are time charts for explaining the operation of one embodiment of the present invention, and FIG. 5 and 6 are block diagrams when applied to processing, and are block diagrams for explaining a conventional phase difference absorption circuit for digital signals. Description of main symbols in the drawings 1: Data input terminal, 3, 4, 5, 6: Latch, 7,
27, 41, 42, 43: shift register, 8, 30,
31: multiplexer, 21: data output terminal, 2
3, 24, 25, 26: Gate circuits.

Claims (1)

[Claims] 1. A phase difference absorption circuit for a digital signal, wherein input digital data and an external clock synchronized with the input digital data are input to form output digital data synchronized with an internal clock having the same frequency as the external clock. In at least three latch means for supplying the input data in parallel, and in synchronization with the external clock for sequentially latching the input data from the external clock to the latch means,
Means for forming latch control signals of phases corresponding to the number of the latch means, gate means for supplying each output of the latch means and sequentially turning on one cycle of the internal clock by the gate control signal, and the latch A first latch control signal, which is one of the control signals, and a second latch control signal obtained by changing the phase of the first latch control signal by 1/2 cycle of the internal clock or the external clock. Means for selecting any one of the above based on a selection signal, a jitter detecting means for detecting whether or not there is jitter in the signal selected by the selecting means, and the second latch when the jitter is detected. A control signal selecting means for generating the selection signal for instructing selection of the first latch control signal if the jitter is not detected; The gate control signal for delaying the latch control signal selected by the stage in synchronism with the internal clock so as to turn off when the latch means corresponding to the gate means performs a latch operation. The jitter detecting means is provided with a plurality of shift registers and the selected latch control signal provided between the input terminals of the plurality of shift registers, the internal clock cycle A phase difference absorption circuit for digital signals, comprising: delay means for delaying a sufficiently shorter time; and comparison means for comparing outputs of different stages in each of the plurality of shift registers.