JPH0650918B2 - Time division multiple time switch control system - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time division multiplex time switch control system for time division switching, and more particularly to a time division multiplex time switch which handles various types of traffic at various speeds in a multiple manner. Regarding control method.

[Prior art]

Currently, Digital Integrated Services Network (ISDN: Integrat)
ed Service Digital Network) is being energetically pursued both inside and outside the country. ISDN is a network that comprehensively handles not only voice communication but also various communication services such as data images and images.

In this case, if these various communication services can be provided by a single network with little overhead, simplification of the communication network,
It is considered that there are considerable advantages such as centralized maintenance and operation. It is also well known that ISDN is required to provide not only services of 64 kb / s or 1 / n or n times that of voice communication, but also communication services in an extremely wide speed range including images. Therefore, it is desired to realize a switch with a single architecture that can handle these as easily and uniformly as possible.

Based on the above idea, a new switching system called "line / packet integrated switching system" (patent application) for exchanging various communication services in an extremely wide speed range with a single architecture integrated switching system including circuit switching / packet switching. Japanese Patent Application No. 58-044740 and Japanese Patent Application No. 58-095169, the following document 1
And 2) are proposed.

In the method of the invention described in the above-mentioned documents 1 and 2, as shown in FIG. 2, an exchange is used as a building block communication node, and these are connected by a plurality of loops, and a plurality of lines extending between specific communication nodes are provided. For example, a method is adopted in which an exchange call is assembled into one mixed packet and sent / received at every 125 μsec voice sampling period.

The "line / packet integrated switching system" according to the documents 1 and 2 will be briefly described below with reference to FIG. However, in FIG. 2 and the following description, the additional portion generated by the mixture of packet calls relating to the above method is not directly related to the description of the present invention, and therefore will be omitted.

In FIG. 2, the INF unit (interface circuit) in each communication node has an interface function for accommodating information from a subscriber line and an inter-office relay trunk group accommodated in the exchange, and digitally multiplexes these information. Alternatively, it has a function of demultiplexing. Further, the time division multiplex time switch memory circuit T temporarily buffers the call information in the digital multiplexed channel from the INF section in the forward direction from the INF section to the plurality of loops to convert the time phase between channels ( (Time switch function), and a function of editing a plurality of circuit-switched calls extending between specific communication nodes into a mixed packet format, which will be described later with reference to FIG. 3, and a transmission waiting function for a plurality of loops,
The reverse function described above is provided in the reverse direction from the multiple loops to the INF section. Further, CM in the figure is a time switch control memory circuit, which is an address for writing the digitally multiplexed call information coming from the INF section to the time division multiplexing time switch memory circuit T for each time slot, or vice versa. Divided / multiple time switch memory circuit T to INF
It has a function to specify the address from which the call information to be digitally multiplexed and sent to each unit is read out for each time slot.

Further, in FIG. 2, D / I is an interface circuit between the time division multiplex time switch memory circuit T of the communication node and a plurality of digital multiplex loops (a plurality of loops), and a call from the communication node is made at an idle time position on the plurality of loops. It has a function of inserting information (Insert function), or conversely, a function of branching communication information addressed to its own module from multiple loops (Drop function).

FIG. 3 shows a mixed packet format used when assembling a plurality of circuit-switched calls spanning the specific communication nodes shown in FIG. 2 into one mixed packet and transmitting / receiving it through a loop. In the figure, DA is the number of the incoming communication node, SA is the number of the outgoing communication node, and DA and SA form a header section. Further, CH _{1 to} CH _n are n-channel call message parts in which a call is being made at the same time between the call-originating communication node and the call-receiving communication node, respectively. The size of the call message part of each channel is secured in proportion to the communication speed of the circuit switched call. For example, in the case of voice, the information amount of one voice channel included in one mixed packet can be one sample (8 bits). In addition, this method enables uniform switching of multiple communication services in an extremely wide speed range.

Now, an economical and concrete realization method of the conventional "line / packet integrated switching system" described above, in particular, a time division multiplex time switch memory circuit T shown in FIG. 2 and a time switch control memory which is its control circuit. As an economical and concrete method for realizing the circuit CM, a time division multiple time switch circuit shown in FIG. 4 (Japanese Patent Application No. 58-155581, reference 3).
Is proposed.

FIG. 4 is a time-division multiplex time switch memory circuit T described in FIG. 2 and a time switch control circuit CM for controlling the same.
FIG. 3 is a block diagram showing the outline and operation of the configuration of FIG. However, for the sake of simplicity in FIG. 4, the time division multiplex time switch memory circuit T shows a schematic circuit configuration related to the forward direction of the signal flow from the INF section to the loop side in FIG. The flowing circuit is omitted (the circuit in the reverse direction has almost the same structure as the forward direction, and can be easily inferred because the operation is just the reverse relationship).

The time division multiplex time switch memory circuit T shown in FIG. 4 is composed of two surfaces of the memory circuit configured by a so-called random access memory (RAM). The first memory side writes the call information for one frame of each digital multiplexed channel received from the INF section in an even time frame, and reads it in the next odd frame to execute the loop branch / insertion shown in FIG. It is sent to the interface circuit D / I having a function. On the contrary, the second memory surface writes the call information in the odd time frame and reads the call information in the next even time frame. The call information of the digital multiplexed channels from the INF section to the memory circuits of these two sides is written to the memory address designated by the time switch control memory circuit CM for each input time slot (random writing). The time switch control memory circuit CM, on the time division multiplex time switch memory circuit T, indicates that the call information of the input channel is addressed to the communication node # 1 in order from the head address of the memory (node in the figure). # 1) call information, node # 2 call information, ...
..., the call information addressed to the node #N, and the call information addressed to the communication node having the same number (for example, # 1), if there are n calls at that time, are also included in the channels # 1, # 2.
, #N (CH ₂ , ..., CH _{n in} FIG. 3) are arranged in order, indicating the write address for each input time slot.

As described above, as a result of writing the call information of the input channel to the time division multiplex time switch memory circuit T, the content is read from the head address at a speed consistent with the transmission speed of the loop side sequentially (sequential read). By adding the destination node address DA and the source node address SA as shown in FIG. 3 to each of a series of call information groups addressed to the same communication node, a desired mixed packet can be formed.

The reason why the time division multiplex time switch memory circuit T is provided on two surfaces for even and odd frames is to avoid the phenomenon of "slip" which is well known to those skilled in the art (for details, refer to the above-mentioned document 3). .

By the way, on the time division multiplex time switch memory circuit T, in order to arrange and write call information in order from the head address to # 1 channel, # 2 channel, ... Alternatively, the content of the switch control memory circuit CM needs to be updated each time a new call occurs. Now, for example, # addressed to communication node #i
When the call of the j channel is recovered, if this call uses k words on the time division multiplex time switch memory circuit T, that is, if this call has a communication speed k times the basic communication speed, On the multi-time switch memory circuit T, the memory use area of the call of each communication channel, which has used the memory area located in the older number than this, may be advanced to the address k. To do this, enter C for each input time slot.
When the memory content of M is read out and the result is sent to the time division multiplex time switch memory circuit T, the result is compared with the address indicating the area used by the restored call, and when the result is larger than the address of the restored call, K the contents
Just subtract and rewrite to the original position. Conversely, k
When a double call is made, the memory usage of the call of each communication channel, which uses the memory area located in the oldest place from the area to be used by the new call on the time division multiplex time switch memory T, is used. It is necessary to move the area down by k addresses.
For that purpose, as in the case of the memory contents of the CM, as described above, only the contents of the memory contents larger than the address indicating the area used by the new call may be added by k. Although not shown in the figure, the ASU (address shift unit) in FIG. 4 is an operation for performing the above-mentioned comparison of the memory contents of the CM and the correction operation according to an instruction from the control processor that controls the exchange call processing. Circuit.

[Problems of conventional technology]

In the conventional method described above, two communication nodes connected to the loop (hereinafter referred to as node i and node j) are communicating and a call in the direction from node i to node j is restored or a new call occurs. In such a case, the length of the mixed packet assembled in the time division multiplex time switch of the transmitting node i changes according to the above-described operation principle, the changed mixed packet is transmitted on the loop, and the time division multiplex in the receiving node j is performed. Written to the time switch. The mixed packet after this change goes down when the call data after the call or restoration channel is called, and goes up when the call data is restored,
Since the position is shifted, when the call data forming the mixed packet is read at the read address supplied by the switch control memory before the change at the node j,
Interference occurs because another call data is read.

That is, between the communication nodes, the time switch control memory needs to be updated at the time of making and receiving a call by synchronizing the time in frame units between the call originating and terminating nodes. Since no means for updating the switch control memory has been provided, the interference cannot be completely prevented.

[Object of the Invention]

An object of the present invention is to provide a time division multiplex time switch control system in which the frame times for updating the time switch control memories of respective nodes associated with call origination and restoration are made coincident to prevent the above-mentioned interference.

[Structure of Invention]

The present invention relates to a time division multiplex time of a communication system comprising a plurality of communication nodes having a time division multiplex time switch and a time switch control memory for controlling the time division multiplex time switch, and a communication network connecting the communication nodes. In a time division multiplex time switch control system for controlling a switch, the communication node is provided with an N-ary counter for counting the number of time-division multiplex frames and means for matching the value of the N-ary counter of each communication node. When communication is set up or released between the communication nodes, a value m of 0 ≦ m ≦ N−1 is selected each time by a meeting between the communication nodes, and thereafter, the value of the N-ary counter is selected by the communication node. When the value becomes equal to the value m, the contents of the time switch control memory of the communication node are set or restored by the communication. And changes to so that.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a schematic diagram showing the configuration of each node in the embodiment of the time division multiplex time switch control system of the present invention. First
The figure shows the case where the input call signal coming from the INF section is transmitted to the INF section on the output side through the route of the transmission node → loop → reception node. The transmitting node is an INF section,
The transmission time division multiplex time switch 10, a signal transmission time switch control memory 11, a transmission loop interface 12, a control processor 13, an N-ary counter 14, and a comparison circuit 15. Further, the receiving node includes an INF unit, a receiving time division multiplex time switch 20, and a receiving time switch control memory.
21, receiving loop interface 22, control processor
23, an N-ary counter 24, and a comparison circuit 25.
Then, the transmitting node and the receiving node have loops # 1 to #
Connected by.

In FIG. 1, the operations of the transmission time division multiplex time switch 10, the transmission time switch control memory 11, and the transmission loop interface 12 are the same as those of the conventional time division multiplex time switch shown in FIGS. 2 and 4. Memory circuit T, time switch control memory circuit CM, interface circuit D / I
And the same respectively.

In addition, the reception time division multiplex time switch 20, the reception time switch control memory 21, the reception loop interface 22.
The operation of is almost the same as the operation of the transmitting side, except that the data flow is in the opposite direction. Further, in FIG. 1, the N-ary counters 14 and 24 count frame times from 0 to N-1. The value of the N-ary counter of each communication node is controlled so as to match by the following procedure, for example. That is, a certain pattern (hereinafter referred to as counter reset data) is defined as data to be transmitted on the loop, and the node receiving this counter reset data clears the N-ary counter of its own node. . At system initialization, one node (system management node, etc.) sends counter reset data onto the loop. Each node connected to the loop receives this,
It clears the N-ary counter of its own node and transfers it to the next node. Since the counter reset data goes around the loop until the node that first sent it receives it again, the values of the counters of all the nodes become 0, and the values of the node counters match.

Thereafter, the N-ary counter counts the frame times from 0 to N-1 by incrementing by 1 every frame time (for example, 125 μs) at each node.

Next, the operation when a new call originates from the transmitting node to the receiving node will be described. The control processor 13 that controls the transmission node reads the value of the N-ary counter 14 and selects the frame time m (0 ≦ m ≦ N−1) for updating the transmission time switch control memory 11 from the value. N
When the value of the binary counter 14 is k (0 ≦ k ≦ N−1), if the frame time m is, for example, (k−1), the transmission time switch control memory 11 is actually updated ( N
-1) After the frame. The transmitting node transmits this frame time m and the update information of the time switch control memory associated with the call to the receiving node via the loop.

The control processor 23, which controls the receiving node, checks whether or not the receiving time switch control memory 21 can be updated at the frame time m designated by the transmitting node. This is because there are cases where the receiving node has already decided to update the receiving time switch control memory 21 with another communication node at the designated frame time m.

In this case, the receiving node uses the receiving time switch control memory 21 at the frame time designated for the transmitting node.
A "frame time block signal" indicating that it is impossible to update is returned. When the designated frame time is vacant, the control processor 23 stores the frame time and the update information of the reception time switch control memory 21 and simultaneously controls the reception time switch at the frame time for the transmission node. A "frame time / space signal" indicating that the memory 21 can be updated is returned. After that, the receiving node compares the frame time with the value of the N-ary counter 24 by the comparison circuit 25, and the control processor 23 updates the reception time switch control memory 21 with the coincident frame.

On the other hand, the transmitting node which has received the reply information, if the reply information is the “frame time block signal”, controls the processor.
The frame time is again selected by 13 and the above-mentioned processing is retried. On the contrary, when the transmitting node receives the "frame time empty signal", the value of the N-ary counter 14 and the frame time for updating the transmission time switch control memory 11 are compared by the comparison circuit 15, and the coincident frame is detected. The transmission time switch control memory 11 is updated with.

In the above, the case where a new call originated between the transmitting node and the receiving node was explained, but the same procedure is used except that the updated information content of the time switch control memory is different even when the call currently in progress is restored. Can be processed by.

In this embodiment, the update processing of the time switch control memory associated with the origination and restoration of a call has been described with respect to one communication node and a maximum of one call. However, the origination and restoration of a plurality of calls in one frame. The same procedure can be applied to a configuration capable of performing. In this case, since the probability that the selected frame time m is blocked by the partner node is reduced, the invalid processing is reduced and the processing capacity of the system is increased. Further, if a system capable of generating and recovering an arbitrary number of calls in one frame is configured, any m (0 ≦ m ≦ N) separated by the minimum time required for meetings between nodes and preparation for update is established. -1),
All that is required is to notify the other node, and no reply is required from the other node. Further, the value of N itself can be made considerably smaller than that of the present embodiment.

The present invention is also applicable to general communication systems having shapes other than those shown in the above embodiments. For example, it is also effective for an ordinary electronic exchange system in which a communication node having a time division multiplex time switch and a time switch control memory is connected by a space division switch, and a communication system in which the communication nodes are connected by a bus. In these systems, the interference as shown in the conventional example of the present invention does not always occur even if the frame time for updating the time switch control memory is different between the communication nodes. However, if the frame time for updating the time switch control memory is different between the transmission node and the reception node, there is a problem that unnecessary data other than the transmission data appears at the reception node. Therefore, by similarly applying the present invention and matching the frame times, these drawbacks can be completely eliminated.

〔The invention's effect〕

As described above, according to the present invention, the frame time for updating the time switch control memory is made to coincide between the sending and receiving nodes when a call is originated and restored, so that interference, which is a drawback of the conventional example, is prevented. The effect that can be obtained is obtained.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a configuration of each node in an embodiment of a time division multiplex time switch control system of the present invention, and FIG. 2 is a block diagram showing a configuration of a communication system to which the present invention is applied, FIG. 3 is a diagram showing an example of a mixed packet format when transmitting and receiving call information between communication nodes which are made into building blocks, and FIG. 4 is a block diagram showing a configuration of a time switch according to the prior art and its operation outline. It is a figure. 10 …… Time division multiple time switch for transmission 11 …… Time switch for transmission Control memory 12 …… Loop interface 13 …… Control processor 14 …… N-ary counter 15 …… Comparison circuit 20 …… Time division multiple time switch for reception 21 …… Time switch control memory for reception 22 …… Loop interface 23 …… Control processor 24 …… N-ary counter 25 …… Comparison circuit INF …… Interface circuit T …… Time division multiple time switch memory circuit CM …… Time Switch control memory circuit D / I …… loop interface circuit ASU …… address shift unit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication location H04Q 11/04 301 B 9076-5K 8529-5K H04L 11/20 102 F

Claims (1)

[Claims] 1. A time division multiplex of a communication system comprising a plurality of communication nodes having a time division multiplex time switch and a time switch control memory for controlling the time division multiplex time switch, and a communication network connecting the communication nodes. In a time division multiplex time switch control system for controlling a time switch, the communication node is provided with an N-ary counter for counting the number of time-division multiplex frames and means for matching the value of the N-ary counter of each communication node, When communication is set up or released between nodes, a value m of 0 ≦ m ≦ N−1 is selected by a meeting between the communication nodes each time,
Thereafter, the communication node changes the contents of the time switch control memory of the communication node so that the communication is set or restored when the value of the N-ary counter becomes equal to the selection value m. A time division multiplex time switch control method characterized by: