JPH065173B2 - Resolver phase error compensation method - Google Patents

Description

The present invention relates to a resolver for detecting the rotational phase of a rotating body, and more particularly to a method for compensating for a phase error of an inductor type resolver.

[Problems of conventional technology]

Simple position detectors with a small number of grooves and conductors for each pole, such as inductor resolvers and inductosins, often include phase errors, and removing them is easy even if the machine structure is complicated. Not really.

Since these errors have good repeatability, that is, repeatability,
Although it is possible to compensate for this on the detection side, there is a drawback that the compensating circuit becomes very complicated in order to achieve high resolution and high accuracy.

[Object of the Invention]

Here, the present invention overcomes the drawbacks of the conventional device, can compensate the phase error of all harmonic orders to be erased including the fundamental wave, has a simple circuit, and can easily set the compensation amount of the resolver. It is an object of the present invention to provide a phase error compensation method.

[Outline of Invention]

The present invention, the phase error due to the structure of the resolver body,
In controlling and compensating the excitation current waveform, when the mutual inductances of the detection winding Wθ and the excitation windings Wα and Wβ are Mα and Mβ, respectively, and the excitation current is iα and iβ, i ² α + i ² β = const ( This is a resolver phase error compensation method in which the control of iβ / iα = Mβ / Mα is performed at equal time intervals with the number of steps per cycle that is at least twice the phase error harmonic order to be erased.

[Principle of Invention]

 The principle of the present invention is as follows.

The machine constants of the current excitation resolver are Mα (θ) and Mβ
It is represented by (θ).

The magnetic flux ψθ linked to the detection winding is ψθ = iα · Mα (θ) + iβ · Mβ (θ) ... (1) Since the detection voltage eθ is eθ = dΨθ / dt (t is time), eθ = diα / Dt ・ Mα (θ) + diβ / dt ・ Mβ (θ) (2) As a result, the vector (diα / dt, diβ / dt) becomes the vector (Mα
When it is orthogonal to (θ) and Mβ (θ)), eθ = 0.

By the way, in the phase modulation method, the time of this detection voltage eθ = 0 is measured.

If it is constant, the vector (iα, iβ) when eθ = 0
Is perpendicular to the vector (diα / dt, diβ / dt), it is parallel to the vector (Mα (θ), Mβ (θ)).

Therefore, iβ / iα = Mβ (θ) / Mα (θ) ……………… (3) where the phase error is tan ⁻¹ [Mβ (θ) / Mα (θ)] − θ Θ obtained from the current phase is tan ^-1 [iβ / i
α], so that tan ⁻¹ [Mβ (θ) / Mα (θ)] − tan ⁻¹ [iβ / iα] = 0.

〔Example〕

A block diagram showing a circuit configuration in one embodiment of the present invention is shown in the drawing.

1 is an oscillator that generates a frequency of 16fe, 2 is a 1/16 frequency divider that forms a reference time axis, 3 is a counter that has 16 steps with an output stage of 4 bits, 5 is k = 0, 1, ..., 15 And δ = 2π /
When it is set to 16, a ROM prestored so as to output an 8-bit isin kδ corresponding to the 4-bit input kδ from the counter 5, and 6 is an 8-bit ic corresponding to the 4-bit input kδ.
ROM stored in advance so as to output os k δ, 7 and 8 D / A converters, 9 and 10 adder / subtractors, 11 and 12 current amplifiers, 13 resolver iβ is β-phase excitation current / iα Is an α-phase excitation current, eθ is a detection voltage, 14 is a bandpass filter, 15 is a synchronous rectifier that synchronously rectifies the output of the bandpass filter 14 corresponding to the reference time axis from the 1/16 frequency divider 2, and 16 is Phase output 4 is a phase error compensation circuit.

The compensation circuit 4 is composed of the following elements.

41 is 4 from the k-th phase error δk previously obtained by measurement.
8-bit output 32 · iδkcos corresponding to bit input kδ
A ROM stored to output (kδ), 42 corresponds to a 4-bit input kδ and outputs an 8-bit output 32 · iδksin (k
ROM stored to output δ), 43 and 44 are D
The A / A converters 45 and 46 are attenuators that attenuate the input to 1/32.

It is assumed that the highest order of the phase error to be erased is 8 and the exciting current vector is corrected at 16 isochronous intervals.

For this purpose, firstly m.alpha (theta), was measured Mβ (θ), relative to θk = kδ, Mα (kδ) + jMβ (kδ) = (kδ) = M · exp [j (kδ + δ k)] where , K = 0, ... 15, M is a real number, and δ _k is the k-th phase error.

On the other hand, the current is expressed as iα (kωτ) + jiβ (kωτ ) = (kωτ) = iexp [j (kδ + δ k)] = iexp [j (kωτ + δ k)], where a .omega..tau = [delta], omega is It is the average excitation current angular frequency.

That is, the current vector may be added in the direction shifted by the phase error δk from the phase detected at each time point.

.delta.k "[delta] = because it is ωτ iexp [j (kωτ + δk )] iexp [jkωτ] (1 + jδ k) Accordingly, the compensation amount is ^{iexp [jkωτ]} · jδ _k.

Where δ _k is And If you try to reduce it by compensation, The resolution of is required.

If 8 bits are used for setting kδ and 8 bits are attenuated to 1/32 for correction of δ _k , a resolution of 13 bits can be obtained.

Therefore, it is sufficient to add Δiα = −iδKsin (kδ) to iα and Δiβ = iδKcos (kδ) to iβ. In the figure, 14 parts surrounded by a broken line are this compensation circuit.

While 16 changes continuously, 16 times higher harmonics generated by adding only in steps are removed by inserting a bandpass filter 14 on the detection side.

As another embodiment of the present invention, ROM4 is used to compensate for unbalance, offset, etc. of the excitation circuit and the signal processing circuit.
1, δk + Δk may be put in the ROM 42 including this amount (Δk is the compensation amount). This can be automatically measured and tuned.

The following means can be considered as another embodiment of the present invention.

Since the figure is a principle diagram, it has complicated hardware, but if it is processed by software using a microcomputer, it will be very easy.

Similar compensation can be performed in the amplitude modulation method.

Although the current excitation is shown in the figure, the same method can be used for voltage excitation.

[Effects of the Invention] Thus, according to the present invention, a number of effects are obtained as described below, which greatly contributes to the field.

It is easy to manufacture detectors such as inductor resolvers and inductosyns, and highly accurate ones can be manufactured cheaply.

Since the detector structure is simple and good, very small size is possible. A linear type can also be easily realized.

Since the inductor type resolver is not affected by the temperature change of resistance, temperature correction is not necessary.

The circuit is relatively simple and the cost is low.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration in an embodiment of the present invention. 1 ... Oscillator, 2 ... Divider, 3 ... Counter, 4 ... Compensation circuit,
41, 42 ... ROM, 43, 44 ... D / A converter, 45, 46 ... Attenuator, 5, 6 ... ROM, 7, 8 ... D / A converter, 9, 10 ...
Adder / subtractor, 11, 12 ... Current amplifier, 13 ... Resolver, 14 ... Bandpass filter, 15 ... Synchronous rectifier, 16 ... Output.

Claims (1)

[Claims] 1. A resolver phase error compensating method for compensating a phase error due to the structure of a resolver body by controlling an exciting current waveform, wherein a mutual inductance of a detection winding Wθ and exciting windings Wα, Wβ is Mα, respectively. When Mβ and the excitation currents are iα and iβ, iα ² + iβ ² = const (constant) iβ / iα = Mβ / Mα The phase error to be erased is controlled at every step of at least twice the high frequency order. Resolver phase error compensation method, characterized in that it is performed at equal time intervals in each cycle.