JPH0652473B2 - Autorhythm playing device - Google Patents

Description

The present invention relates to an autorhythm playing device in which a break pattern is inserted in an autorhythm to eliminate monotonous rhythm.

2. Description of the Related Art In conventional electronic musical instruments and the like, an automatic rhythm playing device that automatically generates a rhythm is used. However, the rhythm generated by this auto rhythm playing device is one pattern, and it is unavoidable that it is monotonous. 1 every 4 bars, 8 bars or 16 bars to eliminate this monotony
An autorhythm playing device that inserts an autorhythm variation that changes the rhythm during a measure is also known, but it is still not sufficient to eliminate the monotony of autorhythm.

The present invention has been made in view of the above-mentioned problems in the conventional form, and an auto rhythm playing device, in particular, a rhythm pattern includes data indicating the sounding timing of each rhythm sound, and whether or not the sounding timing and the current timing match. If a normal rhythm pattern (hereinafter referred to as a normal pattern) is in progress in an autorhythm playing device that uses so-called event-type pattern data that produces a sound for the corresponding data of the autorhythm, the break pattern is generated at any timing. It is an object of the present invention to provide a technique suitable for an auto rhythm playing device that enables the insertion of a rhythm and eliminates monotonous rhythm, and particularly applies a microcomputer system.

In order to achieve this object, in the present invention, a periodic signal generating means for generating a signal of a predetermined period according to the tempo, timing data indicating the sounding timing of each rhythm sound, and a rhythm to be generated at the timing. First including performance data composed of musical sound data indicating a sound
A pattern memory in which at least two types of rhythm patterns, that is, a pattern and a second pattern, are stored, timing management means for managing the current rhythm performance timing based on a signal of a predetermined cycle, and one of the first pattern and the second pattern. First detecting means for detecting the performance data corresponding to the current rhythm performance timing indicated by the timing management means from among the rhythm patterns of the first address, the first address indicating a current read address in the rhythm pattern. The rhythm performance timing designated by the timing management means is selected from among the rhythm patterns of the other of the first pattern and the second pattern, which has a designating means and updates the read address when the detection is made. Second detection for detecting the corresponding performance data Which has a second addressing means for indicating the current read address in the rhythm pattern and updates the read address when the detection is made, and which one of the first pattern and the second pattern Means for selectively designating whether or not to be output at an arbitrary timing of the rhythm performance, and the musical tone data of the rhythm pattern designated by the selection designating means for the first or second
And a rhythm sound source for forming a rhythm sound according to the rhythm pattern output by the reading means.

This makes it possible to effectively switch patterns even for event-based pattern data. That is, in the event-based pattern, for example, if the pattern of the rhythm sound to be currently pronounced is detected from the second pattern at the time when the switching from the first pattern to the second pattern is instructed, the pronunciation is delayed. Will end up. According to the present invention, even when the first and second detecting means detect one pattern and it is used for actual sounding, the other detecting means similarly detects the other pattern, that is, it is empty. I am sending. Therefore, it is possible to react immediately when the pattern switching is instructed.

The above-mentioned "detection" refers to a process in the event method in which it is checked whether the sounding timing of each rhythm sound included in the rhythm pattern matches the current timing, and the event data that matches this is searched.

Embodiments of the present invention will be described below with reference to the drawings.

(Description of Overall Configuration of Embodiment) FIG. 1 shows the configuration of an electronic musical instrument to which the autorhythm playing device of the present invention is applied. In the figure, the keyboard 1 is provided with an upper keyboard (UK), a lower keyboard (LK), a pedal keyboard (PK), etc., which are not shown, and generates key information in accordance with a key depression operation by a performer. The panel 10 is provided with musical tone selection operators 15 and rhythm section operators, and generates operator information such as musical tone selection and rhythm type selection. The control unit 30 scans the keyboard 1 and the panel 10 and takes in the generated key information and operator information, and based on these information, various data relating to the keyboard sounds and rhythm sounds is supplied to the key tone interface, rhythm interface, etc. It is sent via the interface of. The keyboard sound generation circuit 65 inputs keyboard sound data from the control unit 30 to form keyboard sound data with a plurality of (for example, 10) time-division channels, and these data are time-division multiplexed keyboard sound signals. To occur. The rhythm sound generation circuit 70 inputs data on the rhythm sound from the control unit 30 and generates percussion instrument sound signals for each of the eight time division channels, and these percussion instrument sound signals are time division multiplexed. Is output. The register 85 inputs the keyboard sound signal and the rhythm sound signal, and outputs the data of all the channels of the percussion sound signal and the keyboard sound signal generated from the central speaker among the rhythm sound signals and the rest of the rhythm sound signal, that is, the left speaker. After calculating the data for all channels of the percussion instrument sound signal respectively and mixing them acoustically,
Output to the central and left sound systems as separate parallel data. The parallel data for these central and left sound systems from register 85 are respectively D
A sound signal is converted and sounded via a central sound system 90 including an A / A converter 91, an amplifier 92 and a speaker 93 and a left sound system 95 including a D / A converter 96, an amplifier 97 and a speaker 98. It

(Detailed Description of Each Part) (1) Rhythm Operator 20 FIG. 2 shows the arrangement of each operator in the rhythm operator 20. In the figure, the break (fill-in) switch 21
Is for switching the normal pattern and the variation rhythm pattern (break pattern). Variation type selection switch 22 (22-1, 22-2, 22-3)
Is to select a break pattern generated in place of the normal pattern when the break switch 21 is pressed from among three types of variation patterns. As soon as the performer presses the break switch 21, the variation pattern selected by the switch 22 is switched to the break pattern, and when the break switch 21 is released, the original normal pattern is restored when the rhythm performance within the bar ends.

The intro switch 23 is a switch for switching the rhythm to the prelude for a predetermined number of measures after the start of the autorhythm, and is normally pressed while the rhythm is stopped before the start of the autorhythm.

The auto break switch 24 (24-1, 24-2, 24-3) automatically selects a bar cycle for inserting a break pattern. The types of this auto break are 4 bars (4 bar), 8 bars (8 bar) and 16 bars (16 ba).
r) is provided.

The rhythm selection switch 25 (25-1, 25-2, ...) Is for selecting a rhythm type such as march, waltz, ..., Swing.

The start / stop switch 26 is for starting or stopping the generation of autorhythm.

Balance setter 27 has drum volume and cymbals (noise)
It is for setting the volume ratio with the system volume.

The total volume 28 is for setting the volume of the rhythm sound (mixing ratio with the keyboard sound).

The tempo setter 29 is for setting the tempo of autorhythm.

These balance setter 27, total volume 28, and tempo setter 29 are multistage digital switches or variable resistors with voltage applied to both ends and A / D conversion for A / D converting the sliding terminal voltage of these variable resistors. A combination of a container and the like can be used.

(2) Control unit 30 In FIG. 1, the control unit 30 has a program counter (P
C), A register (A), X register (X), Y register (Y), etc., central processing unit (CPU) 31, program memory 32, working memory 33, rhythm pattern memory 34, pattern head address memory 35, A logarithmic volume memory 36, a bus line 37, a key switch interface 38, a panel interface 39, a key tone interface 40, a rhythm interface 41, and a panel data interface 42 are provided.

The program memory 32 is a read only memory (ROM)
The control program of the CPU 31 is stored.

The working memory 33 is a random access memory (RA
M) and a working area for temporarily storing various data generated when the CPU 31 executes the control program. This working area is composed of registers or flags as shown in Table 1. In the following description, each register and the like will be represented by the same label name. For example, both the beat count register and its contents are HKPE. Also, in Table 1, the tempo register TEMP
O, the total volume register TOTLEV, and the rhythm type register RHYPTN have rhythm operators 20 respectively.
The tempo setter 29, total volume 28, and operator information of the rhythm selection switch 25 are stored, and the drum set volume ratio register RHDLEV and the cymbal (noise) volume ratio register RHCLEV are operated from the balance setter 27. The child information is set, and the variation type selected by the variation type selection switch 22 is stored in the variation type register VARI. Further, 3, 7, and 15 are set in the automatic break register AUTOBRK in accordance with the selection of 4 bars, 8 bars, and 16 bars by the auto break switch 24, respectively.

Table pattern ROM start address register RHYROM1
Is composed of a total of 2 bytes of memory, each of which is 1 byte RHYROM1 and RHYROM1 ', and address designation for reading the rhythm pattern, replacement of contents with the back pattern ROM head address register RHYROM2, etc. are processed one byte at a time. The back pattern ROM top address register RHYROM2 (RHYROM2, RHYROM
2 ') and intro pattern ROM start address IN
TROM (INTROM, INTROM ') is also 2
The byte memory is processed one byte at a time.

The rhythm pattern memory 34 is composed of a ROM. As shown in FIG. 3 (a), one normal pattern, three variation patterns and one variation pattern for each rhythm type such as march, waltz, ... The intro pattern is stored. As shown in the enlarged view of FIG. 3 (b), each of these patterns has an instrument group number IGN at the start address, and then event data EVT and 16
The beat end data BE consisting of the data of “OD” (hereinafter referred to as “$ OD”) in the base notation, and the return data (bar end data in the case of one bar pattern) RTN ($ OF) at the end of the rhythm pattern. ) Is stored.
Here, the instrument group number IGN is equal to the number of sound source forming channels in the rhythm sound generation circuit 70 from 28 kinds of percussion instrument sounds such as cymbals and maracas for generating 13 kinds of rhythm sounds such as march and tango. A group formed by extracting eight types of percussion instrument sounds, and by assigning one percussion instrument sound constituting each of the instrument groups to the sound source forming channel, the electronic musical instrument of FIG. It is possible to generate an autorhythm consisting of up to eight types of percussion instrument sounds regardless of the type. Incidentally, in order to generate the same rhythm type and rhythm sound in the conventional auto rhythm playing device, 28 sound source forming channels are required, and if 8 sound source forming channels are used, one rhythm sound is generated. It is necessary to perform processing such as reducing the types of percussion instrument sounds.

The electronic musical instrument shown in FIG. 1 is configured to generate a rhythm at a timing of 1 beat, that is, 1/12 of 1 beat, and the event data EVT in the rhythm pattern memory 34 is also indicated by this beat. It is stored in the order of in-beat timing. As shown in FIG. 3 (c), this event data EVT uses 2 bytes of an 8-bit memory, and the low-order 4 bits (4th to 1st bit) of the 1st byte generate an intra-beat timing HTIMING, 7th
Sound source formation channel number CHNO in 5 bits, second
Pitch P of percussion instrument sound generated at the in-beat timing HTIMING in the upper 4 bits (8th to 5th bits) of the byte
ITCH, sustain data S / L in the 4th bit, and LEV on the musical note of the percussion instrument sound in the 3rd to 1st bits
EL, that is, data indicating whether the level of the percussion sound generated at that timing is ff to pp. The beat end data BE indicates the boundary between beats, and the return data RTN indicates the end of the rhythm pattern (the end of the measure when the rhythm is one measure pattern). The beat end data and the return data indicate that there is no event within the beat after the intra-beat timing indicated by the immediately preceding event data.

In the electronic musical instrument shown in FIG. 1, the normal pattern of the rhythm type selected by the rhythm selection switch (FIG. 2) 25 and the variation pattern selected by the variation type selection switch 22 are displayed in a table pattern in the working memory 33. Memory pointer RHPN
T1 and the back pattern memory pointer RHPNT2 search for events at the same timing at the same timing, and the front pattern memory pointer RHYPTN1 reads and outputs event data of the rhythm pattern on the searched side. Normally, the normal pattern is read out by the front pattern memory pointer RHPNT1 and is output as a front pattern, and the variation pattern is output as a back pattern, and a back pattern memory pointer RHYPTN2.
At the same timing, only the event search at the same timing is performed and the feed is performed in the air. After the break switch 21 is pressed, the front and back sides of the variation pattern and the normal pattern are switched until the measure in which the switch 21 is released is completed, and the variation pattern is sequentially read by the front pattern memory pointer RHYPTN1 and output as a break pattern. The normal pattern is fed by the back pattern memory pointer RHYPTN2.

In this embodiment, the table pattern memory pointer RH
The pattern indicated by YPTN1 is always sounded, the pattern indicated by the back pattern memory pointer RHYPTN2 is constantly fed, and when the pattern is switched, the contents of the front pattern memory pointer RHYPTN1 and the contents of the back pattern memory pointer RHYPTN2 are exchanged. However, the switching method is not limited to this. For example, the pattern memory pointer RHYPTN1 always indicates a normal pattern, and the pattern memory pointer RH
The correspondence between the pointer and the pattern is fixed such that YPTN2 always points to the variation pattern, and the pointers RHYPTN1 / RHYP are used when switching.
The correspondence relationship between TN2 and sounding / idle feed may be exchanged.

In FIG. 1, the pattern start address memory 35 stores the start addresses of the rhythm patterns of normal, first to third variations, and intro of each rhythm type stored in the rhythm pattern memory 34, and the contents of the rhythm type register. It is a conversion ROM that outputs these pattern start addresses in response to the input of RHYPTN. The start address read from this pattern start address is the start address of the normal pattern stored in the table pattern memory start address register RHYROM1 of 2 bytes in the working memory 33, and the variation type selection switch 22 of the three types of variation patterns. The start address of the variation pattern selected by is stored in the back pattern memory start address register RHYROM2,
The start address of the intro pattern is stored in the intro pattern memory start address register INTROM, respectively.

The logarithmic volume memory 36 has a total volume TOTLEV.
And drum system volume ratio RHDLEV and noise system volume ratio R
It is a conversion ROM that performs logarithmic conversion with HCLEV. These respective sound volumes and sound volume ratios are logarithmically converted and then calculated to obtain 8-bit noise sound volume NLEV and drum sound volume D.
The LEV is sent to the rhythm sound generation circuit 70 via the panel data interface 42. Here, the noise volume NLEV is obtained as a product of the total volume TOTLEV and the noise volume ratio RHCLEV, but as a result of logarithmic conversion in the logarithmic volume memory 36, the sum of these logarithmic values is easily and quickly calculated. be able to.

The bus line 37 includes a data bus (DB) and an address bus (ADB), and connects the CPU 31 to the memories 32 to 36 and the interfaces 38 to 42. The CPU 31, the memories 32 to 36, and the interfaces 38 to 42 exchange data via the bus line 37.

The rhythm interface 41 temporarily stores the rhythm sound source data output from the CPU 31, and stores the data stored in response to a command from the CPU 31 as serial data OPCIDA.
Converted to T and transferred to the rhythm sound generation circuit 70, CPU
When a rhythm start signal from 31 is input and thereafter every beat, an interrupt signal RINTRPT for causing the CPU 31 to perform data transfer processing by interruption is generated.

FIG. 4 shows a detailed block diagram of the rhythm interface 41. In the figure, the decoder 43 includes a CPU 31 (first
The address signal sent to the address bus ADB is
When any of the tempo register 44, the rhythm sound source data register 45, the channel register 46 and the function register 47, load signals RHYDEC1 to 4 are sent to the registers 44 to 47 according to the address signal.
Therefore, the data sent by the CPU 31 via the data bus DB is stored in the register designated by the address by the CPU 31.

The tempo register 44 has a tempo data register TEMPO.
New tempo data TEMP whenever the contents of
O is stored, and the tempo ROM 48 converts the tempo data TEMPO output from the tempo register 44 into preset data PSD of the counter 49. Counter 49 is load terminal L
The output of the D i.e. OR circuit 50 is preset data PSD is preset at "1", followed by counting the clock signal φ of the constant frequency output of the clock generation circuit 51, the output terminal C ₀ when overflow "1 Is output. This output is input to one input terminal of the OR circuit 50, and the counter 49 is preset each time it overflows. That is, when the overflow value is N and the preset value is M, the counter 49 divides the frequency of the clock signal φ into 1 / (N−M) and sets the tempo set to the tempo setter 29 (FIG. 2). Generate output. It should be noted that the counter 49 is preset to clock signal φ
May be down-counted to output "1" to the output terminal C ₀ with a count value of 0 to divide the clock signal φ into 1 / M, or another well-known variable frequency division type counter. The other input terminal of the OR circuit 50 is connected to the start output terminal of the function register 47, and the function register 47 causes the start signal START described later.
The counter 49 is also preset when is generated. The output of the OR circuit is further sent to the CPU 31 as an interrupt signal RINTRPT, and the CPU 31 starts the interrupt processing operation described later at the same time as the counter 49 is preset. Since the output of the clock generation circuit 51 is input to one input terminal of the OR circuit 52 and the output of the OR circuit 52 is connected to the reset terminal of the clock generation circuit 51, the clock generation circuit 51 immediately generates an output. It is reset and thus produces a short pulse width clock signal φ. Also, this O
The start signal STA is applied to the other input terminal of the R circuit 52.
Since RT is input, the counter 49 is preset and the clock generation circuit 51 is reset when the start signal is generated.

The event data EVT read from the rhythm pattern memory 34 by the CPU 31 (FIG. 1) is a 3-bit level LEVEL, a 1-bit sustain S / L and a 4-bit level.
The bit pitch PITCH is stored in the rhythm sound source data register 45 as 8-bit data, and the channel number CHNO is temporarily stored in the channel register 46.
The channel counter 53 repeatedly counts the channel timing signal Ch T obtained by dividing the clock signal φ from 0 to 7, and the comparator 54 uses this channel counter.
53 output is compared with the channel number CHNO output from the channel register 46, and when they match, A
The channel matching signal CHEQ is transmitted via the ND circuit 55. The flip-flop 56 is set by the load signal RHYDEC3 of the channel register 46 and reset by the channel match signal CHEQ. The channel match signal CHEQ is a logical product of the output of the comparator 54 and the set output Q of the flip-flop 56. By outputting, the channel match signal CHEQ as the differential waveform of the leading edge of the channel timing signal Ch T is output only once after loading the channel number CHNO. This channel match signal CHEQ is the selector 57
Input to the SB terminal of this channel match signal CHE
Only when Q occurs, the 8-stage 8-bit shift register 58 is loaded with the data such as the level LEVEL stored in the rhythm sound source data register 45. Further, the channel match signal CHEQ is stored as a key-on signal KON in the 8-stage 1-bit shift register 59, and the inverted signal “0” of the channel match signal CHEQ is input to the 8-stage 1-bit shift register 60. Clear the contents of. These shift registers 5
Since all of 8, 59, 60 and the channel counter 53 are operated by the same channel timing signal Ch T, the data stored in the rhythm sound source data register 45 is synchronized with the channel timing of the shift registers 58-60. Channel number CH in register 46
The channel corresponding to NO is loaded.

The function register 47 takes in the data sent from the CPU 31 via the data bus DB when the output RHYDEC4 of the decoder 43 is "1" by the address designation of the CPU 31. When this data value is $ 01, the start output START is automatically cleared after the pulse start signal START of a short time is transmitted. When the data value is $ 04 or $ 20, all the data for 8 channels is output as serial output time buffer clear signal BUFCLR (when $ 04) or transfer signal T
Outputs RANS (when $ 20) and automatically clears the rest. When the data value is $ 08 and $ 10, the break set signal and break reset signal are output, respectively. The break set / reset signal may be set, for example, when the break output BREAK "1" is transferred and reset when "0" is transferred.

The P / S converter 61 has its parallel data input terminals P1 to P1.
In P11, the rhythm data stored in the shift registers 58, 59, 60 for each of the eight channels is sequentially input for each channel in synchronization with the channel timing signal ChT, and the load terminal LD receives the channel timing signal Ch. T is typing. And the function register
When 47 generates the transfer signal TRANS, this P
The / S converter 61 takes in the data of P1 to 11 one by one in the section where the channel timing signal ChT is "1", and takes the taken-in data as the clock signal φ in the section where the channel timing signal ChT is "0". It is converted to serial data OPCIDAT and sent to the rhythm sound generation circuit 70.

In FIG. 1, the panel data interface 42 is
CPU31 is total volume 28 and balance setter 27
Total volume TOTLEV, drum volume volume ratio RHDLEV, and noise volume volume ratio RHC read from
The LEV is logarithmically converted by the logarithmic volume memory 36, and each 8-bit noise volume NLEV and drum volume DLEV obtained by calculation are converted into 16-bit serial data LVIN.
Converted to T and sent to the rhythm sound generation circuit 70,
When the intro pattern is generated, the instrument group number IGN read from the rhythm pattern memory 34 by the intro pattern ROM top address register INTROM is used. When the intro is not in progress, each pattern memory top address register RHYROM1 and R
Each instrument number IGN for front and back pattern generation read from the rhythm pattern memory 34 by the HYROM2 is converted into serial data PANCDD and sent to the rhythm sound generation circuit 70.

(3) Rhythm sound generation circuit 70 FIG. 5 is a detailed block diagram of the rhythm sound generation circuit 70.
The rhythm sound generating circuit 70 includes an S / P converter 71 and a selector 7
2, 8-stage 8-bit shift register 73, S / P conversion latch circuit 74, channel counter 75, musical instrument number balance channel ROM 76, rhythm sound signal generation circuit 77,
The envelope generator 78, the S / P conversion circuit 79, the volume selector 80, the level control circuit 81, the speaker selector 82 and the P / S conversion circuit 83 are provided, and the rhythm interface 41 and the panel data interface of the control unit 30 (FIG. 1) are provided. The rhythm data OPCIDAT, LVINT, and PANCDD transmitted from 42 are input, and percussion instrument sound signals are generated in each of the eight time division channels. The percussion instrument sounds are time-division multiplexed for each sound generation channel to register 85. Send to.

The entire rhythm sound generation circuit 70 is driven by the clock signal φ _AB , and eight rhythm sound source forming channels are formed in time division for each time slot which is sequentially divided for each cycle of the clock signal φ _AB . One of eight types of percussion instruments forming an instrument group is assigned to each of the eight channels.

The S / P converter 71 includes a rhythm interface 41 (first
The serial data OPCIDAT transferred from the figure) is converted into parallel data, the parallel data for 8 channels is temporarily stored in the built-in buffer memory, and it is synchronized with the channel counter 75 and is output to the output terminals P11 to 1 for each channel. Output.

The selector 72 normally outputs the signal input to the input terminal A because the select terminal SB is "0". Therefore, the shift register 73 sequentially shifts the input signal for each clock signal φ _AB and memorizes it while circulating it. The shift register 73 has output terminals P11 to P4 of the S / P converter 71 when the key-on signal KON is generated at the output terminal P2 of the S / P converter 71 and the select terminal SB of the selector 72 is "1".
Rhythm sound source data generated at is input. in this case,
In order to match the channel with the rhythm interface 41 (FIG. 1) on the sending side, for example, the transfer signal of the function register 47 (FIG. 4) is generated in synchronization with the channel 0 of the channel counter 53, and the channel is inevitable. The data from 0 to channel 7 are transferred in sequence, and the rhythm generating circuit 70 on the receiving side transfers S / P data.
The channel counter 75 outputs the output of the converter 71 in order from the channel number 0 output by the channel counter 75.
Or the system clock signal φ _AB is output.

The S / P conversion latch circuit 74 is an instrument group number IGN for generating front, back and intro patterns, which is transferred from the panel data interface 42 (FIG. 1).
Is converted into parallel data and the parallel data is latched until the next serial data PANCDD is input. Further, the S / P conversion latch circuit 74 is used in the rhythm interface 41.
A break flag BRKF set and reset by a break set / reset signal BREAK input from the output terminal P3 of the S / P converter 71 from FIG.
Instrument group number IG of the variation pattern having the selected G and having the break set signal input and the break flag BRKFG set.
When N is output and the break reset signal is input and the break flag BRKFG is reset, the normal group instruction group number IGN is output.
Since only one instrument group number IGN is input during the introduction, this is output.

The channel counter 75 counts the system clock signal φ _AB and outputs a channel number CHNO of 0 to 7.

When the instrument group number IGN and the channel count value are input, the instrument number balance channel ROM 76 inputs a 5-bit instrument number IN.
O, that is, the instrument name, a 1-bit sound source group signal BAL indicating whether this instrument is a cymbal (noise) type or a drum type, and 1 bit indicating whether the speaker that emits this instrument sound is the center or the left Is a conversion ROM for generating the tone generation control signal CHA.

The rhythm sound signal generating circuit 77 generates a percussion instrument sound waveform based on the 5-bit instruction number INO output from the instrument number balance channel ROM 76 and the 4-bit pitch data PITCH output from the shift register 73. As the rhythm sound signal generation circuit 77, a well-known waveform memory type or arithmetic type can be used. Instrument number I for waveform memory method
The start and end addresses of the memory are designated by NO and pitch data PITCH. In the case of the calculation method, the pitch data and the constants for determining the timbre are set by the instrument nanda INO, and the pitch data PITCH is set.
Is used for slight correction of pitch.

The envelope generator 78 is determined by the instrument number INO output from the instrument number balance channel ROM76 and the sustaining signal S / L from the shift register 73 using the key-on signal KON generated at the output terminal P2 of the S / P converter 71 as an attack. Waveform envelope data EG is generated. When the buffer clear signal BUFCLR is generated at the output terminal P1 of the S / P converter 71, the envelope data EG of all eight channels are immediately set to 0 to dump the rhythm sound.

The S / P conversion circuit 79 outputs the noise volume NLEV and the drum volume DL output from the panel data interface 42.
The serial data LVINT composed of EV is converted into parallel data and temporarily stored.

Volume selector 80 is instrument number balance channel ROM
Noise system volume NL according to the sound source group signal BAL generated by 76
Either EV or drum volume DLEV is selected and sent to the level control circuit 81.

The level control circuit 81 is composed of, for example, a multiplier, and includes sound source waveform data from the rhythm sound signal generation circuit 77, noise volume NLEV or drum volume DLE from the volume selector 80.
V, the level data LEVEL from the shift register 73 and the envelope data EG from the envelope generator 78 are calculated for each channel to generate a time division multiplexed percussion sound signal.

The speaker selector 82 is a musical instrument number balance channel R
Based on the tone generation control signal CHA generated by the OM 76, the percussion instrument sound signals generated by the level control circuit 81 are distributed to the center and left speakers, respectively.

The P / S conversion circuit 83 converts the percussion instrument sound signals for the center and left speakers into serial data and sends it out.

(Explanation of Operation of Electronic Musical Instrument of FIG. 1) Next, referring to the flowcharts of FIGS.
The operation of the electronic musical instrument shown in the figure will be described particularly for the control unit 30.
Referring to FIG. 6, when the electronic musical instrument is powered on, CPU 31 starts operation according to the control program stored in program memory 32 (step 100). In step 101, the registers, flags, etc. of the CPU 31, working memory 33, rhythm interface 41, etc. are cleared to initialize the entire circuit, and in step 102, the operators of the keyboard 1 and panel 10 are scanned to change the operation. Detect child and its manipulator information. This detection is performed by, for example, operator information for each operator and each register TE.
MPO, TOTTLEV, RHDLEV, RHCLEV,
When the exclusive OR with the previous manipulator information stored in RHYPTN, VARI, etc. is not 0, it can be detected that the manipulator information has been changed, that is, there is an event. In step 102, the operator information is detected even when the rhythm start / stop switch 24 is pressed toward the start or stop side. As the operator information, for example, the set values by the total volume 28 and the balance setter 27 are represented by digital data 0 to 15, respectively, and this data is stored in the total volume register TOTLEV, the drum system volume ratio register RHDLEV, and the noise system volume ratio register RHCLEV. To do.

Further, the break change flag BCHNGF is set in accordance with the operation of the break switch.

In step 103, it is determined whether or not an event is detected in step 102. If there is no event, the process returns to step 102 to detect another event. If there is an event, depending on the type of event detected in the subsequent steps. Perform processing.

If the event detected in step 102 is a tone change by pressing or releasing a key or pressing the tone selection operator 15, the process proceeds to step 110. In step 110, each key data or tone selection data is processed to create data relating to the key tone and output to the key tone interface 40. The keyboard sound interface 40 further sends these data to the keyboard sound forming circuit 65.

If the event is a start command from the start / stop switch 26, in step 120 the working memory
After setting the rhythm run flag RHYRUN in 33 to $ 80 (only the most significant bit is 1), the rhythm tempo is synchronized in step 121. This is to load the data $ 01 into the function register 47 (Fig. 4) of the rhythm interface 41 and start the start signal ST to the function register 47.
Generate an ART and use this start signal to counter
49 and tempo clock generator 51 by resetting. Further, the generation of the start signal START causes the rhythm interface 41 to interrupt the CPU 31, and the CPU 31 causes the rhythm sound generation circuit 70 to perform the rhythm sound generation circuit 70 through the rhythm interface 41 and the panel data interface 42 by the interrupt processing RHIRQ after step 200 described later. Sound serial data OPCI
Send DAT.

If the event in step 102 is a rhythm stop by the start / stop switch 26,
At 130, data $ 04 is loaded into the function register 47 of the rhythm interface 41 and the buffer clear signal B
After UFCLR is generated and all stages (8 channels) of the shift register 60 (Fig. 4) are set to "1", a data transfer command is further output in step 131 to output the rhythm data OPCIDAT including this buffer clear. It is sent from the interface 41 to the rhythm sound generation circuit 70.
In the rhythm sound generation circuit 70, this buffer clear signal BUF
The CLR clears the envelope generator 78 and dumps the rhythm sound. Further in step 132 the first
The rhythm-related registers and flags such as the pattern change flag PCHNGF and the rhythm run flag RHYRUN shown in the table are cleared.

If the event in step 102 is a tempo change by the tempo setter 29, the tempo data TEMPO is loaded into the tempo register 44 (FIG. 4) of the rhythm interface 41 in step 140. The tempo data stored in the tempo register 44 determines the pitch of one beat, that is, the tempo at which the rhythm pattern is read.

When the event in step 102 is a change in the rhythm volume by the total volume 28, the panel level data TOTLEV is output to the panel data interface 41 in step 150. Panel data interface 41
Converts the panel level data TOTLEV into serial rhythm level data LVINT and outputs it to the rhythm sound generation circuit 70.

The event in step 102 is the rhythm selection switch 23.
When the rhythm type RHYPTN is changed by pressing the button, the rhythm set processing RHYSET of step 160 and subsequent steps shown in FIG. 7 is executed. That is, the rhythm run flag RHYRUN is checked in step 161 and if the rhythm is in progress, the pattern change flag PCHNG is detected in step 162.
After setting F, if the rhythm is not progressing in step 161, skip step 162 and skip step 1
Proceed to 63. Pattern change flag PC in step 162
The HNGF is set because the previous rhythm sound is forcing-dumped when the rhythm type changes in the middle of the rhythm. At the next interrupt processing (see step 213), if the pattern change flag PCHNGF is set, the buffer is cleared. This is because the signal BUFCLR is sent to the rhythm sound forming circuit 70. In step 163, the timing counter TI
Referring to the contents of MING, set the number of beats in the number of beats register to 1 if the timing TIMING is 0 to 11, and to 2 if it is 12 to 23,
Set to 3 for 24-35, and set to 4 for 36-47. This is because the changed rhythm is continued at the same timing as before the change, and when the pattern pointer PHPNT1,2 is set to the address where the rhythm pattern data of the same number of beats and the same beat timing is stored in step 167. To use. In step 164, the rhythm run flag RHYRUN is checked again, and if the rhythm is in progress, the beat end flag RHHEND1,2 is cleared in step 165. This is because if the beat end flags RHHEND1,2 remain set, when the changed rhythm has event data after the timing of the change, the reading of these event data is skipped ( See step 401).
Even in the changed rhythm, if no event data exists after the changed timing, the rhythm pointer RHP
Beat end flag RHHEND when setting NT1,2
Set 1,2. If the determination in step 164 indicates that the rhythm is stopped, the beat end flag RHHEND1,2 has already been cleared in step 132 during the rhythm stop processing, so step 165 is skipped and step 166 is proceeded to.

At step 166, the contents of the rhythm type register RHYP
The head address of the normal pattern, variation pattern and intro pattern of the selected rhythm type is read out by addressing the head pattern address memory 35 with TN, and these head addresses are read to the front, back and intro pattern head address register RHYROM1 respectively.
, RHYROM2 and INTROM. At step 167, the rhythm pattern memory 34 is loaded with the leading addresses RHYROM1 and RHYRO of the front and back patterns.
Sequentially read from M2, the number of read beat ends, the timing within the beat, the beat number HKPE, and the timing TI
The table pattern pointer R is compared with MING.
Set HPNT1 and back pattern pointer RHPNT2. In step 168, the instrument group numbers IGN stored in the respective head addresses RHYROM1 and RHYROM2 of the rhythm pattern memory 34 are read out and output to the panel data interface 41.
The panel data interface 41 converts the instrument group number IGN for these front and back patterns into a serial signal PANCDD and sends it to the rhythm sound generation circuit 70.

In step 169, it is determined whether the rhythm type RHYPTN is 3 beats or 4 beats. If it is 4 beats, in step 170. If it is 3 beats, in step 171 the maximum tempo number register TMPMAX is set to the maximum timing within one bar, respectively. Remember the numbers 35 and 47.

When the event in step 102 is the depression of the intro switch 23, the intro process INTRO180 of FIG.
To execute. That is, in step 181, the rhythm run flag RHYRUN is checked to determine whether or not the rhythm is in progress. If the rhythm is in progress, pressing the intro switch 23 is meaningless. Therefore, the event of step 102 in FIG. Return to detection. If it is determined in step 181 that the rhythm is stopped, the start address of the rhythm pattern memory 34 is specified by the intro pattern start address INTROM, the intro instrument group number IGN stored therein is read, and the panel data interface 42 is set. It is sent to the rhythm sound generation circuit 70 via the.

After the event is detected in step 102, when the processing for each kind of event is completed, the process returns to step 102 to detect a new event.

As described above, in the electronic musical instrument shown in FIG.
When the stop switch 26 is started and when the counter 48 counts 1/12 of one beat, that is, one beat according to the set tempo, the rhythm interface
An interrupt signal RINTPT is sent from 41 to the CPU 31.
Therefore, the CPU 31 executes the interrupt processing INTRPT200 of FIG. 9 at the start of the rhythm and for each subsequent beat.

First, at step 201, each register, program counter, etc. are saved so that the state can be returned to the original state after completion of the interrupt processing, and then the rhythm sound generation data output processing RHIRQ210 shown in FIG. 10 is executed.

Referring to FIG. 10, in step 211, the rhythm run flag RHYRUN is checked to determine whether or not the rhythm is in progress. If RHYRUN = 0, that is, if the rhythm is stopped, it is not necessary to output the rhythm sound data.
Immediately release the interrupt at 290 (Fig. 9),
~ Return to the routine of FIG. If the rhythm is in progress in step 211, the intro flag INTON in step 212.
Is checked, and if the intro flag INTON is set, the intro pattern reading process from step 250 is executed. If the intro is not set, or if the intro pattern is finished and the intro flag INTON is reset even if it is set, the process proceeds to the next step 213. In step 213, the pattern change flag PCHNGF is inspected. If the pattern change flag is set, the data output is the first after the rhythm change or the change between the normal pattern and the variation pattern. Therefore, in step 214, the buffer clear signal BUFCLR is sent to the rhythm interface 41. Send out. This buffer clear signal is sent to the rhythm sound generation circuit 70 in step 225 described later.
The rhythm sound generating circuit 70 clears the envelope generator 78 to clear the previous rhythm sound. Next, at step 215, the pattern change flag PCHN
Clear GF and proceed to the next step 216. Step two
If there is no rhythm change in the judgment in step 13, skip steps 214 and 215 and proceed to step 216. In step 216, the bar up flag RDISPF is checked to determine whether or not the previous bar has ended in the previous interrupt process, that is, whether or not it is the head of the bar. If the bar up flag RDISP is $ FF, that is, the head of the bar, the exchange subroutine CHANG300 of FIG. 11 is executed.

Referring to FIG. 11, in step 301, the bar number counter SYOCNT is stepped up to count the number of bar ups, and in step 302, the break flag BRKON is checked and BRKON ≠ 0, that is, the previous bar is a break. If so, the process proceeds to step 320, and BRKON = 0, that is, if the previous bar is not a break, the process proceeds to step 303.

At step 303, the automatic break register AUTOBRK
Is checked to determine whether an auto break is set, and if an auto break is set, step 304
Then, it is determined whether or not the bar is a bar that is an integral multiple of the set auto-break type, that is, the break cycle (4, 8, 16 bar). This determination is made by the logical product of the lower 4 bits of the bar number counter SYOCNT and the lower 4 bits of the auto break register AUTOBRK. When this logical product is 0, it is judged that the present measure is an integral multiple measure of the break cycle, that is, a variation insertion measure, the break flag BRKON is set in step 311, and then step 312
Replace the contents of the front pattern memory pointer RHPNT1 and the contents of the back pattern memory pointer RHPNT2 with
At step 313, the contents of the front pattern memory start address register RHYROM1 and the contents of the back pattern memory start address register RHYROM2 are exchanged. By the processing of steps 312 and 313, the normal pattern was processed as the front pattern and the variation pattern as the back pattern in the previous measure, but in this measure, the variation pattern is replaced as the break pattern and the normal pattern is replaced as the front pattern and the normal pattern is processed as the back pattern. . Next, in step 314, the break flag BRKON is checked again. This time, in step 311, since the break flag BRKON is set, the process proceeds to step 315, the data $ 08 is loaded into the function register 47 (Fig. 4), and the break is set. Generate a signal. This break set signal is sent along with other data to the rhythm sound generation circuit in step 225.
70 (FIG. 5), the break flag BRKFG of the P / S conversion latch circuit 74 is set, so that the P / S conversion latch circuit 74 sends the instruction group number IGN for generating the break pattern.

If BRKON ≠ 0, that is, the previous bar is a break in the judgment of step 302, the break switch 21 (FIG. 2) is inspected in step 320. If the break switch 21 is pressed, the bar continues to be broken pattern. Since the table pointer RHPNT1 and the instruction group number IGN have already been set to the break pattern side, the break change flag BCHNGF is reset in step 321, and the process returns to the original routine (FIG. 10). If break switch 21 (Fig. 2) was released in step 320,
After clearing the break change flag BCHNGF at 322 and resetting the break flag BRKON at step 323, the contents of the front pointer RHPNT1 and the contents of the back pointer RHPNT1 are exchanged at the above steps 312 and 313, and at the step 313 the pattern start address. After replacing the front and back and setting the front pattern etc. to the normal side,
In step 314, the break flag BRKON is checked again. In this case, the break flag BRKON is stepped.
Since it has been reset at 323, proceed to step 316, and break the function register 47 (Fig. 4) to change the instrument group number IGN in the rhythm sound generation circuit 70 (Fig. 5) to the normal pattern side. After loading the reset data $ 10, return to the original routine (Fig. 10).

If auto-break is not set in step 303 and if auto-break is set
If the measure is not the break pattern insertion measure at 304, the process returns to the original routine (Fig. 10) without exchanging patterns.

Referring to FIG. 10, after executing the exchange subroutine CHANG, or when it is not the beginning of the bar in step 216, the break change flag BCHN is found in step 220.
Examine GF. If BCHNGF ≠ 0, the break switch 21 was pressed, so after resetting the break change flag BCHNGF in step 221,
CH diverted from a part of the exchange subroutine CHANG
The ANG1 routine 310 replaces the table pattern with the break pattern, and then, in step 223, the table beat end flag RH.
The contents of HEND1 and the contents of the back beat end flag RHHEND2 are exchanged. The change of the table pattern from the break pattern to the normal pattern and the exchange of the front and back patterns in the automatic break are inevitably caused at the time of the bar switching, so the beat end flags RHHEND1 and 2 are inevitably reset, so it is not necessary to exchange them. However, since the change from the normal pattern to the break pattern by fill-in can occur at any time,
223 processes are required.

After executing the CHANG1 subroutine described above, and at step 220, the break change flag BCHN.
If GF is 0, then the data output subroutine RH
Execute YCNV400 (Fig. 12).

Referring to FIG. 12, in step 401, the table beat end flag RHHEND1 is checked, and if it is the end of the beat, the event data of the table pattern does not exist in the in-beat timing TMPCNT until the beat is over. Return to (FIG. 10). If it is not the beat end, the contents of the rhythm pointer RHYPNT1 are set in the Y register in step 402, and then in steps 403 and 404, the rhythm is obtained by adding the contents of the table pattern memory start address RHYROM1 Y register (that is, the contents of the table pointer RHPNT1). Addressing the pattern memory 34, FIG.
) First-channel data CHNO and intra-beat timing data HTIMING are read out and stored in the A register and the X register. Next, in step 405, A
The logical product of the contents of the register and $ OF is calculated and the contents of the A register are set to the lower 4-bit intra-beat timing data HTIMI.
Only NG is left, and in step 406, the timing HT within this beat
It is determined whether or not the timings indicated by IMIN and tempo counter TMPCNT match. If these timings match in step 406, this data is valid at the timing TMPCNT to be processed now, so the content of the Y register as a pointer is incremented in step 407, and in step 408, FIG. c) Pitch of second byte of event data and level LE
The VEL data is read and stored in the A register. In step 409, the pitch and level data stored in the A register are stored in the rhythm sound source data register 45 (FIG. 4).
In addition, the channel number C stored in the X register
The HNO is output to the channel register 46 (Fig. 4).

In step 410, the contents of the Y register as the table pointer are further stepped to read the next event data EVT. Steps 403 to 4 in steps 411 to 414
The procedure of 06 is repeated, and in steps 407 to 414, all the event data having the same in-beat timing as the current timing TMPCNT is read. If there is no event data having the same beat timing in step 406 or 414, the process proceeds to step 415, and the timing data left in the A register in step 405 or 413 is $ 0.
It is determined whether or not it is D or more, that is, whether it is a beat end or a return. Since the timing within the beat is always $ 0 to $ B,
The content A of the A register becomes $ 0D or more when the beat end data BE or the return data RTN is read. Therefore, if A register ≥ $ OD in the above determination, it is then determined in step 416 whether A register = $ 0F, that is, return, and if A register = $ 0F, that is, return, the Y register is cleared in step 417. If the beat ends, skip step 417 and skip step 418.
Proceed to. In step 418, the front beat end flag RHHEN
D1 is set, the content of the Y register is incremented in step 419, the content Y of the Y register is set in the table pointer RHPNT1 in step 420, and the process returns to the original routine (step 225 in FIG. 10). Steps 417, 419 and 4 above
When the return data RTN is detected by the processing of 20, the table pointer RHPNT1 is set to 1, and when the beat end data BE is detected, the table pointer RHPNT is set.
1 indicates the address next to the address in which the beat end data BE is stored in step 419. If the in-beat timing TMPCNT is smaller than $ 0D and is not the end or return of the beat in the determination of step 415, step 4
Proceed to 20 and set the timing TMP to the table pointer PHPNT1.
The address at the time of reading out the in-beat timing that does not match CNT is stored as it is, and then the process returns to step 225 of the routine of FIG.

Referring to FIG. 10, in step 225, a data transfer command is sent to the rhythm interface 41. This is the function register 47 (Fig. 4) specified by address
Do this by loading 20. Then, the function register 47 outputs the transfer signal TRANS, this signal is applied to the P / S converter 61, is output to the rhythm interface 41 in step 409, and is transferred to the shift register 58.
The pitch PITCH stored for each channel in
Sustain S / L and level LEVEL, key-on data KON stored in shift register 59, buffer clear signal BUF stored in shift register 60
Break set / reset signals output from the CLR and the function register 47 are output by the P / S converter 61.
It is converted into bit serial data OPCIDAT and sent to the rhythm sound generating circuit 70 (FIG. 5).

Subsequent to step 225, the back pattern advance subroutine RHY
The process of PUP500 (Fig. 13) is executed. Referring to FIG. 13, in step 501, the back beat end flag RHHEN
If D2 is inspected and the end of the beat is detected, there is no back pattern event data in the timing TMPCNT until the end of the beat.
Return to Figure). If it is not the beat end, the content of the rhythm pointer RHYPNT2 is set in the Y register in step 502, and then in steps 503 and 504, the back pattern start address RHYROM2 and the content Y of the Y register (that is, the content of the back pointer RHYROM2) are added. The rhythm pattern memory 34 is addressed and the first byte of channel data CHNO and in-beat timing data HTIMING of FIG. 3 (c) are read out and stored in the A register and the X register. Next, in step 505, the logical product of the contents of the A register and $ OF is obtained, and the contents of the A register are left only for the in-beat timing data of the lower 4 bits. In step 506, this in-beat timing and the timing indicated by the tempo counter TMPCNT are It is determined whether they match. Step
If these timings match at 506, there is data to be read at the current timing TMPCNT, so at step 507 2 is added to the contents of the Y register as a pointer. In steps 508 to 511, the procedure of steps 503 to 506 is repeated, and all the event data having the same in-beat timing as the current timing TMPCNT are idle-fed. If there is no event data having the same in-beat timing as at present in step 506 or 511, the process proceeds to step 512. Step 5
In steps 12 to 517, as in steps 415 to 420 (FIG. 12), the timing data left in the A register in steps 505 or 510 is used to determine the in-beat timing at which the next event occurs, and the back pointer RHHEND is set.
After setting 2 to the address from which the next event can be read, the process returns to the original routine (step 230 in FIG. 10).

Referring to FIG. 10, in steps 230 and 231, the beat measure up flag is reset, in step 232, the tempo counter TMPCNT is incremented, and in step 233, it is determined from the contents TMPCNT of the tempo counter whether the beat is over. Since there are 12 timings within one beat, 0 to 11, there are overbeats when the timing TMPCNT indicated by the tempo counter overflows. Step two
If it is determined at 33 that the beat is over, then at step 234, the timing counter TIMING is incremented. Since it is always a beat over when the measure is over, and the beat over may be also a measure over, so next step 235
Then, in step 233, the beat over is determined by whether or not the bar over is determined by whether or not the content TIMING of the timing counter reaches the maximum timing number TMPMAX. If the measure is over, in step 236 the front and back beat end flags R
HHEND 1 and 2 are reset, and at step 237, timing counter TIMING and tempo counter T
After resetting MPCNT and further decrementing the beat / measure up flag RDISPF in step 238 to set the contents to $ FF indicating the measure up (cleared in step 231 before decrementing), as shown in FIG. Return to step 290. If the beat is over but the measure is not over, the front beat end flag RHHEND1 is reset in steps 240 and 241, the back beat end flag RHHEND2 is reset in steps 242 and 243, and the in-beat timing counter TMPCN is reset in step 244.
T is reset, and in step 245, the beat / measure up flag RDISPF is incremented to indicate beat up $ 01.
Then, the process returns to step 290 in FIG.

If the determination in step 233 is not overbeat, the timing counter TIMING is incremented in step 246, and then the process returns to step 290 in FIG.

If it is determined in step 212 that the intro is started or during the intro, in step 250 the contents of the table pattern memory start address register RHYROM1 and the contents of the intro pattern memory start address register INTROM are exchanged,
In step 251, the contents of the table pointer RHYPNT1 and the intro pointer INPNT are exchanged, and in step 252, the contents of the front beat end flag RHHEND1 and the contents of the intro beat end flag INHEND are exchanged,
After setting the start address, pointer and beat end flag of the intro pattern to the table pattern, the above-mentioned data output subroutine RHYCNV400 (FIG. 12) is executed to read the intro pattern data of the rhythm pattern memory 34 and the rhythm interface 41 (first Four
Output). Subsequently, in steps 255 to 257, the intro pattern is replaced with the back pattern and the normal pattern is replaced with the front pattern to restore the state before step 212, and then in step 258, the above-mentioned data output subroutine RH is executed.
The intro pattern data read by the YCNV400 is transferred to the rhythm sound generating circuit 70. Following steps 259 and
In 260, the beat / measure up flag RDISPF is reset, and in step 261, the intra-beat timing counter TMPCN is reset.
Increment T, and in step 262, in-beat timing counter T
It is determined from the contents of MPCNT whether the beat is over. If the beat is over, the timing counter TIMING is incremented in step 263, and the content TIMING of the timing counter is checked in step 264. If TIMING has reached the maximum timing number TMPMAX, it means that the bar is over, so in step 265, the intro beat end flag I
Check NHEND. INHEND = $ OF, that is, if the intro pattern is completed, the intro-on flag INTON is reset in step 266, and step 267
After reading out the instruction group numbers IGN for generating normal and break patterns at the front and back pattern start addresses RHYROM1 and 2, respectively, and sending them from the panel data interface 42 (FIG. 1) to the rhythm sound generating circuit 70 as serial data PANCDD, If INHEND ≠ $ OF in step 265 and the intro pattern is not completed yet, step 266
And 267 are skipped, the intro beat end flag INHEND is reset in step 268, and the routine jumps to step 268. In steps 237 and 238, as described above, the intra-measure timing counter TIMING and the intra-beat timing counter TMPCNT are cleared, and the beat / measure up flag RDISPPF is decremented to $ F.
After setting to F, return to step 290 (Fig. 9). If the beat is over at step 264 but not over the measure, the routine proceeds to step 270, where the intro beat end flag INHEND is cleared at steps 270 and 271 and the routine jumps to step 244. In step 244, the in-beat timing counter TMPCNT is reset, and in step 245
The beat / measure up flag RDISPF is incremented and set to $ 01, and the process returns to step 290 (FIG. 9). If it is not overbeat in step 262, step 2
Jump to 64 and start timing bar TIMIN
After stepping through G, return to step 290 (Fig. 9).

Referring to FIG. 9, rhythm sound generation data output processing RHI
Steps 211, 238, 245 and 2 of RQ (Fig. 10)
After returning from 46, in step 290, the program counter and each register, etc., which have been saved to execute the interrupt processing INTRPT, are restored, and the sixth interrupt before interrupt is executed.
~ Return to the process of FIG.

As described above, according to the present invention, the rhythm pattern includes data indicating the sounding timing of each rhythm sound, and if the sounding timing and the current timing are checked while checking whether or not they match, the pronunciation of the data of the autorhythm is generated. In an automatic rhythm playing device that uses so-called event-based pattern data, normal patterns and variation patterns that are break patterns are always translated as front and back patterns, respectively, and sound is generated at any timing by the player pressing the break switch. Since variations can be inserted immediately without delay, a more varied autorhythm can be generated.

[Brief description of drawings]

FIG. 1 is a block diagram of an electronic musical instrument according to an embodiment of the present invention, FIG. 2 is a layout diagram of respective operators in a rhythm section of a panel of the musical instrument of FIG. 1, and FIG. FIG. 4 is a block diagram of the data stored in the rhythm pattern memory of the musical instrument shown in FIG. 4, FIG. 4 is a detailed block diagram of the rhythm interface of the musical instrument shown in FIG. 1, and FIG. 5 is a detail of the rhythm sound generation circuit of the musical instrument shown in FIG. Block diagram, FIG. 6 is a flow chart for explaining the operation of the electronic musical instrument of FIG. 1, FIG. 7 is a flow chart showing a subroutine of rhythm set processing, FIG. 8 is a flow chart showing a subroutine of intro processing, FIG. 9 is a flowchart showing an interrupt process, FIGS. 10 (a) and (b) are a flowchart showing a subroutine of a rhythm sound generation data output process, and FIG. 11 is a normal blur. Flowchart illustrating a subroutine of click exchange, FIG. 12 is a flowchart showing a subroutine of the data output processing, Fig. 13 is a flowchart showing a subroutine of the back pattern development processing. 21 ... Break switch, 23 ... Auto break switch, 25 ... Rhythm selection switch, 31: CPU, 33 ... Working memory, 34 ... Rhythm pattern memory, 70 ... Rhythm sound generation circuit.

Claims (1)

[Claims] 1. The sounding timing data of a rhythm pattern formed by combining a plurality of performance data composed of timing data indicating the sounding timing of each rhythm sound and musical sound data indicating the rhythm sound to be generated at the timing and the current sounding timing data. In the event type auto rhythm playing device that checks whether the playing timings match and if they match, a periodic signal generating means for generating a signal of a predetermined period according to the tempo At least two types of rhythm patterns are stored for each rhythm sound, including timing data indicating the sounding timing and performance data composed of musical sound data indicating the rhythm sound to be generated at the timing. Pattern memory and the current signal based on a predetermined cycle Timing management means for managing the rhythm performance timing, and first performance data for detecting the performance data corresponding to the current rhythm performance timing indicated by the timing management means from one of the first and second rhythm patterns. And a first address designating means for indicating a current read address in the rhythm pattern, the read address being updated when the detection is made, and the first pattern and the second pattern. Second detecting means for detecting the performance data corresponding to the current rhythm performance timing indicated by the timing managing means from the other rhythm pattern of the second rhythm pattern, the second detecting means indicating a current read address in the rhythm pattern. When the detection is made, The unit for updating the read address, the unit for selectively designating which of the first pattern and the second pattern should be output at an arbitrary timing of the rhythm performance, and the tone data of the rhythm pattern designated by the selection designating unit. An automatic rhythm playing apparatus comprising: a reading unit that outputs based on a detection result of the first or second detecting unit; and a rhythm sound source that forms a rhythm sound according to a rhythm pattern output by the reading unit.