JPH0652501B2 - Data processing device - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a data processing device for interpreting and executing a tagged data instruction having a tag indicating a data type and an untagged data instruction.

[Background of the Invention]

A Neumann type general-purpose data processing device (hereinafter, referred to as a computer) has a macro instruction (hereinafter, referred to as an instruction) unique to the computer, and the instruction is an operation code that normally indicates the type of operation and an operand that is an operation target. Consists of an operand specifier that indicates the whereabouts of. The method of specifying the operand is called an addressing mode, and various methods have been proposed. A common feature of these computers is that the data type of data handled by an instruction is uniquely determined by an opcode. For example, even if data exists in the same operand, if it is a fixed-point instruction, it is treated as an integer, and if it is a character string instruction, it is treated as a character code. is there.

In contrast, the Proceeding of Logistics Programming Conference '84 (Proceeding of Log
ec Programming Cnoference '84) "Hardware development of personal sequential inference machine PSI" or International Symposium on Logic Programming '84 (International Symposium on Logic
Programming) "Towards a Pipelined Prolog Pro"
cessor ”), and moreover, S.R.I.International Artificial Intelligence Center Technical Report 1983 (Tech Report 3)
09, Artificial Intelligence Center, SRI Internati
onal 1983) "Abstract Prolog Instruc"
In the computer dedicated to prologue described in "tion set"), a specific bit of each data is assigned as a tag,
The tag has the data type information of the data. At the time of calculation, the type of calculation is changed while checking the tag and determining the data type. Such a tag architecture is an architecture that can efficiently execute a symbol processing language such as a Lisp or a prologue.

The above-mentioned two types of computer architectures are independent of each other and are not compatible with each other. However, in applications such as knowledge engineering, both the numerical processing that the former is good at and the non-numerical processing (symbol processing) that the latter is good at are required, and both, namely, untagged data instructions and tagged data instructions are required. A computer that can execute both is required.

In order to interpret and execute the untagged data instruction and the tagged data instruction in the same computer, there is a method in which both are set as instruction sets in different modes and each instruction set is provided with an instruction for shifting to another mode. It is conceivable, but the overhead cannot be ignored if the mode changes frequently.

Alternatively, the Proceeding of 11th International Symposium on Computer Architects (Proceeding of 11th International)
Symposium on Computer Architecture, june, 198
4) “Architecture of SOAR: Smalltalk on RISC”
As described in (a RISC), there is a method of providing a mode bit for distinguishing both instructions in an instruction and providing a mode for handling untagged data and a mode for handling tagged data for each instruction. This method is excellent in terms of easiness of implementation, but has a drawback that the instruction length is increased by 1 bit, and it is not necessary to change the operation depending on the presence / absence of a tag (for example, a data transfer instruction). For example, the data indicated by the operand specifier may be transferred regardless of the presence or absence of a tag.), The mode bit is wasted. These problems are serious drawbacks in commercialization. That is, the change in the instruction length impairs the compatibility of the instruction word with the conventional software resources, and the waste of the mode bit increases the object code capacity which should be as small as possible.

Further, in the above-mentioned known example, since the number of bits of the tag is limited to one bit, there are two data types that can be expressed,
It has a drawback that it is difficult to deal with prologues and Lisps that handle various data types. Further, since there is no instruction for handling floating data, it is difficult to apply it to an application system such as plant control.

The present invention has been made in view of the above problems.

[Object of the Invention]

An object of the present invention is to provide a general-purpose data processing device capable of executing an instruction for untagged data and an instruction for tagged data.

[Outline of Invention]

The tagless data instruction (so-called general-purpose instruction) is an instruction that has been used for a long time and in a wide range, and there are many instruction types from a simple transfer instruction to a floating instruction. On the other hand, the tagged data instructions have a small number of instruction types because the languages that use them, such as the lispe or prologue, are not widely used.

Therefore, by incorporating the instruction for tagged data into the instruction system for untagged data, both instructions are made into the instruction system of the same computer without changing the entire instruction system. That is, part of the opcode is assigned to the untagged data instruction, and part of the opcode is assigned to the tagged data instruction.

The data processing device is provided with a decoding means for interpreting the operation code to detect whether it is an instruction for untagged data or an instruction for tagged data, and according to the output of this decoding means, when the instruction for tagged data is used, the operand is Operate the operand specified by the specifier as tagged data and perform processing while evaluating the tag. In the case of an instruction for untagged data, the portion corresponding to the tag is also treated as data and the instruction is executed.

Example of Invention

FIG. 1 is a block diagram of the internal configuration of a data processing device showing an embodiment of the present invention, and a detailed description will be given later.

FIG. 2 shows registers that can be designated as operands by a macro instruction (hereinafter, simply referred to as an instruction) of a computer in the registers in the data processing device with a tag (hereinafter referred to as a computer) described in this embodiment. Shows. There are 33 registers each with a width of 32 bits, and the program counter (P
Other than C), they are so-called general-purpose registers. Although the number of registers is not essential to the present invention, it is assumed here that there are 32 general-purpose registers.

FIG. 3 shows the data format used in the computer, and the basic word length is 32 bits. (A) is untagged data, which is often used in ordinary computers.
In other words, the signed 16-bit addition instruction regards bit 0 to bit 0 as a signed integer, and the 32-bit floating addition instruction regards bit 31 to bit 0 as single-precision floating data for calculation (b). First
Data having a tag indicating the type of data and the data are embedded in one word. In the present invention, the bit length of the tag and the bit position of the tag are not essential problems, but in the present embodiment, it is assumed that k = 8 and the tag is on the MSB side. (C) is the second tagged data, in which the tag indicating the data type of the data body and the memory address (pointer) of the data body are stored in the first 32 bits (hereinafter referred to as a pointer word). There is. Then, the data exists on the memory designated by the pointer. In the present invention, the bit length of the tag is not an essential problem as described above, but in this embodiment, l = 4 will be described. Further, the data pointed by the pointer does not necessarily have to be 32 bits, and the present invention can be applied even if the data is 64 bits or more.

(D) is the third tagged data, and the pointer and the pointer to the first, second, or third tagged data are stored in the pointer word.

In the data of (b) to (d) above, what is specified as the operand of the instruction is the tagged data itself in (b), and in 4 bytes including the pointer in (c) and (d). is there. That is, untagged data can be addressed in byte units, but tagged data cannot be addressed in 4 byte (basic word length) units.

FIG. 4 shows a specific example of tagged data. nill, variable, atom, short-integer is an example of the first tagged data, long-integer big-number, double-
floating is an example of the second tagged data, referenc
e, structure, list, and undefine are examples of the third tagged data. As described above, since the tag bit length may be increased or decreased, it is easy to introduce a new data type. For example, when a frequently used integer is larger than 16 bits, if this is expressed by Long-integer, memory access will occur twice for each reference. So T
28 bits long middle-integer for AG "1000"
By adding, it is possible to refer to a relatively large integer with one memory access.

FIG. 5 shows the format of instructions that can be executed by the computer of this embodiment. The instruction is composed of an operation word 50 (abbreviation OPW) of 16 bits and an operand specifier 51 (abbreviation OPS) of 16 bits or more indicating the location of the operand to be operated.

The CPW 50 indicates whether the operation type and its name can handle tagged data. In this embodiment, O
An instruction in which the upper 9 bits of PW50 is "111111100" can handle tagged data, and the operation at that time is shown by the lower 7 bits of OPW50.

Here, the above bit allocation is performed in order to facilitate the configuration of the instruction decoder. However, if all OPWs are decoded, it is possible to allocate an arbitrary code to an instruction that handles tagged data.

In this embodiment, a 32-bit microprocessor MC68020 manufactured by Motorola, Inc. of the United States is used as an instruction for untagged data.
It has an upward compatible instruction with a floating instruction added to it, and a prologue instruction set as an instruction for tagged data. Here, the prologue instruction set is the technical report 309, 1983 (Tech.Repor 309, Artificial Int).
The above is compatible with a prologue instruction set (hereinafter abbreviated as WAM) described in "An Abstract Prolog Instruction Set" of the Elligence Center, SRI International 1983). Since the WAM is described in detail in the above-mentioned document, the parts necessary for understanding the present invention will be briefly described here. WAM is roughly divided into four categories, which are called put-type instructions, get-type instructions, unify-type instructions, and Control-type instructions, respectively. The program described in the prologue is converted into the above instruction by the compiler. The put type instruction is an instruction that loads an argument into the argument register, and the get type instruction is an instruction that performs pattern matching of another argument with the data in the argument register. The unify instruction is an instruction to perform pattern matching for each element when the argument has a structure (for example, list / structure).

Here, the unify instruction must completely change its operation depending on the execution result (read mode or write mode) of the preceding get instruction. This mode is reflected in the status flag RMB (described later) of the data processing device. O
The PS 51 is composed of a mode specifier EA52 indicating an addressing mode and a displacement disp53 used in address calculation.

FIG. 6 shows the details of the EA 52, and the operand address calculation procedure in each addressing mode will be described with reference to FIGS. 7 and 8.

The MOD 55 of "000", "001", "010" is an addressing mode called so-called register direct or register indirect, which is well known to those skilled in the art. When MOD55 is "011", it is an addressing mode called auto increment. When Sz54 is 0, 2 is added to the register indicated by REGNO56 as shown in FIG.
When 54 is 1, 4 is added to the register indicated by REGNO 56. When the MOD 55 is "100", it is an addressing mode called auto decrement, and as shown in FIG. 8 (e), the operation opposite to the auto increment is performed.

The mode in which the MOD 55 is "101" is an addressing mode called register-relative. As shown in FIG. 8 (f), when Sz 54 is 0, the DISP 53 is di-stated in FIG.
The format is sp type I, which is added to the register indicated by REGNO56. When Sz 54 is 1, di
The sp type II is added and the operand address on the memory is calculated.

When the MOD 55 is “111” and the REGNO 56 is “0000” is an addressing mode called absolute, and as shown in (g) of FIG. disp type I format,
This directly becomes the operand address on the memory.
When Sz 54 is 1, the disp type II is directly used as the operand address in the memory.

When the MOD55 is "111" and the REGNO56 is "0001" is an addressing mode called immediate, and as shown in (h) of FIG. Disp type I format,
This becomes the operand as it is. When Sz 54 is 1, the disp type II becomes the operand as it is.

The one in which MOD55 is "111" and REGNO56 is "0101" is an addressing mode called program counter relative, and the operand address similar to the register relative addressing mode as shown in (i) of FIG. Take the calculation procedure of.

MOD55 is "111" and REGNO56 is "0111"
Are called tagged immediate addressing modes. In the tagged immediate addressing mode, as shown in FIG. 8 (j), DISP53 is in the form of disp type III in FIG. 7, that is, a 4-bit tag and a 28-bit pointer, and the program counter The second operand format shown in FIG. 3 which has a pointer of the value obtained by adding this pointer to the value of becomes the operand.

In this embodiment, the bad registers used in the tagged immediate addressing mode are described only for the program counter, but the general-purpose registers described above or other registers not mentioned in this embodiment are also used. What is possible is clear.

FIG. 9 shows the overall configuration of a computer capable of executing both the tagged data instruction and the untagged data instruction described above. 100 is an instruction execution unit (abbreviated as BPU),
Interpret and execute the above instructions. A memory device (abbreviated as MM) 800 stores the above-mentioned command or data. Reference numeral 500 is a 32-bit wide memory address bus (abbreviation ADRBUS), and 600 is a 32-bit wide memory data bus (abbreviation DATBUS). Since the present invention is applied to the BPU 100, the inside of the BPU 100 will be described in detail below.

FIG. 1 is a block diagram showing the internal structure of the BPU100.

110 is an instruction buffer (IBR), and DATBUS600
The instruction fetched from the MM 800 is stored via the. 120 is an OPU 50, EA from the instruction in IBR110.
52, an aligner (ALM) that cuts out DISP 53,
The OPW 50 is output to the signal line 350, the EA 52 is output to the signal line 355, and the DISP 53 is output to the signal line 340.

Reference numeral 130 is an instruction decoder (INSDEC), which is a signal line 35.
5 and the information input from the signal line 350, an entry address for address calculation and an entry address for instruction execution are generated and output to the signal lines 360 and 460, respectively. 140 is a control circuit (A-CT) for address calculation.
L), which has a function of setting the signal line 370 to "1" in the tagged immediate addressing mode. A
In addition to the signal line 370, the CDL 140 includes a register file 160 (ARF) and an arithmetic unit 190 for address calculation.
Although a control signal such as (A-ALU) is also generated, it is omitted because it is not necessary for understanding the present invention.

Reference numeral 153 is a tag length detection circuit (TL) that determines the length of the tag included in the disp 53, and the signal line 159 becomes "1" when the tag is an 8-bit length tag.

Reference numeral 160 denotes a separation circuit (SEP) that separates the tag and the pointer from the displacement in the signal line 340.
When both the signal lines 370 and 159 are “1”, the tag is output to the signal line 380 and the pointer unit is output to the signal line 400. At other times, the data on the signal line 340 is output to the signal line 400 as it is.

170 is a program counter (PC). 180
Is a register file (ARF), and AR of FIG.
Corresponds to O to AR15. Reference numeral 190 is an arithmetic unit (A-ALU) used in address calculation.

Reference numeral 200 is a register (TAG) that holds the tag cut out by the SEP 160, and stores the tag of the operand in the tagged immediate addressing mode.

210 indicates the pointer and PC1 cut out in SEP160 in the tagged immediate addressing mode.
This is a register (IMR) in which a new pointer obtained by adding 70 is stored. Further, in the immediate addressing mode, immediate data is stored. According to the present embodiment, the operand in the tagged immediate addressing mode is TAG200.
And IMP200.

220 is a register file (ERF), which corresponds to ER0 to ER15 in FIG.

Reference numeral 230 denotes an arithmetic unit (E-ALU), which is a standard arithmetic unit.
In addition to the logical operation, when the signal line 465 is “1”, the length of the tag included in the data input from the signal line 430 is determined by the TL 152, and the signal is output according to the value of the signal line 158. It has a function of embedding in the data input from the tag signal line 445 from the line 430 to generate tagged data.

When the signal line 475 is "1", 240 indicates the tag length detection circuit T from the tagged data input from the ESAB440.
The tag is masked according to the determination result of L151, and the data for outputting the data portion to the signal line 445 is cut out by a circuit (MS
K).

Reference numeral 250 is a circuit (TAG-EXT) that cuts out only the tag determined by the TL 150 from the tagged data input from the ESBB 430, and outputs the tag to 251. The tag cut out by the TAG-EXT 250 has a tag register 260 when the signal line 455 is "0".
(TAGR), and when the signal line 455 is “1”, it is stored in the tag register 270 (TAGR).

Reference numeral 280 is a selector (SEL), which is connected to the signal line 470 in accordance with the TAGR 260, the ATGR 270, or the E-CTL.
ESBB by selecting one from the tags output from 290
Output to upper 8 bits of 430.

290 is a control circuit (E-CTL) for instruction execution,
The control signal is generated by the microprogram control method.

Reference numeral 300 is a status flag (RMB) indicating the state of the BPU 100, which indicates a read mode when "0".
When it is "1", it indicates the write mode.

A memory address register (MAR) 310 holds an address of a memory, and stores an operand address calculated by the address calculation. Further, in the tagged immediate addressing mode, the pointer of the pointer word is stored.

A memory write data register (MWR) 320 holds data to be written in the MM 800. 330 is
It is an operand buffer register (OBR) that holds the data read from the MM880.

A detailed description of each block necessary for understanding the present invention will be given below.

The INSDEC 130 has, for example, the configuration shown in FIG. 10 and has at least means 133 for detecting whether or not an instruction handles tagged data. The entry address generation circuit 131 outputs different entry addresses in the untagged data instruction and the tagged data instruction according to the output 134 of the tagged data instruction detection circuit 133.
Output to 0. Further, the A-CTL entry address generation circuit 132 generates an entry address for address calculation according to the EA 52 in the instruction, but when the signal line 134 is “0”, that is, the instruction for untagged data, the tagged imitation. The date addressing mode is an unusable addressing mode, and no entry address is generated.

The entry address generation circuits 131 and 132 can be easily configured by those skilled in the art by using a read only memory (ROM), a programmable logic array (PLA), or the like. In addition, the tagged data instruction detection circuit 133 is
In the case of this embodiment, it can be constituted by a circuit as shown in FIG. In FIG. 11, the signal line 352 is an O in the instruction.
It is the upper 9 bits of the 16 bits of PS50, and the signal line 351 is the other bits. 1330 and 133
1 is NOT logic and 1332 is AND logic.
The signal line 134 is “1” for a tagged data instruction, and is “0” for other instructions.

If the operation word (OPW) has high regularity, the entire instruction decoder 130 can be realized as one decoder by using the ROM, PLA or random logic.

The tag / pointer separation circuit SEP160 has the configuration shown in FIG. 12, and the control signal 3 from the A-CTL 140 is supplied.
When 70 is “1”, the tag and the pointer are separated from the displacement on the signal line 340, and the signal line 3 is separated.
Output on 80,390.

Here, in the case of the present embodiment, the tag cutout circuit 161 can be constructed by a circuit as shown in FIG. In FIG. 13, the upper 8 bits of the signal line 340 are output to the signal line 344, and when the signal line 370 is “1”, the tag is output to the signal line 380.

Further, in the case of the present embodiment, the pointer cutout circuit 162 can be constituted by a circuit as shown in FIG. 14th
In the figure, the signal line 343 outputs the lower 24 bits of the signal line 340, and the signal lines 367 and 347 respectively output the 28th bit and the 24th bit of the signal line 340.

In the pointer cutout circuit 162, the signal line 370 is “1”.
At this time, if the output of the TL153 is "1", that is, if it is an 8-bit tag, the sign extension data of the 24-bit pointer is ASB.
If the output of TL153 is "0", the sign extension data of 28-bit pointer is output to ASBB400.
Output to. If the signal line 370 is “0”, the value of the signal line 340 is output to the ASBB 400 as it is.

The tag length detection circuit TL153 is a circuit for detecting whether the tag included in the tagged data is 8 bits or 4 bits,
In the case of this embodiment, it can be constructed by a circuit as shown in FIG. In FIG. 15, the signal line 344 is the signal line 34.
The upper 4 bits of 0 are output, and 151 is an AND logic that takes the logical product of these. Of the tagged data shown in FIG. 4, the TL 153 has an 8-bit tag, that is, the output signal line 159 is "1" when the upper 4 bits are "1111" and is "0" when it is a 4-bit tag.

In the present embodiment, the tag length detection circuit includes a T
There are L150, TL151, and TL152.
The function and internal configuration are the same.

In the case of the present embodiment, the tag cutout circuit TAG-EXT250 can be constructed by a circuit as shown in FIG. In FIG. 16, the upper 8 bits of the ESBB 430 are output to the signal line 434, and when the 8 bit tag, that is, the signal line 156 is “1”, the signal line 434 is output to the signal line 251 as a tag. When the 4-bit tag, that is, the signal line 156 is "0", the upper 4 bits are "0000" on the signal line 251, and the tag is output to the lower 4 bits.

In the case of this embodiment, the data cutout circuit MSK240 can be constructed by a circuit as shown in FIG. In FIG. 17, the signal line 442 outputs the upper 8 bits of the ESAB440, and when the control signal 475 for cutting out data from the E-CTL 290 is true, the output 157 of the TL 151 is “1”, that is, the 8 bit tag. In this case, only the data part in which the above 8 bits are mastered is output to the signal line 445. If the output 157 of the TL 151 is "0" at this time, a 28-bit data section in which only the upper 4 bits are mastered is output to the output 445. Also, the signal line 47
If 5 is “0”, the data on the ESAB440 is output to the signal line 445 as it is.

The tag embedding circuit is positioned as one function of the arithmetic unit E-ALU 230, and in this embodiment, E
It can be realized by providing a circuit as shown in FIG. 18 in the ALU 230. In FIG. 18, the data in which the tag is embedded is output to the signal line 445, the upper 4 bits of the signal line 445 are output to the signal line 447, and the lower 24 bits are output to the signal line 448. Are output, and the other bits are output to the signal line 446. The tag to be embedded is output to the signal line 432, and when the tag embedding control signal 465 from the E-CTL 290 is “1”, the output 158 of the TL 152.
Is "1", that is, an 8-bit tag, the lower 24 bits of the signal 450 are output to the lower 24 bits of the output 450, and the signal line 432 is output to the upper 8 bits of the output 450.
Is output. At this time, if the output 158 of the TL 152 is "0", the lower 28 bits of the signal 450 is output to the lower 28 bits of the output 450, and the lower 4 bits of the signal 450 is output to the upper 4 bits of the output 450. 4 bits are output. If the tag embedding control signal 465 is "0", all the outputs 450 are "0".

FIG. 19 shows the internal configuration of the control circuit 290. E-CT
L290 is a control circuit of a micro program control system that generates various control signals for instruction execution.

Although the microprogram control method is used in this embodiment, a wire logic control method can be used when high-speed control is realized or when a less complicated instruction is executed. . Although the control circuit generally has more components and signal lines than those shown in FIG. 19, those not directly related to the present invention are omitted. In FIG. 19, reference numeral 296 is a control memory (CS),
Stores micro programs. A microinstruction register (MIR) 295 holds the microprogram read from the CS296. The microprogram address selector 297 follows the address of the control memory to be read next according to the signal line 289, and outputs the signal lines 299 and 30.
Select from 1,303,305. The entry modification circuit 291 uses the value of the RM 300 to change the E-CTL 290.
This is a circuit for modifying the entry address 460 of the above. In this embodiment, it can be constituted by a circuit as shown in FIG. In FIG. 20, the least significant bit of the entry address 460 is output to the signal line 461.
Other bits are output to 62. INSD
When the EC 130 generates an entry address of an instruction to be modified with the value of the RMB 300, the unidirectional instruction detection circuit 2910 detects the entry address, and outputs the signal line 291.
1 becomes "1", and the least significant bit of the address 299 to be read first from the CS296 is the output 46 of the RMB300.
It becomes 9. When the output of the UNIFI command detection circuit 2910 is “0”, the address 299 remains the entry address 460. Although the lowest bit is modified in this example, it is obvious that other bits can be used.

The tag determination circuit 293 uses the combination of the outputs 490 and 495 of the tag registers in accordance with the test pattern 304 specified by the microprogram to offset the jump address 303 of the microprogram.
To generate. In this embodiment, the logic having the functions shown in FIGS. 21 (1) to (3) can be used. 21st
The logic as shown in the figure can be easily realized by using ROM, RAM, PLA and the like.

The jump destination modification circuit 292 is a circuit for generating jump addresses separated by the offset 302 based on the jump address 303 specified by the microprogram, and performs so-called multi-way jump. In the present embodiment, the 22nd
It can be configured by a circuit as shown in the figure. Second
In FIG. 2, the signal line 3031 is a jump address 30.
The lower 4 bits of 3 are shown, and the signal line 3032 shows the other bits. Output jump address 3
The lower 4 bits of 01 are 3031 and the offset 302.
The logical sum of is output.

Next, an operation example when executing the untagged data instruction and the tagged data instruction will be described.

(1) Execution example of instructions for untagged data As an example of instructions for untagged data, a load instruction will be taken up and described. The Load instruction shown in (a) of FIG. 23 is an instruction for transferring the data in the operand designated by the operand specifier 1 to the operand designated by the operand specifier 2, and the operation code is (a) of FIG. ). In this embodiment, the addressing mode of the operand specifier 1 is set to 32 bits immediate, and the addressing mode of the operand specifier 2 is set to register direct.

The Load instruction is read from the MM 800 and stored in the IBR 110 in the form as shown in FIG.
Then, the aligner 120 outputs the operation code and the mode designator to the signal lines 350 and 355, respectively (the 25th
(B1) and (b2)) are input to the instruction decoder INSDEC130. The upper 9 bits of the operation code are input to the tagged data instruction detection circuit 133 and are found to be untagged data instructions, and the signal line 134 becomes "0". In response to this, the E-CTL entry address generation circuit 131 outputs the entry address of the untagged data instruction Load to the signal line 460. In parallel with this, A
The -CTL entry address generation circuit 140 decodes that the source operand is in the 32-bit immediate addressing mode, and outputs the entry address for the immediate addressing mode to the signal line 360.

The A-CTL 140 uses the control signal 370 of the SEP 160.
Is set to "0", and a control signal required for address calculation not shown in the figure is output.

At this time, 32 bit immediate data is output to the signal line 340 by the ALN 120 (FIG. 25 (c)). The tag / pointer separation circuit SEP160 is
This immediate data is input, but the signal line 37
Since 0 is “0”, the data as it is is sent to the signal line 4
00 (FIG. 25 (d)). The immediate data on the signal line 400 passes through the A-ALU 190 in a through state, is stored in the IMR 210, and the address calculation in the immediate addressing mode is completed.

On the other hand, the E-CTL 290 reads the microprogram from the control memory CS296 according to the entry address of the Load instruction input via the signal line 460 and generates a control signal for instruction execution, but the Load instruction has no tag. Since it is a data instruction, the control lines 470, 480, 455, 475, 465 of the circuits for tagged data are "0".
Becomes Then, the immediate data in the IMR 210 passes through the data cutout circuit MSK240,
Further, it passes through the E-ALU 230 and is stored in the ERF 220, and the load command is completed.

(2) Execution example of instruction for data with tag As an example of instruction for data with tag, a put-constant instruction will be taken up and described. Pu shown in FIG. 23 (b)
The t-Constant instruction uses the tagged data in the operand specified by operand specifier 1 as operand specifier 2
Is an instruction to be transferred to the operand designated by, and the operation code is as shown in FIG.

Here, the addressing mode of the operand specifier 1 is the tagged immediate addressing mode,
The addressing mode of operand specifier 2 is register direct.

The Put-Constant instruction is read from the MM 800 and stored in the IRB 110 in the form as shown in FIG. Then, the aligner 120 outputs the operation code and the mode designator to the signal line 350 (FIG. 26 (b)),
Input to the instruction decoder INSDEC130. The upper 9 bits of the opcode are input to the tagged data instruction detection circuit 133 and are found to be tagged data instructions.
The signal line 134 becomes “1”. In response to this, the E-CTL entry address generation circuit 131 outputs the entry address of the tagged data instruction Lcstp to the signal line 460. In parallel with this, the A-CTL entry address generation circuit 140 decodes that it is in the tagged immediate addressing mode, and since the signal line 134 is "1", it is in the correct addressing mode. And outputs the entry address for the tagged immediate addressing mode to the signal line 360. AC
The TL 140 sets the SEP 160 control signal 370 to "1" in accordance with the entry address on the signal line 360.

At this time, 32-bit tagged data is output by the ALN 120 to the signal line 340 (FIG. 26 (c)). The tag / pointer separation circuit SEP160 is
This tagged data is input, and the signal line 370 is "1".
Therefore, the tag is output to the signal line 380, and the sign-extended pointer is output to the signal line 400.

This pointer is added by the PC 170 and the A-ALU 190 by the control signal from the A-CTL (not shown) and stored in the IMR 210 and the MAR 310, and the tagged immediate address calculation is completed.

On the other hand, the E-CTL 290, according to the Put-Constant instruction entry address input via the signal line 460,
The microprogram is read from the control memory CS296 and a control signal for instruction execution is generated. Put-Constan
In the t instruction, the tag in the TAG 200 and the pointer in the IMR 210 need to be combined and stored as tagged data in the ERF 220. Therefore, the tag embedding control signal 465 becomes “1”, and the E-ALU 230 embeds the tag. Stored in the ERF and the Put-Constant command is completed.

An addition instruction will be taken up and described as another example of execution of the tagged data instruction. In the addition of an instruction for untagged data, the data type is uniquely determined by the instruction, as is well known. That is, even in the same 32-bit sequence, if it is an integer addition instruction, it is calculated as a 32-bit integer, and if it is a floating addition instruction, 32 bits are divided into an exponent part and a mantissa part.

On the other hand, in the addition of the tagged data instruction, the type of data is determined by the tag when the instruction is executed, and the operation is changed or the exception is detected according to the determination. For example, in the instruction shown in FIG. 5, addition of tagged data is designated as an operation, two operands are designated in the ER0 and ER1 registers by an operand specifier, and the tag in the ER0 register is designated in FIG. It is assumed that the word shown and the tag in the ER1 register are Long. The control circuit 290 for instruction execution judges the tag of each operand according to the test pattern of FIG. 21 (No. 3),
In this case, the processing specified by offset 5 causes ER0
The 16-bit integer of is expanded to 32 bits. And ER
After the addition with the 32-bit integer indicated by the pointer of 1, the result is stored in the place indicated by the pointer of ER1 and the instruction is completed.

As another case, when the tag of the specified operand has a data type (str, Lst, etc.) that is not suitable for addition, the second
Offset 1 according to the test pattern shown in Fig. 1 (No. 3).
When 1 is specified and an operation exception occurs, the control circuit 290 for instruction execution sets the PC 170 to perform exception jump to a specific address (not shown). The subsequent processing is equivalent to the operation exception in the untagged instruction, and the exception processing is performed by software according to the procedure well known to those skilled in the art.

In this embodiment, a 32-bit microprocessor MC6802 manufactured by Motorola Co., Ltd. is used as an instruction system for untagged data.
Although upward compatibility with 0 is adopted, it is clear that the present invention is not based on this instruction system, and can be applied to other instruction systems.

〔The invention's effect〕

According to the present invention, in a computer in which untagged data and tagged data have the same word length, the untagged data instruction and the tagged data instruction can be executed as the same instruction set, so that the untagged data instruction and the tag This has the effect of making a program suitable for knowledge engineering that uses mixed data instructions in a mixed manner more practical.

[Brief description of drawings]

FIG. 1 is a block diagram of the internal configuration of a data processing device showing an embodiment of the present invention, FIG. 2 is an explanatory diagram of a general-purpose register used in the present invention, and FIG. 3 shows a data format used in the present invention. FIG. 4, FIG. 4 is a diagram showing a concrete example of tagged data, FIG. 5 is a diagram showing a format of an instruction executable by the present invention, and FIG. 6 is an addressing mode used in the explanation of FIG. FIG. 7 is a diagram showing the format of the displacement (disp) shown in FIG. 5, FIG. 8 is a diagram showing the details of the operand, and FIG. 9 is a diagram showing the computer to which the present invention is applied. FIG. 10 is a diagram showing the overall structure, FIG. 10 is a block diagram of an embodiment of the instruction decoder shown in FIG. 1, and FIG. 11 is a circuit diagram of an embodiment of an instruction detection circuit 133 for tagged data shown in FIG. FIG. 12 is a specific example circuit of the tag / pointer separation circuit shown in FIG. FIG. 13 is a circuit diagram showing a concrete example of the tag cutting circuit shown in FIG. 12, FIG. 14 is a circuit diagram showing a concrete example of the pointer cutting circuit shown in FIG. 12, and FIG. 15 is a tag length shown in FIG. Circuit diagram of a specific example of the detection circuit, 16th
FIG. 17 is a circuit diagram of a concrete example of the tag cutting circuit shown in FIG. 1, FIG. 17 is a circuit diagram of a concrete example of the data cutting circuit shown in FIG. 1, and FIG. 18 is a concrete example of the arithmetic unit shown in FIG. Example circuit diagram,
FIG. 19 is a diagram showing an internal configuration of the control circuit shown in FIG.
FIG. 20 is a circuit diagram of a specific example of the entry modification circuit shown in FIG. 1, FIG. 21 is a logic diagram used to explain the operation of the tag determination circuit shown in FIG. 1, and FIG. 22 is the jump shown in FIG. FIG. 23 is a diagram showing an internal configuration of the pre-modification circuit, FIG. 23 is a diagram showing a concrete execution example of an instruction, FIG. 24 is a diagram showing a concrete embodiment of an opcode of an instruction used in the present invention, and FIG. Is a diagram showing data of each part used for explaining an execution example of an instruction for untagged data according to the present invention, and FIG. 26 is each part used for explaining an execution example of an instruction for tagged data according to the present invention. It is a figure which shows the data of. 130 ... Instruction decoder, 160 ... Tag / pointer separation circuit, 200 ... Tag register, 210 ... Pointer and immediate register, 370 ... Control signal for tag / pointer separation circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tadaaki Bando 4026 Kujimachi, Hitachi City, Hitachi, Ibaraki Prefecture Hitachi Research Laboratory Ltd. (72) Inventor Hiroaki Nakanishi 5-2-1 Omikacho, Hitachi City, Ibaraki Prefecture Ceremony company Hitachi Ltd. Omika factory (72) Inventor Kenji Hirose 3-2-1, Saiwaicho, Hitachi City, Ibaraki Hitachi Engineering Co., Ltd.

Claims (23)

[Claims] 1. A data processing device for processing an operand according to an instruction consisting of an operation code and an operand specifier, in a tagged data including a tag for designating a data type of the operand as the operand and a tag not including the tag. Memory means for respectively storing the untagged data, a first type instruction for processing the tagged data as the instruction and a second type instruction for processing the untagged data, and an instruction called from the memory means. If the discrimination means discriminates from the operation code whether the instruction is the first type instruction or the second type instruction, and if the determination result of the discrimination means is the first type instruction, the tag portion of the tagged data is determined. , Tag determination means for determining the operation of tagged data, and if the determination result of the determination means is the first type instruction, the tag determination is performed. Means for executing the operation of the tagged data determined by the means and executing the operation of the untagged data according to the operation code of the instruction of the second type, with the tag having a uniform word length A data processing apparatus, wherein a first type instruction and a second type instruction for respectively processing data and untagged data are mixed and processed. 2. The data processing device according to claim 1, wherein the tag is composed of a plurality of bits. 3. The operand designator according to claim 1, wherein the operand specifier indicates the address of the memory in which the operand is stored, the register in which the operand is stored, or the operand itself. Characteristic data processing device. 4. The data processing device according to claim 1, wherein the at least one untagged data is floating point data. 5. The data processing device according to claim 1, wherein the second type instruction for processing at least one of the untagged data is a floating point instruction. 6. The claim 1 according to claim 1, wherein the tag determining means cuts out a tag from the tagged data, and the cut out tag performs an operation different from bits other than the tag. Characteristic data processing device. 7. The tag determining means or the arithmetic means according to claim 1, wherein when the operand specifier specifies an operand, the predetermined addressing for the tagged data is Data processing means for generating a predetermined signal when different addressing is designated. 8. The data processing device according to claim 1, wherein the memory means has a register file for holding the tagged data and the untagged data. 9. The data processing according to claim 1, wherein the memory means has a register for holding the first type instruction and the second type instruction. apparatus. 10. A data processing device for processing an operand according to an instruction consisting of an opcode and an operand specifier, wherein tagged data including a tag for specifying the data type of this operand as the operand and the above tag are not included. Memory means for respectively storing untagged data, a first type instruction for processing the tagged data as the instruction, and a second type instruction for processing the untagged data, and the first type instruction or the above Arithmetic means for executing the operation of the tagged data or the untagged data according to the opcode of the second type instruction, wherein the arithmetic means is based on the opcode of the instruction called from the memory means. An instruction or a second type instruction, and the result of the determination by the determining means is the first type instruction. Nara, the data processing apparatus characterized by having a tag determination means for determining the tag portion of the tagged data, determines the operation of the tagged data. 11. The data processing device according to claim 10, wherein the tag is composed of a plurality of bits. 12. The operand designator according to claim 10, wherein the operand designator indicates the address of the memory in which the operand is stored, the register in which the operand is stored, or the operand itself. Characteristic data processing device. 13. The data processing device according to claim 10, wherein the at least one untagged data is floating point data. 14. The data processing device according to claim 10, wherein the at least one second type instruction for processing the untagged data is a floating point instruction. 15. The tag determination means according to claim 10 cuts out a tag from the tagged data, and the cut-out tag performs an operation different from that of bits other than the tag. Characteristic data processing device. 16. The tag determining means or the arithmetic means according to claim 10, wherein when the operand specifier designates an operand, the predetermined addressing is performed on the tagged data. A data processing device, which generates a predetermined signal when different addressing is designated. 17. The data processing device according to claim 10, wherein the memory means has a register file for holding the tagged data and the untagged data. 18. The data processing according to claim 10 or 17, wherein said memory means has a register for holding said first type instruction and said second type instruction. apparatus. 19. A data processing device for processing an operand according to an instruction, wherein the operand has a first operand having a tag consisting of a plurality of bits indicating a data type within a basic word length, and the tag within the basic word length. Is a second operand that does not have, and the above-mentioned instruction holds the above-mentioned operand or the above-mentioned operand and the first field containing the content of the above-mentioned operand processing and information indicating whether to process the above-mentioned first operand. An instruction having at least a second field containing information identifying the location of the memory means, the memory means holding the instruction and the operand respectively, and decoding the first field of the instruction A check for detecting whether the instruction read from the memory means is an instruction for processing the first operand. If the operand specified by the second field is the first operand, the output means and the detection means perform operand processing based on the contents of the tags of the first field and the first operand. And a processing means for performing the operand processing based on the first field if it is the second operand. 20. The data processing device according to claim 19, wherein the at least one first operand is floating point data. 21. The data processing device according to claim 19, wherein the detecting means cuts out a tag from the first operand. 22. A data processing apparatus according to claim 19, wherein said memory means has a register file holding said first operand and said second operand. 23. A data processing device according to claim 19 or 22, wherein said memory means has a register for holding said instruction.