JPH0652517B2 - Data processing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a signal processing technique and a technique effectively applied to a serial communication system in a data processing system. For example, serial I / O in a data processing system such as a micro computer system. The present invention relates to a technique effectively used for an O device.

BACKGROUND ART As a data transfer method between a micro computer and a peripheral device, there are a parallel method for transferring a plurality of bits of data in parallel and a serial method for transferring one bit at a time in sequence. Further, in the serial system, there are a clock synchronous system and a non-synchronous system (asynchronous system) that transfer data in synchronization with a clock signal.

In the asynchronous serial transfer system, as shown in FIG. 1, there is a start bit Bstart of 1 bit "0" (space) at the beginning, followed by, for example, an 8-bit data portion, and finally 2 bits. A signal having a stop bit Bstop consisting of a bit "1" (mark) is transmitted and received as one frame of data.

However, in the conventional micro-computer system which is designed to perform asynchronous serial transfer, when one frame of data is loaded into the 1-byte receive data register and reception is completed, the received data is processed by a microprocessor (hereinafter referred to as CPU). ) Reads into a register like an internal accumulator, does some processing, and then receives the next data. Also, at the time of transmission, the data to be transmitted was once read from the memory into the accumulator and then transferred to the transmission register for transmission (Hitachi: 8 / 16-bit micro computer, September 1982). Issue 66-68, 752
Therefore, the reading of data from the memory or the receiving register to the accumulator and the transfer of the data from the accumulator to the memory or the transmitting register must be executed according to a program. As a result, there is a problem that the load on the software becomes large and the throughput decreases.

In addition, if the communication speed increases and two or more frames of data are continuously sent while the microcomputer is processing the received data, the first one of the two frames will be sent.
The data of the frame is lost (it can be replaced with the data that came later), which causes a so-called overrun error. To prevent this, while the CPU is processing the previous data, the RTS (Request to Send) signal is sent from the CPU side to the data transmission source so that the data of two or more frames will not be transmitted continuously. It is necessary to send an appropriate signal such as. Therefore, there is an inconvenience that the communication speed is limited by the processing capacity of the CPU and the software.

[Object of the Invention] An object of the present invention is to provide a signal processing technique which exhibits a significant effect as compared with the conventional art.

Another object of the present invention is to reduce the load on software, improve throughput, and speed up transmission / reception processing in a micro computer system employing, for example, a serial transfer system.

Yet another object of this invention is to provide C at any time after data transfer.
It is to improve the function of the system by enabling the PU to confirm whether or not data has already been transferred.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[Outline of Invention] The outline of a typical invention disclosed in the present application will be described below.

That is, according to the present invention, instead of the 1-byte reception data register and the transmission data register, a plurality of 1-byte registers are connected in multiple stages to provide a buffer circuit having a FiFo (first-in first-out) configuration. It is possible to directly transfer a block of a plurality of bytes of data between the buffer circuit and the memory by an instruction from the CPU without passing through an accumulator, thereby reducing the load on software and improving the throughput and the communication speed. Is achieved.

In addition, the present invention provides a function for setting or resetting a memory cell read by a data transfer instruction from the memory to the transmission data buffer circuit, thereby accessing C
The purpose of the above is to enable the PU to check whether data has already been transferred at any time.

The present invention will be specifically described below with reference to the drawings.

[Embodiment] FIG. 2 shows an embodiment in which the present invention is applied to a single-chip microcomputer provided with an asynchronous serial I / O. The micro computer unit (hereinafter referred to as MCU) surrounded by a chain line A in the figure is formed on one semiconductor chip such as silicon, although not particularly limited thereto.

In the figure, reference numeral 1 denotes a CPU including a controller having an appropriate forward circuit and ALU (arithmetic logic unit) and registers such as a program counter and an accumulator.
(Microprocessor). The CPU 1 has a ROM (Read Only Memory) 3 in which a program is stored via an internal bus 2 and a RAM (Random Access Memory).
A storage device such as a memory 4 and a serial I / O 5 are connected.

The serial I / O 5 includes a transmission data buffer circuit 6 connected to the internal bus 2, a reception data buffer circuit 7 also connected to the internal bus 2, and one word (for example, 8 words) connected to the transmission data buffer circuit 6. A transmission shift register 8 capable of holding (bit) data, and a reception shift register 9 connected to the reception data buffer circuit 7 and capable of holding 1-word data are also provided.

Although not particularly limited, in the transmission data buffer circuit 6 and the reception data buffer circuit 7, for example, four registers each capable of holding 1-word data are connected in multiple stages,
It has a FiFo system configuration. That is, the internal bus 2
The four words of data stored in the transmission data buffer circuit 6 are transferred to the transmission shift register 8 in the order in which they are stored, and the data received from the reception terminal Rx to the reception shift register 9 are received word by word. The data is transferred to the buffer circuit 7 and held therein, and is ejected to the internal bus 2 in the order of entry.

Further, 11 is an oscillation circuit provided with a crystal oscillator externally attached to the chip, and 12 is an appropriate division of the oscillation signal output from the oscillation circuit 11, and a clock signal CLK in the system.
And a frequency dividing circuit that forms the sampling clock SCL and the like.

In this embodiment, a RAM 1 where a load instruction is issued from the CPU 1 at the time of transmission and the first data is stored.
When a signal indicating a predetermined address in 4 is output to the internal bus 2, the RAM 4 is accessed and desired data is read. Then, the data of the number of words (4 words in the embodiment) according to the stage of the transmission data buffer circuit 6 is output to the internal bus 2, and this data is directly taken into the transmission data buffer circuit 6 one after another. Transmission data buffer circuit 6
The data taken in is automatically transferred word by word to the transmission shift register 8 in synchronization with an appropriate clock signal supplied from the frequency dividing circuit 12. At this time, CPU1
As long as the above-mentioned load command is issued, one block of data is read from the RAM 4 and transferred to the transmission data buffer circuit 6 via the internal bus 2.
U1 can move to another process.

The transmission shift register 8 shifts bit by bit in synchronization with an appropriate clock from the frequency dividing circuit 12 and serially outputs 8-bit data to the transmission terminal Tx.
At this time, the transmission shift register 8 adds a start bit Bstart of "0" to the beginning of the transfer data and a stop bit Bstop of "1" to the end of the data to form a transmission terminal Tx as a data signal of one frame. Output to.

On the other hand, in a microcomputer system adopting an asynchronous serial transfer system, a peripheral device such as a floppy disk driver has a start bit Bstart at the head and a stop bit Bstop at the end at the end to the MCU. A data signal as shown in FIG. 1 is sent.

Then, the reception shift register 9 detects the falling edge of the start bit Bstart, and operates and fetches the following 8-bit data at a speed corresponding to the baud rate, that is, the data transfer speed. The reception shift register 9 is operated at a speed proportional to the baud rate by the sampling clock SCL output from the frequency dividing circuit 12.

The 1-word data received by the reception shift register 9 is automatically transferred to the reception data buffer circuit 7.
The reception data buffer circuit 7 becomes full (4 in the embodiment).
When the word data is taken in), the interrupt signal IRQ indicating that the data is full is supplied from the serial I / O 5 to the CPU 1. Then, the CPU 1 receives this and issues a store instruction to collectively transfer the data in the received data buffer circuit 7 to the RAM 4 in the order in which they came in, and store the data in a desired area in the RAM 4.

Therefore, the CPU 1 can perform other processing until the received data buffer circuit 7 is filled with the received data.
This reduces the load on the software and improves throughput and communication speed.

Further, in this embodiment, the reset circuit 10 of the RAM 4 is
Is provided, for example, the output of RAM4 or CP
The memory cell at the address containing the data read in response to the load instruction from U1 is reset and "0" is written.

Therefore, when the data to be transmitted is read from the RAM 4, all the areas containing the data are reset to "0". As a result, CPU1 is RAM
By reading the data in the predetermined area in 4 and checking the contents, it is possible to know at any time whether or not the data in the RAM has been transferred. In the above case,
Instead of resetting the read memory cell to "0" and setting it to "1", it may be set.

Although not shown, the serial I / O 5 should come within a certain time after the fall of the start bit is detected in the case where the data portion of the signal shown in FIG. 1 is generally extended. It is possible to provide an error detection circuit that sets the framing error when the stop bit is not detected and prevents the data from being transferred to the reception data buffer circuit 7.

In the above embodiment, the present invention is applied to the asynchronous serial I.
However, the present invention is not limited to this, and can be applied to a system having a synchronous serial I / O.

Further, in the above-mentioned embodiment, the one applied to a single-chip microcomputer is explained as an example, but the present invention can also be applied to an I / O chip for an interface which constitutes a normal microcomputer system.

[Effects] (1) In a system equipped with a serial I / O, a reception shift register and a transmission shift register capable of holding 1-byte data, and a plurality of 1-byte registers connected in multiple stages to form a FiFo-structured transmission data Since the buffer circuit and the reception data buffer circuit are provided, the instruction from the CPU does not need to go through the accumulator,
The effect of enabling block transfer of a plurality of bytes of data directly between the buffer circuit and the memory has the effect of reducing the load on software and improving throughput and communication speed.

(2) In a system equipped with serial I / O, the function to set or reset the memory cell read by the data transfer command from the memory to the transmission data buffer circuit is provided, so that the data is not transmitted during transmission. The effect of changing the contents of the memory before and after being read has an effect that the CPU can always confirm whether or not the data has already been transferred by accessing a predetermined area of the memory.

Although the present invention has been specifically described based on the embodiments of the invention made by the present inventor, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, in the above embodiment,
Although each of the transmission data buffer circuit and the reception data buffer circuit has a four-stage configuration, the number of stages is not limited to four and may be any number of stages, that is, three stages or five or more stages.

[Field of Use] In the above description, the case where the invention made by the present inventor is mainly applied to the microcomputer system which is the field of use as the background has been described, but the present invention is not limited to this. It is applicable to all systems with serial communication interface.

For example, when serial communication is performed between the CPU and the peripheral device, such as a personal computer equipped with a peripheral device such as a floppy disk driver or a CRT display, or a system development device equipped with a console typewriter, or a data terminal or When connecting a terminal to a large central computer online for serial communication, such as a cash register system, or when performing serial communication between computers, and a system adapted to perform serial communication using an acoustic coupler, etc. It can also be applied to.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a waveform of a signal transmitted during asynchronous serial communication, and FIG. 2 shows an embodiment of a single-chip microcomputer provided with a serial I / O device according to the present invention. It is a block diagram. 1 ... CPU (microprocessor), 2 ... internal bus, 4 ... memory (RAM), 5 ... serial I / O,
6 ... Transmission data buffer circuit, 7 ... Reception data buffer circuit, 8 ... Transmission shift register, 9 ... Reception shift register, 10 ... Reset circuit, Rx ... Reception terminal, Tx ... Transmission terminal.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Chie Kawashita 4-6 Kanda Sugawadai, Chiyoda-ku, Tokyo Inside Hitachi, Ltd. (56) References JP-A-55-88118 (JP, A) JP-A-53- 11539 (JP, A) Actually opened Sho 57-20034 (JP, U)

Claims (3)

[Claims] 1. A control means, a readable / writable memory, and a serial I / O for transmitting / receiving serial data.
The serial I / O device comprises a transmission terminal and a reception terminal, and a parallel processing unit for converting 1-word parallel transmission data into serial data and outputting the serial data to the transmission terminal. Serial conversion means, serial-parallel conversion means for converting serial received data input from the reception terminal into parallel data in word units, and a sequence in which a plurality of registers each capable of holding 1-word data are connected and stored. In the same manner, a transmission data buffer circuit for transferring the transmission data to the parallel-serial conversion means and a plurality of registers each capable of holding 1-word data are connected, and the reception data sent from the serial-parallel conversion means are sequentially received. It is configured to output data in the order in which it is held and output an interrupt signal to the control means when the received data is full. The control means executes a load instruction to block-transfer the desired data in the memory directly to the transmission data buffer circuit, and a store instruction when the interrupt signal is received. And block transfer the data stored in the reception data buffer circuit directly to a desired area in the memory, and at the time of data transfer based on the load instruction,
A data processing device characterized by being configured to activate a reset means for clearing all areas in the memory from which transfer data has been read to "0" or "1". 2. A data processing device comprising a control means, a readable / writable memory, and a serial I / O device for transmitting / receiving serial data on one semiconductor substrate. The serial I / O device includes a transmission terminal and a reception terminal, parallel-serial conversion means for converting one word of parallel transmission data into serial data and outputting the serial data to the transmission terminal, and input from the reception terminal. Serial-parallel conversion means for converting serial reception data into parallel data word by word, and a plurality of registers each having a function of holding one word of data are connected to transfer the transmission data to the parallel-serial conversion means in the order stored. Of the transmission data buffer circuit and a plurality of registers each of which can hold one word of data, respectively, are connected to sequentially store the reception data sent from the serial-parallel conversion means. And a reception data buffer circuit configured to output an interrupt signal to the control means when the reception data is full, as well as outputting the data in the input order, wherein the control means is Execute a load instruction to block transfer the desired data in the memory directly to the transmission data buffer circuit, and execute a store instruction when receiving the interrupt signal to directly input the data in the reception data buffer circuit. While performing block transfer to a desired area in the memory, at the time of data transfer based on the mode command,
A data processing device characterized by being configured to activate a reset means for clearing all areas in the memory from which transfer data has been read to "0" or "1". 3. A serial I circuit comprising a clock generation circuit.
3. The data processing device according to claim 2, wherein the / O device is configured to operate in synchronization with the clock generated by the clock generation circuit.