JPH0652532B2 - Circuit board wiring route search method by CAD - Google Patents
Circuit board wiring route search method by CADInfo
- Publication number
- JPH0652532B2 JPH0652532B2 JP63124125A JP12412588A JPH0652532B2 JP H0652532 B2 JPH0652532 B2 JP H0652532B2 JP 63124125 A JP63124125 A JP 63124125A JP 12412588 A JP12412588 A JP 12412588A JP H0652532 B2 JPH0652532 B2 JP H0652532B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- empty
- empty line
- circuit board
- point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Design And Manufacture Of Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔概要〕 CADによる回路基板の配線径路探索方法に関し, CADによる回路基板の配線径路探索にあたって,処理
時間を大幅に短縮して処理の高速化を図るとともに,必
要な処理データ量を大幅に削減することを目的とし, 回路基板に主配線方向に走る配線走行軸を複数並列に配
列して各配線走行軸を配線可能な空ラインと配線不能な
障害物ラインに区分し,始点を含む空ラインから探索を
開始して終点を含む空ラインに到達するまで互いに隣接
する空ラインを,探索した空ラインに追番を付与しつつ
順次に探索し,終点を含む空ラインに到達したら追番を
逆に辿って終点から始点に到る空ラインを決定し,この
決定した空ラインについて隣接する空ラインのオーバラ
ップする区間のうちの少なくとも1点を両者間の接続箇
所に決定することで,配線経路を決定するように構成さ
れる。DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to a method for searching a wiring path of a circuit board by CAD. When searching a wiring path for a circuit board by CAD, the processing time is greatly shortened and the necessary processing is performed. For the purpose of significantly reducing the amount of data, a plurality of wiring traveling axes that run in the main wiring direction are arranged in parallel on the circuit board, and each wiring traveling axis is divided into an empty line that can be wired and an obstacle line that cannot be wired. , The empty line including the start point is searched sequentially until the empty line including the end point is reached until the empty line including the end point is reached. When it reaches, it determines the empty line from the end point to the starting point by tracing back the serial number, and at least one point in the overlapping section of the adjacent empty line between the two points is determined between the two. The wiring path is determined by determining the connection point of.
本発明はCAD(Computer Aided Design) によるによる
回路基板の配線径路探索方法に関する。The present invention relates to a wiring path searching method for a circuit board by CAD (Computer Aided Design).
CADによる配線径路探索処理においては処理の高速化
をはかって処理時間を短縮することが必要とされてい
る。In the wiring path search processing by CAD, it is necessary to speed up the processing and shorten the processing time.
従来,CAD装置によるプリント基板に配線処理,すな
わち一方の部品ピン位置と他方の部品ピン位置とを接続
する配線径路を探索する処理,としてはセル方式が用い
られている。2. Description of the Related Art Conventionally, a cell system is used as a wiring process on a printed circuit board by a CAD device, that is, a process for searching a wiring path connecting one component pin position and the other component pin position.
セル方式においては,プリント基板面をXおよびY軸方
向にメッシュ状に区分し,このメッシュの各枡(セルと
称される)に障害物の有無を示す情報を保持させ,障害
物のないセルを始点から終点に辿ることによって配線パ
ターンの探索を行うものである。In the cell method, the printed circuit board surface is divided into meshes in the X and Y axis directions, and information indicating the presence or absence of obstacles is held in each cell (called a cell) of this mesh, and cells without obstacles are held. The wiring pattern is searched by tracing from the start point to the end point.
すなわち,第3図はセル構造による径路探索処理の一例
を示す図であり,図中の網目状の各枡がセルであり,斜
線が施されたセルは障害物セル,それ以外は空セルであ
る。またSは始点となる部品ピン位置に対応する始点セ
ル,Eは終点となる部品ピン位置に対応する終点セルで
ある。That is, FIG. 3 is a diagram showing an example of the path search processing by the cell structure, in which each mesh-shaped cell in the figure is a cell, the shaded cells are obstacle cells, and the other cells are empty cells. is there. Further, S is a starting point cell corresponding to the starting point of the component pin, and E is an ending point cell corresponding to the ending point of the component pin.
始点セルSから終点セルEまでのパターン径路の探索
は, (1)始点セルSからその上下左右のセルを見てそれら
が障害物セルであるか否かを判定し,障害物セルでない
場合にはパターン走行可能であるためそれらのセルに追
番「1」をセル情報として付加する。The search for the pattern path from the start point cell S to the end point cell E is performed by (1) looking at the cells above and below and to the left and right of the start point cell S to determine whether or not they are obstacle cells. Since the pattern can be run, the additional number "1" is added to these cells as cell information.
(2)次に追番「1」のセルから更に上下左右のセルを
見てそれらのセルが障害物セルあるいは追番が既に付加
されたセルでなければ,それらのセルに「追番+1」の
セル情報を付加する。なお既に追番がセル情報として付
加されているセルに対しては追番付加処理は行わない。
このような処理を繰り返し行うと,始点セルSから始ま
って隣接する空セルに追番1,2,3,4…がセル情報
として順次に付加されていく。(2) Next, looking at the upper, lower, left, and right cells from the cell with the serial number "1", and if those cells are not obstacle cells or cells to which the serial number has already been added, add "serial number +1" to those cells. Cell information is added. Note that the additional number addition process is not performed on cells to which the additional number has already been added as cell information.
When such a process is repeated, additional numbers 1, 2, 3, 4 ... Are sequentially added to adjacent empty cells as cell information starting from the starting point cell S.
(3)追番が付加されたセルの隣接セルが終点セルEと
なった場合,径路探索処理は完了する。第3図では追番
「11」の隣接セルが終点セルEとなっている。(3) When the cell adjacent to the cell to which the additional number is added becomes the end point cell E, the route search processing is completed. In FIG. 3, the adjacent cell with the additional number “11” is the end point cell E.
配線パターン径路は,終点セルEから各セルの追番を,
E→11→10→9→……→3→2→1→Sのように逆
にトレースして始点セルSまで到達することによって求
められる。The wiring pattern path is from the end cell E to the serial number of each cell,
It is obtained by tracing in the reverse order of E → 11 → 10 → 9 → ... → 3 → 2 → 1 → S and reaching the start point cell S.
セル構造による配線径路の探索では,始点セルSと終点
セルEとが遠く離れている場合には多数のセルをその間
に経由しなければなない。この場合,セル情報の蓄積は
多数の経由セルの各々について行うため,処理時間が長
くなり,処理するデータ量も膨大となる。In the search for the wiring path by the cell structure, when the start point cell S and the end point cell E are far apart, many cells must be routed therebetween. In this case, since cell information is stored for each of a large number of transit cells, the processing time becomes long and the amount of data to be processed becomes enormous.
したがって本発明の目的は,CADによる回路基板の配
線径路探索にあたって,処理時間を大幅に短縮して処理
の高速化を図るとともに,必要な処理データ量を大幅に
削減することにある。Therefore, an object of the present invention is to significantly reduce the processing time and speed up the processing when searching the wiring path of the circuit board by CAD, and to significantly reduce the required processing data amount.
本発明にかかるCADによる回路基板の配線経路探索方
法は,回路基板に主配線方向に走る配線走行軸を複数並
列に配列して各配線走行軸を配線可能な空ラインと配線
不能な障害物ラインに区分し,始点を含む空ラインから
探索を開始して終点を含む空ラインに到達するまで互い
に隣接する空ラインを,探索した空ラインに追番を付与
しつつ順次に探索し,終点を含む空ラインに到達したら
追番を逆に辿って終点から始点に到る空ラインを決定
し,この決定した空ラインについて隣接する空ラインの
オーバラップする区間のうちの少なくとも1点を両者間
の接続箇所に決定することで,配線経路を決定するよう
に構成される。According to a method of searching a wiring path of a circuit board by CAD according to the present invention, a plurality of wiring travel axes that run in the main wiring direction are arranged in parallel on the circuit board, and each wiring travel axis can be wired and an unobstructable obstacle line. The search is started from an empty line including the start point and the adjacent empty lines are sequentially searched until the empty line including the end point is reached, and the searched empty line is sequentially numbered, and the end point is included. When an empty line is reached, the trailing numbers are traced backward to determine an empty line from the end point to the starting point, and at least one point in the overlapped section of adjacent empty lines for this determined empty line is connected between them. The wiring route is determined by determining the location.
本発明方法を第1図の径路探索処理例を参照にして説明
する。第1図は第3図の場合と障害物の配置位置が同じ
環境における径路探索処理を示す図である。The method of the present invention will be described with reference to the path search processing example of FIG. FIG. 1 is a diagram showing a path search process in an environment in which the positions of obstacles are the same as those in FIG.
プリント基板配線においては,基板を多層構造として配
線層別に主配線方向を決定し,XY軸方向に分離配線す
る手法が配線率向上に寄与することが知られている。In printed circuit board wiring, it is known that a method of determining a main wiring direction for each wiring layer with a substrate having a multi-layered structure and separately wiring in the XY axis directions contributes to improvement of a wiring rate.
本発明方法では,各配線層別に径路探索を行うものと
し,第2図はX軸方向が主配線方向となっている層につ
いての径路探索を取り扱う。すなわち第2図では主配線
方向に平行な複数のパターン走行軸L1〜L8を複数
本,列状に配置する。各パターン走行軸は配線パターン
の走行が可能な空ライン範囲と不可能な障害物範囲とに
区分された空ライン構造となっている。障害物範囲は図
中に斜線領域で示される。In the method of the present invention, the path search is performed for each wiring layer, and FIG. 2 deals with the path search for the layer whose X-axis direction is the main wiring direction. That is, in FIG. 2, a plurality of pattern running axes L 1 to L 8 parallel to the main wiring direction are arranged in rows. Each pattern running axis has an empty line structure divided into an empty line range in which the wiring pattern can travel and an impossible obstacle range. The obstacle range is indicated by a shaded area in the figure.
始点部品ピン位置Sから終点部品ピン位置Eまでの径路
探索は以下の手順により行われる。The path search from the starting point component pin position S to the ending point component pin position E is performed by the following procedure.
(1)始点Sをその領域上に含む空ラインに空ライン情
報として追番「1」を付加する。(1) An additional number “1” is added as blank line information to a blank line including the start point S on the area.
(2)追番「1」の空ラインからみて上下配線走行軸L
5,L7上の空ライン「1」に隣接する空ライン位置を
探し,あればその空ラインに対して「追番+1」を空ラ
イン情報として付加する。この時,既に空ラインに追番
が付加されていれば追番付加処理は行わない。(2) Vertical wiring running axis L as seen from the empty line with the additional number “1”
5 , an empty line position adjacent to the empty line “1” on L 7 is searched, and if there is, an “additional number + 1” is added to the empty line as empty line information. At this time, if the additional number is already added to the empty line, the additional number addition process is not performed.
(3)上述の処理(2)を,終点Eを含んだ空ラインに
追番が付加されるまで繰り返し行い,終点Eの空ライン
に追番が付加されたのならば径路探索処理を完了する。(3) The above process (2) is repeated until an additional number is added to the empty line including the end point E, and if the additional number is added to the empty line at the end point E, the path search process is completed. .
(4)終点Eを含む空ラインから,E→4→3→2→1
→Sの順に追番を逆に辿る逆トレースを行って,終点E
から始点Sに到る空ラインを決定する。(4) From an empty line including the end point E, E → 4 → 3 → 2 → 1
→ Perform a reverse trace by tracing the serial numbers in reverse order in the order of S, and end point E
An empty line from the start point S to the start point S is determined.
(5)上記の(4)で決定した空ラインについて所定の
規則に従って隣接する空ライン間を接続して,配線パタ
ーン経路を決定する。所定の規則としては,,空ライン
4上の終点Eと空ライン1上の始点Sを固定点とし,例
えば空ライン4と空ライン3間は両者の配線がオーバラ
ップしている区間のうちの少なくとも1点を両者間の接
続箇所とする。これを空ライン3と2間,空ライン2と
1間についても行う。この際,図4に示されるように,
これらの空ライン1〜4で作られる面領域を主配線方向
と垂直方向あるいは45゜方向に走って空ライン1から
4に到る配線(イ)(ロ)などが可能であれば,そのよ
うに配線するとよい。(5) Regarding the empty line determined in (4) above, adjacent empty lines are connected according to a predetermined rule to determine a wiring pattern route. As a predetermined rule, the end point E on the empty line 4 and the starting point S on the empty line 1 are fixed points, and for example, between the empty line 4 and the empty line 3, the wirings of the two overlap each other. At least one point is the connection point between the two. This is also performed between the empty lines 3 and 2 and between the empty lines 2 and 1. At this time, as shown in FIG.
If wirings (a) and (b) that run in the plane area formed by these empty lines 1 to 4 in the direction perpendicular to the main wiring direction or in the direction of 45 ° and reach the empty lines 1 to 4 are possible, It is good to wire to.
なお,上記接続を行った結果,隣接する空ライン間で電
気経路として重複しているため不要となる部分が生じた
場合には,経路決定後にその部分を再び空ラインとして
解放するとよい。In addition, as a result of the above connection, when an unnecessary part is generated because the electric paths overlap between the adjacent empty lines, it is preferable to release the part as an empty line again after the route is determined.
この空ライン構造による径路探索では,従来,複数のパ
ターン走行可能セルで構成されていた箇所をライン化し
て連続した1ラインと見なしてFROM−TO座標で管
理するものであるから,始点と終点を結ぶ径路はそれを
構成するコンポーネントが一般に少なくてすむ。上述の
例では,従来のセル方式の場合には経由セル数が11個
であるものが,本発明の空ライン方式では経由ライン数
が4本ですみ,この経由コンポーネント数の差がそのま
ま径路探索時間の差およびデータ削減量となる。In the path search by this empty line structure, a place which has been conventionally composed of a plurality of pattern-runnable cells is made into a line and is regarded as one continuous line to be managed by FROM-TO coordinates. A connecting path generally requires fewer components. In the above example, the number of passing cells is 11 in the case of the conventional cell method, but the number of passing lines is only 4 in the empty line method of the present invention, and the difference in the number of passing components is the same as the path search. It is the difference in time and the amount of data reduction.
以下,図面を参照して本発明の実施例を説明する。第2
図は交換機用のプリント基板を設計するためのCAD装
置に本発明方法を適用した場合のプリント基板配線処理
の手順の一実施例を示す流れ図である。Embodiments of the present invention will be described below with reference to the drawings. Second
The drawing is a flow chart showing an embodiment of the procedure of printed circuit board wiring processing when the method of the present invention is applied to a CAD device for designing a printed circuit board for an exchange.
まず初期設定として,部品ピン位置や配線禁止領域等の
データにもとづき,プリント基板上の主配線方向の走行
軸毎にパターン走行可能空ラインと障害物ラインとを決
定し,これらの情報を空ライン構造情報としてメモリD
1に保持する(ステップS2)。First, as an initial setting, based on data such as component pin positions and wiring prohibited areas, a pattern-runtable empty line and an obstacle line are determined for each running axis in the main wiring direction on the printed circuit board, and this information is used as an empty line. Memory D as structural information
It is held at 1 (step S2).
次に全配線区間中から,これから配線処理しようとして
いる配線区間の始点ピン位置と終点ピン位置のデータを
一つ抽出する(ステップS3)。Next, from the entire wiring section, one piece of data of the starting point pin position and the ending point pin position of the wiring section to be subjected to wiring processing is extracted (step S3).
抽出するデータがない場合には全配線区間の配線トライ
が終了したものであるので,配線処理を終了する(ステ
ップS8)。If there is no data to be extracted, it means that the wiring trial has been completed for all the wiring sections, so that the wiring process is completed (step S8).
未配線区間が抽出されたのならば,当該区間に対して前
述の〔作用〕の欄で説明した空ライン構造を使用して配
線径路を探索する(ステップS4)。If the unwired section has been extracted, a wiring path is searched for using the empty line structure described in the above section [Operation] for the section (step S4).
径路探索の結果,配線不可能であれば,配線処理で各空
ラインに付加した到着追番情報をクリアして(ステップ
S7),再び未配線区間の抽出を行う(ステップS
3)。If the result of the route search indicates that wiring is not possible, the arrival serial number information added to each empty line in the wiring processing is cleared (step S7), and the unwired section is extracted again (step S).
3).
配線可能な径路が探索できた時には,そのパターンデー
タを障害物データとして空ライン構造D1に追加する
(ステップS6)。その後,各空ラインの追番情報をク
リアする(ステップS7)。なお空ライン構造D1は各
区間の配線処理毎に毎回再設定する必要はなく,配線結
果パターンデータを障害物として初期空ライン構造に追
加(更新)していくものである。When a wirable path is found, the pattern data is added to the empty line structure D1 as obstacle data (step S6). After that, the serial number information of each empty line is cleared (step S7). The empty line structure D1 does not need to be reset every time wiring processing is performed in each section, and wiring result pattern data is added (updated) to the initial empty line structure as an obstacle.
ステップS3で全区間の配線が終了したと判定された場
合には処理を終了する(ステップS8)。When it is determined in step S3 that the wiring of all the sections is completed, the process is completed (step S8).
交換機用プリント基板は他のプリント基板と同様に多く
の回路的機能を満足させるべく回路の大規模化,プリン
ト基板に搭載される部品の高安定化が要求されており,
このためには回路配線が非常に複雑化する。上述の本発
明方法はこれら多数の配線区間を持ち,配線が進むにつ
れて障害物が増えて配線が複雑となる処理に対して,顕
著な処理時間と処理データ量の削減効果がある。Similar to other printed circuit boards, printed circuit boards for exchanges are required to have a large-scale circuit and high stability of components mounted on the printed circuit board in order to satisfy many circuit functions.
This makes circuit wiring very complicated. The above-described method of the present invention has a large number of wiring sections, and has a remarkable effect of reducing the processing time and the processing data amount in the processing in which obstacles increase and wiring becomes complicated as the wiring progresses.
本発明によれば,CADによる回路基板の配線径路探索
にあたって,処理時間を大幅に短縮して処理の高速化を
図れるとともに,必要な処理データ量も大幅に削減する
ことができる。According to the present invention, when the wiring path of the circuit board is searched by CAD, the processing time can be significantly shortened, the processing speed can be increased, and the required processing data amount can be significantly reduced.
第1図は本発明方法による径路探索処理を説明する図, 第2図は本発明方法を適用したCAD装置における径路
探索処理手順の例を示した流れ図, 第3図は従来のセル方式による径路探索処理を説明する
図である。 第4図は本発明方法における主配線方向に垂直な方向へ
の配線経路を説明するための図である。 図において, S……始点、E……終点 1〜11……追番FIG. 1 is a diagram for explaining a path search processing by the method of the present invention, FIG. 2 is a flow chart showing an example of a path search processing procedure in a CAD device to which the method of the present invention is applied, and FIG. 3 is a path by a conventional cell system. It is a figure explaining a search process. FIG. 4 is a diagram for explaining a wiring path in a direction perpendicular to the main wiring direction in the method of the present invention. In the figure, S ... Starting point, E ... Ending point 1-11 ... Serial number
Claims (1)
複数並列に配列して各配線走行軸を配線可能な空ライン
と配線不能な障害物ラインに区分し, 始点を含む空ラインから探索を開始して終点を含む空ラ
インに到達するまで互いに隣接する空ラインを,探索し
た空ラインに追番を付与しつつ順次に探索し, 終点を含む空ラインに到達したら追番を逆に辿って終点
から始点に到る空ラインを決定し, この決定した空ラインについて隣接する空ラインのオー
バラップする区間のうちの少なくとも1点を両者間の接
続箇所に決定することで,配線経路を決定するようにし
たCADによる回路基板の配線経路探索方法。1. A plurality of wiring running axes that run in the main wiring direction are arranged in parallel on a circuit board, and each wiring running axis is divided into an empty line that can be wired and an obstacle line that cannot be wired, starting from an empty line that includes a starting point. Until the empty line including the end point is reached, the empty lines that are adjacent to each other are sequentially searched while adding the additional numbers to the searched empty lines. When the empty line including the end point is reached, the additional numbers are reversed. By determining an empty line from the end point to the starting point by tracing, and determining at least one point in the overlapping section of the adjacent empty line as the connection point between the two, the wiring route is determined. A method for searching a wiring path of a circuit board by CAD so as to determine.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63124125A JPH0652532B2 (en) | 1988-05-20 | 1988-05-20 | Circuit board wiring route search method by CAD |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63124125A JPH0652532B2 (en) | 1988-05-20 | 1988-05-20 | Circuit board wiring route search method by CAD |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01293472A JPH01293472A (en) | 1989-11-27 |
| JPH0652532B2 true JPH0652532B2 (en) | 1994-07-06 |
Family
ID=14877546
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63124125A Expired - Fee Related JPH0652532B2 (en) | 1988-05-20 | 1988-05-20 | Circuit board wiring route search method by CAD |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0652532B2 (en) |
-
1988
- 1988-05-20 JP JP63124125A patent/JPH0652532B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01293472A (en) | 1989-11-27 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |