JPH0652867B2 - FET logic circuit - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a logic circuit for inverting the polarity of a digital signal using an FET (Field Effect Transistor), and particularly to a source-grounded input for inverting the polarity of an input signal. The present invention relates to a circuit configuration for speeding up the output operation of a so-called BFL (Buffered FET Logic) circuit including a section and a source follower output section which is a buffer for obtaining a required output level.

(b) Conventional Technology and Problems FIG. 1 shows a conventional circuit in which the source follower outputs the output voltage of the circuit as a required output level to an inverter circuit that inverts the polarity of the input digital signal when the source is grounded. It is a figure which shows one Example of what is called a BFL circuit which attached the buffer part. In the figure, FETs 1 to 4 are field effect transistors, D is a diode, V _dd is a source-grounded input transistor FET 2 and its load transistor FET 1 (gate G ₁ and source S ₁ are directly connected) A source grounded section which is an inverter circuit consisting of and a buffer for the output signal of the FET 2 and the output voltage of the drain D ₂ of the FET 2 is input to its gate G ₃ and its level is shifted from its source S _3. Transistor of constant current source via diode D for
This is the power supply voltage of the source follower section that outputs the required output level by FET 4 (gate G ₄ and source S ₄ are directly connected).

−V _SS1 is the negative power supply voltage for the output level shift of the output signal (OUT) from the cathode side of the diode D of the source follower section, IN is the input terminal of the input digital signal, and OUT is the output signal. It is an output terminal.

In the conventional logic circuit for inverting the polarity of the digital signal by the GaAs FFT IC, the BFL circuit is generally used as shown in FIG. 1, but the drain D ₁ and the source follower of the transistor FET 1 at the source grounded part are used. Power supply to the drain D ₃ of the transistor FET 3 in the same section is the same voltage V _dd
I am trying. Therefore, when the input digital signal to the gate G ₂ of the source-grounded input transistor FET 2 which is the input terminal IN is the low level signal L, the input transistor FE
Drain D _{2 of} T 2 is connected to its source S ₁ and gate G ₁ , and the drain current does not flow in the transistor FET 1 which is the load, and the power supply voltage supplied to the drain D _{1 of the} FET 1
V _dd appears almost as it is at the source S ₁ of the FET 1 and is output as the output voltage from the drain D _{2 of the} FET 2 connected to the source S ₁ to the gate G ₃ of the FET 3 in the source follower section, which is a high level signal H. Is input as the voltage V _dd . However, since the drain D ₃ to be the same power supply voltage V _dd of the FET 3 is supplied, a drain current does not flow in the mom and the drain D ₃ and the gate G ₃ of FET 3 are the same potential. Therefore, in order to make the drain current flow by the constant current source transistor FET 4,
It is necessary for the gate G ₃ of ₃ to have a positive forward bias with a polarity greater than zero (V _gs > 0) as the voltage V _gs between it and its source S ₃ . That is, when the input signal is the low level signal L, the transistor FET that is the output source follower
Due to the low current source transistor FET 4, the voltage V _gs between the gate G ₃ and the source S _{3 of} FET 3 is consequently forward due to the current flowing through ₃ . When V _gs goes forward, FET 3
The junction capacitance C _gs between the gate and source of the FET 3 increases more than when V _gs is zero, and the operating region of FET 3 becomes an unsaturated region, and its mutual conductance g _m decreases. Due to the above factors, there is a drawback that the time response of the output operation of the transistor FET 3 of the conventional circuit becomes slow.

(c) Object of the Invention It is an object of the present invention to provide a FET logic circuit capable of constrained output operation by eliminating the drawback of the prior art that the time response of the output operation is delayed.

(d) Structure of the Invention The above object is to directly connect the gate (G ₁ ) and the source (S ₁ ) of the gate to input a signal, and to the drain (D ₁ ) of the first power supply voltage for bias ( V _dd1 ), a drain current flows, and a first transistor (FET1) showing a constant resistance value, and a gate (G ₁ ) and a source (S ₁ ) of the _first transistor (FET1)
Connected to its drain (D ₂ ) and its source (S ₂ ) to ground, and its drain current is controlled by the signal voltage (IN) input to its gate (G ₂ ). A source grounded section including two transistors (FET2) and a second transistor (FET) which is an output voltage of the source grounded section.
The voltage of the drain (D ₂ ) of ₂ ) is input to its gate (G ₃ ), and the first power supply voltage (V _dd1 ) and its pinch-off voltage (V _p ) are applied to its drain (D ₃ ). The third transistor (FET3) supplied with the bias power supply voltage (V _dd2 ) set equal to the sum of
And the source (S ₃ ) of the third transistor (FET3), the diode
The anode of (D) is connected, the cathode of the diode (D) is directly connected to its gate (G ₄ ) and source (S ₄ ) which are constant current sources, and the DC voltage (-V _ss1 ) is connected to the drain (D ₄ ) of the given fourth transistor (FET ₄ ), and has a source follower section which outputs (OUT) an output signal of a predetermined level from the cathode side of the diode (D). This is achieved by the FET logic circuit of the present invention configured as described above.

(e) Embodiment of the Invention FIG. 2 is a circuit diagram showing an embodiment of the present invention. The symbols and numbers in the figure are the same as in Fig. 1, but only the power supply is different. V _dd1 is the source ground source power supply voltage, V _dd2 is the source follower power supply voltage, and -V _ss1 is the output transistor. Is the power supply voltage for the signal level shift of. As shown in FIG. 2, the power source of the source grounding part and the source follower part are different power sources, and the first power source voltage V _{dd1 of the} power source of the source grounding part is _used.
And the relationship between the second power supply voltage V _dd2 of the power supply of the source follower section are set so as to satisfy the following formula.

V _dd1 <V _{dd2 In} the BFL circuit shown in FIG. 2, when the low level signal L is input to the input terminal IN, the voltage V of the drain D ₂ of the FET 2
_D2 is the first power supply voltage V _{dd1 of the} power supply of the drain D ₁ of FET 1.
F is approximately equal to the first power supply voltage V _dd1
The voltage V _D2 of the drain D ₂ of ET 2 is F of the source follower section.
Input to gate G _{3 of} ET 3. The FET 3 has a drain D ₃ supplied with a second power supply voltage V _dd2, and a constant current source transistor FET 4 connected to the source S ₃ via a diode D causes a constant drain current to flow. At this time
The time constant τ of the drain current of FET 3 is τ ＝ (1 / g _m ) ・ C because the capacitance C _gs between the gate source and the capacitance C _gd between the gate and drain are connected in series via the gate G _{3. gs} · C _gd / (C _gs + C _gd ). Hereinafter, description will be made using mathematical expressions. FET drain
The current I _D between the sources is generally expressed by equation (1).

I _D = β (V _gs −V _p ) ² (1 + λV _DS ) tanh (αV _DS ) ...
...... (1) where β: coefficient of FET saturation current (I _DSS ), λ: current increase coefficient in saturation region, α: coefficient in unsaturated region, V _DS : FET drain-source voltage , V _gs : FET gate-source voltage, V _p : FET pinch-off voltage. If V _gs is less than that, drain-source current _{ID stops} flowing V _gs
Is the value of.

The transconductance g _{m of the} FET is obtained by differentiating I _D in the equation (1) by the voltage V _gs between the gate and the source, and is expressed by the equation (2).

_{g m = ΔI D / ΔV gs} = 2β (V gs -V p) (1 + λV DS) tanh (αV DS) ...
(2) To speed up the output operation of FET 3, the time constant τ above
Needs to be small. Further, as is clear from the equation (2), in order to increase g _m , it is necessary to add V _DS such that tanh (αV _DS ) = 1. Further, C _gs can be expressed by a function of V _gs , and is expressed by equation (3).

C _gs ＝ C _{gs (0)} / (1 −V _gs / V _Bi ) ^1/2 ……… (3) V _Bi : Schottky barrier barrier, and small C _gs to reduce the time constant τ. To V
_It is necessary to increase _gs in the negative direction.

In the present invention, FET 3 is set because V _dd1 <V _dd2.
The gate-drain voltage V _gd is V _gd ≈ V _dd1 − V _dd2 , and the gate-source voltage V _gs is V _gs ≈ 0.

In the equation (1) of the current I _D of the general FET, tanh (αV _DS ) ≈ 1 in the saturation region, so I _D is β (V _gs −V _p ) ² (1 + λV _DS ). Since the FET has a good saturation characteristic, 1> λV _DS , which can be approximately expressed as I _D ≈β (V _gs −V _p ) ² . Source follower FET 3 and FET 4
When using FETs with the same characteristics, β and V _p become equal. And the gate and source of FET 4 are directly connected, and V
_{Since gs} is 0 _v , I _D is I _D = βV _p ² . At this time, since the same value of I _D flows in the FET 3, I _D = βV _p ² = β (V _gs3 −V _p ) ² Therefore, V _{gs3 of} the FET 3 also becomes 0 _v .

That is, when low level signal L is input to FET 2, FE
The drain voltage V _d of T 2 becomes V _d = V _dd1 and FET 3
Of the source voltage V _s in order to keep the _{V s = 0 v, V s} = V
It will be _dd1 . At this time, the gate-source junction capacitance C _gs is C _gs ≈ C _gs (0) (C _gs (0) is the gate-source junction when the gate-source potential is 0 _v. The gate-drain junction capacitance C _gd is C _gd <C _gd (0) (C _gd (0) is the gate-drain junction when the gate-drain potential is 0 _v. Capacity).

The reason for C _gd <C _gd (0) is as follows.

That is, as described above, V _gd of FET 3 is V _gd = V _dd1 − V _dd2 <0, and when the gate-drain potential is V _gd , the gate-drain junction capacitance C _gd (V _gd ) Is represented by C _gd (V _gd ) = C _gd (0) / (1−V _gd / V _p ) ^1/2, so that C _gd (V _gd ) when V _gd <0 is C _gd (0)
It gets smaller. Furthermore, at this time, the mutual conductance g
_m becomes its maximum value g _m max. The maximum value g _m max
G _m is obtained by changing the bias voltage of its FET 3
Is the maximum value of.

As described above, the time constant τ can be decreased by decreasing the junction capacitances C _gs and C _gd of the FET 3 and increasing the mutual conductance g _m , so that the fall time of the signal pulse of the output of the FET 3 can be reduced. It can be improved by speeding up, and the operation of the BFL circuit can be speeded up. Also, by setting the pinch-off voltage V _p of FET 3 so that the following _expression V _dd2 = V _dd1 + | V _p |, when the input signal of FET 2 is the low level signal L, the drain D _{2 of} FET _{2 Becomes} substantially equal to the first power supply voltage V _dd1, and the voltage V _gd between the gate and drain of the FET 3 becomes V _gd = V _dd1 − (V _dd1 + | V _p |) = V _p . At the same time, due to the saturation current, the source potential of FET 3 becomes V _dd2 = V _dd1 + | V _p |
The drain-source voltage V _ds3 is also V. _p . That is, the voltage V _gs between the gate and the source is approximately 0 when V _{gs ≈0} . Also, the mutual conductance g _m is g _m ≈ 2β · | V _p
, And the fall time of the output pulse can be reduced to about 1/2 compared with the case of the conventional same power supply V _dd .

Because, as described above, the current I _{D in} the saturation region of the FET is
Since the equation (1) is I _D = β (V _gs −V _p ) ² , the transconductance g _m is the following equation g _m = d ID / d V _gs = 2β (V _gs −V _p ). The V _gs of the FET 3 is 0 v as described above, and thus g _m = −2βV _p . This is because V _p is a negative value equal to or less than 0 v, and thus g _m = 2β · | V _p |.

(f) Effect of the invention To configure the FET logic circuit so that it can respond at high speed,
According to the present invention, an inverter circuit is provided by adding a power source Vdd2 of another voltage, as compared with the invention described in JP-A-58-103232. Does not increase the number of elements.

Since the logical amplitude of the signal output increases, it is resistant to external noise and variations in the elements.

That is a great effect.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration example of a conventional BFL circuit, and FIG. 2 is a circuit diagram showing a configuration of an embodiment of the present invention.

Claims (1)

[Claims] 1. A gate (G ₁ ) and a source (S ₁ ) of which are directly connected to input a signal, and a first power supply voltage (V _dd1 ) for bias is supplied to its drain (D ₁ ). Then, a first transistor (FET1) showing a constant resistance value by flowing a drain current, and a gate (G ₁ ) and a source (S ₁ ) of the _first transistor (FET1)
Connected to its drain (D ₂ ) and its source (S ₂ ) to ground, and its drain current is controlled by the signal voltage (IN) input to its gate (G ₂ ). A source grounded section including two transistors (FET2) and a second transistor (FET) which is an output voltage of the source grounded section.
The voltage of the drain (D ₂ ) of ₂ ) is input to its gate (G ₃ ), and the first power supply voltage (V _dd1 ) and its pinch-off voltage (V _p ) are applied to its drain (D ₃ ). The third transistor (FET3) supplied with the bias power supply voltage (V _dd2 ) set equal to the sum of
And the source (S ₃ ) of the third transistor (FET3), the diode
The anode of (D) is connected, the cathode of the diode (D) is directly connected to its gate (G ₄ ) and source (S ₄ ) which are constant current sources, and the DC voltage (-V _ss1 ) is connected to the drain (D ₄ ) of the fourth transistor (FET ₄ ) to which it is applied, and has a source follower section which outputs (OUT) an output signal of a predetermined level from the cathode side of the diode (D) FET logic circuit characterized by.