JPH0652946B2 - Descrambler - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a descramble apparatus having a function of receiving a scrambled (encrypted) television signal and descrambled (decrypted) the television signal.

[Technical background of the invention]

In recent years, scramble transmission has attracted attention as one of the transmission modes of television signals. This is to prevent unauthorized viewing by anyone other than the specified person and transform and transmit the television signal. The receiving side can obtain a normal image only by preparing a special descrambler for decoding. it can.

Although various scrambling methods for television signals have been proposed, one of the methods will be described below as an intra-line rotation method. In the in-line rotation system, the video period P of the NTSC video signal 91 shown in FIG. 4 (a) is divided into two parts at arbitrary points to be replaced at the transmitting side, and a digital sync signal 93 for giving an absolute address to the horizontal sync part 92 is added. Then, it is transformed into the format shown in FIG. At this time, the information on the division points is transmitted together with another system, for example, audio data. Here, the address x of the division point is given in units of 108 blocks obtained by dividing the video period into 108 equal parts. The video period P is exchanged at the division point x, but the blocks at the addresses x-1 and x are allowed to be overlapped due to the superposition when they are combined on the receiving side.
4 and 95 are newly prepared, and the margin 94 is added before the address x and the margin 95 is added after the address x-1. When the scrambled video signal is digitized and processed on the receiving side, it is normally sampled at 4f _SC (f _SC : color subcarrier frequency). Therefore, FIG.
As shown in (a), one horizontal period is divided into 910 equal parts by sample points. The absolute address corresponds to this sample point, so the address x in block units is 140, 147
The value is taken every 7th address such as address, ..., 903th address, 910th address.

FIG. 5B is an enlarged view of the digital synchronizing signal 93 added to the horizontal synchronizing portion 92. The digital sync signal 93 is inserted from address 19 to address 64, and its frequency is And has 7 cycles. Since the above-mentioned address x is grasped based on this digital synchronization signal 93, if the address of the digital synchronization signal 93 is accurately detected on the receiving side, the decoding point address read from the division point address x sent together with the audio information. y (see FIG. 4 (b)) can also be accurately known, and the scramble signal 96 can be appropriately combined without causing a hue shift or the like. In addition to the digital sync signal 93, the scramble signal 96 has a frame sync signal 98 which is transmitted at a rate of once per frame in addition to the digital sync signal 93. A scramble timing signal 99, which is transmitted for each piece and serves as a switching reference signal for various scrambled data, is added.

The scrambled signal described in detail above is based on the decoding point information y read from the division point information x on the receiving side, and is based on the video period P.
Are replaced, the margins 94 and 95 and the digital synchronizing signal 93 are removed, and the synchronizing signal 92 is replaced, and the data is decoded as shown in FIG. 4 (c).

Next, an example of a descrambling device that descrambles the above scrambled signal 96 will be described with reference to the drawings. FIG. 6 is a block diagram showing the decoding circuit 100 portion of the descrambling device.

The scrambled signal 96 is band-limited by the low pass filter (LPE) 1 and then supplied to the A / D conversion circuit 2. Here, sampling and quantization are performed and the digital scrambled video signal 3 is output. The sampling frequency f _{S in} this case is f _S = 4 _f SC, and the sampling phase is synchronized with the absolute address of the digital synchronizing signal. The system clock 4 that gives the timing of the sambling can be generated by the clock generation circuit 5, the A / D conversion circuit 2, the decoding circuit 100.
And is used as a reference for circuit operation. The digital scramble video signal 3 is supplied to the clamp calculation circuit 6 and clamp error calculation is performed at the timing of the burst gate pulse 8 output from the timing generation circuit 7, and the D / A conversion circuit 10 is supplied as the digital clamp control signal 9.
Is supplied to. The burst gate pulse 8 gives the timing of color burst integration for detecting the magnitude of the pedestal level in the clamp calculation circuit 6, and has a width of 3 cycles of color burst, that is, 12 samples. The D / A conversion circuit 10 D / A converts the input digital clamp control signal 9 into an analog clamp control signal 11
Output as. The clamp control signal 11 is added as an offset voltage to the scramble signal 96 to be clamped.

The digital scrambled video signal 3 is sent to the PLL arithmetic circuit 1
A PLL error calculation is performed with the digital synchronization reference signal 14 according to the timing of the digital synchronization gate pulse 13 supplied to 2 and output by the timing generation circuit 7. The digital synchronization gate pulse 13 gives the timing of phase error integration for detecting the phase of the digital synchronization signal 93 in the PLL arithmetic circuit 12, and the digital synchronization signal 3
It has a width of one cycle, that is, 15 samples. The digital synchronization reference signal 14 is obtained by dividing the system clock 4 by 5 by the frequency dividing circuit 56, and the phase thereof coincides with the absolute numbers 19, 24, 29, etc. of the digital synchronization signal. the above
The digital phase error signal 15 output from the PLL arithmetic circuit 12 is D / A
The analog phase error signal 17 is converted via the conversion circuit 16 and supplied to the clock generation circuit 5. The clock generation circuit 5 outputs the system clock 4 whose phase is controlled by the analog phase error signal 17. As a result, the sampling phase matches the absolute address of the digital sync signal 93.

The scramble signal 96 is also supplied to the sync separation circuit 18, where the sync separation is performed and the decoded sync signal 19 is output. This decoded sync signal 19 is further supplied to the horizontal sync detection circuit 20.
And the horizontal sync signal is separated therefrom and the horizontal sync signal 21 is output. The horizontal synchronizing signal 21 is supplied to the timing generating circuit 7, where the burst gate pulse 8, the digital synchronizing gate pulse 13, and the digital synchronizing timing pulse 22 are generated and output. Digital sync timing pulse
22 is a gate pulse for detecting the first digital synchronizing signal 93, and detects 22 which is the first falling edge of the digital synchronizing signal 93, so that it rises near 19 and falls near 24. (See FIG. 5 (d)).

The digital sync detection circuit 23 is supplied with the digital scrambled video signal 3, the digital sync reference signal 14 and the digital sync timing pulse 22, detects the absolute address 24, and outputs the descramble reference signal 24 (fifth).
(See Figure (e)). The descramble reference signal 24 is supplied to the phase comparison circuit 25 and output from the horizontal write counter 26.
When the phase is compared with the address signal 27 and the phase is shifted, the phase control signal 28 is supplied to the horizontal writing counter 26, and the phase shift of the 24th address signal 27 output from the horizontal writing counter 26 is corrected. Be seen.

A decoding point address (y) signal 30 is supplied to the horizontal read counter 29 from another system, and a read address 31 for descrambling is output. The horizontal read counter 29 is controlled by the phase control signal 32 from the horizontal write counter 26 so that both counters operate in synchronization.

The digital scrambled video signal 3 is supplied to the 2H memory 33. Here, the digital scrambled video signal 3 has a write address 34 supplied from the horizontal write counter 26.
Are written in and read out by the read address 31 supplied from the horizontal read counter 29, and the video period P is replaced again.

By the way, the digital sync detection circuit 23 detects the frame sync signal 98 added to the horizontal sync portion 97 of the digital scrambled video signal 3 and supplies the frame sync detection signal 35 as a reference signal for frame sync to the phase comparison circuit 36. To do. A frame synchronization reference signal 38 is also supplied from the frame counter 37 to the phase comparison circuit 36, and phase comparison is performed between the frame synchronization detection signals 35. If the result of the comparison shows a phase shift, the comparison circuit 36 supplies the phase control signal 39 to the frame counter 37 in order to correct the phase of the frame synchronization reference signal 38. The frequency 2f _H output from the horizontal writing counter 26 is applied to the frame counter 37.
An input signal 40 of (f _H : horizontal frequency) is supplied.

Now, the horizontal writing counter 26 and the frame counter
Both outputs 41 and 42 of 37 are supplied to the synchronizing signal generating circuit 43. The synchronization signal generation circuit 43 generates a synchronization signal 44 and supplies it to the synchronization replacement circuit 45. The resynchronized video signal 46 output from the 2H memory 33 is also guided to the synchronization reassignment circuit 45. Since the digital synchronization signal 93 remains in the video signal 46, the synchronization reassignment circuit 45 reassigns the digital synchronization signal 93 and the synchronization signal 46,
Outputs digital NTSC video signal 47. Video signal 47
It is converted into an analog NTSC video signal 49 via the D / A converter 48, is interpolated by passing through the LPE 50 in the next stage, and is output as a decoded video signal 51.

The decoded scrambled signal 51 is then supplied to the selection circuit 52 together with the scrambled signal 96. This selection circuit 52
When the scramble signal 96 is not a scramble signal but a normal NTSC signal, the decoded video signal 51 selectively outputs one of the above-mentioned normal NTSC signals in accordance with the instruction of the mode switching signal 53. It is prepared for. That is, the mode switching signal 53 is a control signal for the switching circuit 54 in the selection circuit 52, and the mode switching signal 53
When the instruction mode of is the scramble mode, the decoded video signal 51 is output through the switching circuit 54,
When the instruction mode is the NTSC mode, the normal NTSC signal is sequentially output through the delay correction circuit 55 and the switching circuit 54. The reason why the delay correction circuit 55 is once passed through when outputting the normal NTSC signal is as follows. That is, when obtaining the decoded video signal 51,
Since the 2H memory 33 is used, if the NTSC signal and the decoded video signal 51 are simply switched and output, a relative delay occurs between both signals in the horizontal direction. The delay correction circuit 55 is provided to correct the relative delay in the horizontal tail direction, and is for eliminating the momentary shift of the screen at the time of mode switching.

[Problems of background technology]

The delay correction circuit 55 needs to have an accurate delay amount and a sufficient frequency characteristic. The delay correction circuit 55 is composed of passive components such as LC, and it is extremely expensive to reduce variations and obtain accurate delay and sufficient frequency characteristics.

By the way, when attempting to improve S / N deterioration in a transmission system, it is more effective to perform signal processing in the digital signal domain as is well known, and it is suitable for IC integration. Therefore, in the system shown in FIG. 6, it is optimal to perform signal processing for S / N improvement between the digital NTSC video signal 47 after the synchronization reassignment and the D / A conversion circuit 48. However, if this is done, the S / N cannot be improved because the signal path is different in NTSC mode.

As described above, the descrambling apparatus shown in FIG. 6 leaves room for improvement in terms of cost and additional functions in the future as represented by S / N improvement.

[Object of the Invention]

The present invention has been made in view of the above problems, and an object of the present invention is to provide a descrambler capable of supporting both NTSC and scramble modes without using an analog delay correction circuit.

[Outline of Invention]

According to the present invention, by switching the PLL operation according to the mode signal, the signal is digitized and processed and output in both the NTSC mode and the scramble mode.

Specifically, the whole system operates as a PLL system using a digital synchronization signal in the scramble mode and a PLL system using a burst signal in the NTSC mode.

〔The invention's effect〕

As a result, the input signal is digitized and processed regardless of the mode, eliminating the need for the conventional delay correction circuit and switching circuit. Therefore, the cost of the descrambler can be reduced. Further, according to the present invention, additional functions such as S / N improvement can be performed in the digital signal area through both modes, and the performance of the descrambling device can be improved and the possibility of multi-functionalization can be increased.

Example of Invention

An embodiment of the present invention will be described below with reference to the drawings. In the description, only points different from the descrambling device shown in FIG. 6 will be described. FIG. 1 shows a PLL arithmetic circuit 120 used in the descramble apparatus of the present invention.
FIG. The PLL operation circuit 120 has PLL error operation circuits 121, 1 corresponding to the scramble mode and the NTSC mode.
A switching circuit 123, which outputs the outputs of these error calculation circuits 121 and 122 in accordance with the mode, and a loop filter 1.
It consists of 24 and. In addition, the reference clock for performing the PLL calculation supplies the system clock 4 to the frequency dividing circuit 560 whose frequency division ratio is switched to 1/5 in the scramble mode and 1/4 in the NTSC mode according to the mode switching signal 53. It has gained.

Now, digital sync works effectively in scramble mode
The PLL error calculation circuit 121 includes a digital scrambled video signal 3, a digital synchronization gate pulse 13 and the frequency dividing circuit.
Reference clock 140 from 560 (4 / 5f in scramble mode)
_SC ) is being supplied. With the supply of these signals,
The PLL error calculation circuit 121 sets the value of the sampling point of the digital synchronization signal 93 to Q (see FIG. 5 (b)) and performs the following calculation to output an error signal E _S.

On the other hand, the digital scrambled video signal 3, the burst gate pulse 8 and the reference clock 140 (f _{SC in the} NTSC mode) are supplied to the berth PLL error calculation circuit 122 which works effectively in the NTSC mode. Supplied with these signals, the PLL error calculation circuit 122, the value of the sampling point of the burst signal 97 of the digital scrambled video signal 3 as shown in FIG. 2 as P, and the error signal E _N performs an operation shown below Output.

The error signals E _S and E _N respectively calculated as described above are supplied to the switching circuit 123 together. The switching circuit 123 follows the mode switching signal 53 and outputs E _S in scramble mode and NTSC.
Select respectively E _N at the time of mode, and supplies to the loop filter 124 as an output signal 125. The loop filter 124 smoothes the input error signal 125 and outputs the phase error signal 15 as D / A.
It is supplied to the conversion circuit 16 (see FIG. 6). Thus, in the PLL arithmetic circuit 120 used in the present invention, the PLL arithmetic operation based on the digital synchronization signal 93 in the scramble mode is performed.
In the NTSC mode, the PLL calculation based on the burst signal 97 is selected and performed.

Further, the descrambling device of the present invention is different from the descrambling device shown in FIG. 6 in that a switching circuit 300 is provided in the preceding stage of the 2H memory 33 as shown in FIG. The point is to supply the write address 340 and the read address 310. That is, in the NTSC mode, the switch 301 is instructed by the mode switching signal 53.
Is knocked down to the N side. As a result, the write address 34 output from the horizontal write counter 26 is the read address 31 to the 2H memory 33.
Since it becomes 0, both writing and reading control of the 2H memory 33 are performed by the same write address 34. Therefore, NT
In the SC mode, the 2H memory 33 operates simply as a 1H delay line. In addition, 2H memory 33 at this time
The synchronous reassignment circuit 45 to which the output 46 (delayed NTSC video signal) is supplied is controlled so that the output 46 is simply directed to the D / A conversion circuit 48 without performing the reassignment operation. On the other hand, in the scramble mode, the switch 301 is tilted to the S side, and the write control of the 2H memory 33 is performed by the write address 34 and the read control is performed by the read address 31 as before.

As described above, in the scramble device shown in FIG.
The scrambler according to the present invention can be obtained by adding the changes shown in FIGS. 3 and and deleting the selection circuit 52.

According to the scramble device of the present invention, the PLL arithmetic circuit, 2H
By controlling the mode switching of the memory and the synchronization switching circuit, the decoding circuit 100 portion shown in FIG. 6 can be shared by both modes. As a result, it is possible to eliminate the phase change of the output video signal due to the mode difference at the same time and perform the signal processing (for example, S / N improvement) in both modes in the digital signal area. Allows easy performance expansion.

When obtaining the descrambler according to the present invention, it is necessary to add a mode switching control function to the PLL arithmetic circuit or the like as described above, but considering that this can be achieved by IC, the number of IC chips increases. Is completely negligible, and does not cause an increase in circuit scale or cost. Rather, from the same point of view, it can be said that it is much more beneficial to be able to reduce the selection circuit which is an analog circuit used conventionally.

[Brief description of drawings]

FIG. 1 shows a PLL used in the descramble apparatus of the present invention.
2 is a block diagram of a video signal, and FIG. 3 is used in the descrambling device of the present invention.
2H memory configuration diagram, FIG. 4 is a schematic signal waveform diagram for explaining the in-line rotation system, FIG. 5 is a signal waveform diagram for explaining an address detection method in a descrambling device, and FIG. It is a block diagram of a scramble apparatus. 2 ... A / D conversion circuit, 3 ... digital scrambled video signal, 4 ... system clock, 5 ... clock generation circuit, 15 ... phase error signal, 16 ... D / A conversion circuit, 17 ... analog Phase error signal, 91 ... video signal, 93 ... digital synchronization signal, 96 ... scramble signal, 97 ... burst signal, 120 ... PLL calculation circuit, 121 ... digital synchronization PLL error calculation circuit, 122 ... burst PLL error calculation circuit.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Masaki Nakagawa 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Stock company inside Toshiba Yokohama Metal Factory (72) Inventor Susumu Komatsu 8 Shin-Sugita-cho, Isogo-ku, Yokohama, Kanagawa -Dio Video Engineering Co., Ltd. Development office (72) Inventor Yutaka Morii 22-1 Jinnan, Shibuya-ku, Tokyo Inside Broadcasting Center of Japan Broadcasting Corporation (72) Inventor Masahiro Soejima 2-2, Jinnan, Shibuya-ku, Tokyo No. 1 Japan Broadcasting Corporation Broadcast Center (72) Inventor Noboru Yamazaki No. 2-2-1 Jinnan, Shibuya-ku, Tokyo Inside the Japan Broadcasting Corporation Broadcasting Center

Claims (1)

[Claims] 1. A clock generation circuit for outputting a system clock, and an A / D for outputting a digital video signal obtained by sampling a video signal with the system clock and digitizing the video signal.
A conversion circuit, an input terminal for inputting a mode switching signal indicating whether the video signal is an in-line encrypted scrambled video signal or an unencrypted normal video signal, and the mode switching signal is When indicating a scrambled video signal, a first digital decoding circuit for decoding the digital video signal, and a digital reference signal for decoding the encrypted scrambled video signal inserted in the scrambled video signal. A first error calculation circuit that detects an error between a sync signal and a first sync reference signal obtained by dividing the system clock, and outputs a phase error signal according to the error, and the mode switching signal is the normal video signal. When showing a signal,
A second digital decoding circuit that outputs the digital video signal as it is, a color burst signal inserted into the scrambled video signal, and the system clock are frequency-divided by a frequency division ratio different from that of the first error calculation circuit. An error calculation circuit that detects an error from the second synchronization reference signal and outputs a phase error signal corresponding to this error, and controls the phase of the system clock output from the clock generation circuit according to the phase error signal. And a clock phase control circuit for controlling the descrambling device.