JPH0652960B2 - Time division - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION SUMMARY OF THE INVENTION The present invention has an apparently slow write cycle time,
To secure the timing margin of data and write enable, write n pieces of data in parallel to n pieces of speech path memory at the same time, and n times the speed of writing the same number of data from another n pieces of speech path memory. By serially reading in, the time division speech path is operated at high speed up to the limit limited by the read cycle time.

[Industrial application field]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time-division speech path, and more particularly to an ultra-high-speed time-division speech path capable of expanding the throughput of exchangeable data to the limit of the reading operation speed of the speech path memory.

[Conventional technology]

The time-division communication path in a digital exchange is composed of a time switch having a time slot switching function and a space switch for switching time slots between highways. Further, the time switch is composed of a speech path memory, a holding memory and a counter. The speech path memory stores digitally encoded voice information for highway multiplicity and the like, and the holding memory stores the writing address of the speech path memory ( Or a read address) is designated, and digitally encoded voice information or the like is sequentially read (or written) to the communication channel memory by the counter.

FIG. 3 is a block diagram of a conventional time division speech path.

In FIG. 3, 1 and 2 are channel memories, 3 are holding memories, 4 are counters, 5 are channel memory input registers, 6 and 8 are channel memory address registers, 7 are channel memory output registers, and 9 are , 10, 11 are selectors,
Reference numeral 12 is a holding memory input register, and 13 is a holding memory address register. IHW is the input data highway, DI, DO, WE, AD in the channel memories 1 and 2.
Input / output terminals are a data input terminal, a data output terminal, a write enable terminal, and an address input terminal, respectively. OHW is an output data highway and AHW is a holding memory input highway. DI, DO, WE, and AD in the holding memory 3 are input / output terminals, which are a data input terminal, a data output terminal, a write enable terminal, and an address input terminal, respectively.

FIG. 4 is an operation timing chart of FIG. The operation principle of the conventional time-division communication path of the so-called R / W separation method will be described with reference to FIGS. 3 and 4.

The data A, B, C, ... Of a certain time slot transmitted on the input data highway IHW are latched by the channel memory input register 5. Sequence sequence writing in one of the channel memories 1 or 2, for example 1,
The timing operation when random reading is performed in the other 2 will be described. Output 0 of counter 4,
1, 2, 3, ... Is selected by the selector 10 and latched in the speech path memory / address register 6. next,
By setting the write enable WE1 to the low level in synchronization with the clock, the data latched in the channel memory input register 5 is sequentially transferred to the channel memory 1 based on the address designated by the channel memory address register 6. Write. Also, the counter 4 used here
Output is branched to hold memory address register 1
3 and the contents A (0), A (1), A (2), ... Of the holding memory 3 are read based on the address. In the other channel memory 2, after selecting the output of the holding memory 3 by the selector 11, the channel memory
The address register 8 is latched, the contents of the speech channel memory 2 are read based on the address, selected by the selector 9, and then latched in the speech channel output register 7.
The output data is sent on the highway OHW. If the contents of the holding memory 3 are written in the order in which they are to be exchanged, it is possible to exchange and connect to an arbitrary time slot. Further, the communication channel memory 1 that is writing and the communication channel memory 2 that is reading are switched for each frame.
For example, in order to exchange and connect the data B on the time slot number # 1 of the input data highway IHW to the time slot number # 3 of the output data highway OHW, the content A (3) of the address [3] of the holding memory 3 is set to 1 And then the 4th
It is operated as shown in the second frame in the figure. That is,
In the configuration shown in FIG. 3, a write operation from the input data highway IHW or a read operation from the output data highway OHW is required within one time slot time.
In this case, the memory is required to have a high write speed and a high read speed. However, the current ultra-high speed memory requires a certain timing margin for setting the address, data and write enable at the time of writing, and therefore the write cycle time is longer than the read cycle time. Therefore, in the time-division communication path of FIG. 3, the maximum operation speed that can be exchanged is not determined by the high-speed performance of the memory, and is limited by the slow write cycle time including various timing margins. There is a problem that high speed performance cannot be fully utilized.

[Object of the Invention]

An object of the present invention is to solve such a conventional problem, relax the operation speed limit of the call path due to the write cycle time of the call path memory, and increase the operation speed of the call path up to the read time limit of the call path memory. The purpose is to provide a time-division communication path that can be realized.

[Structure of Invention]

To achieve the above object, the time-division speech path of the present invention comprises two sets of speech path memories for writing / reading data on an input highway, a counter for controlling a write address of the speech path memory, and the speech path. By using a time switch consisting of a holding memory that stores the read address of the memory, the reading operation is performed in the other channel memory while the writing operation of one channel memory is being performed, and this parallel operation is alternately switched for each frame. In a time-divisional speech path, each set of speech path memories is divided into two, and two data are stored at a certain time tw for the two speech path memories divided into two in one set of the speech path memory. In the meantime, writing is performed in parallel at the same time, and according to the address read from the holding memory, the TW / 2 time is obtained from the two divided channel memories of the other channel memory. By reading at the rate of the data, it is characterized in that so as to replace the two data per tw time.

〔Example〕

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a time division speech path showing an embodiment of the present invention, and FIG. 2 is an operation timing chart of FIG.

The time-division speech path of FIG. 1 shows an example of a case where the speech path memory is divided into four. Reference numerals 21, 22, 23 and 24 are four independent speech path memories, 25 is a holding memory,
26 is a counter, 27, 28 and 29 are channel memory input registers, 30 and 36 are channel memory / address registers, 32 and 37 are address selectors, 31, 34 and 35.
Is an output data selector, 38 is a holding memory input register, and 39 is a holding memory address register. In addition, DI, DO, WE, A in the communication path memory 21-24
Reference numeral D denotes an input / output terminal, which is a data input terminal, a data output terminal, a write enable terminal, and an address input terminal, respectively. Further, DI, DO, WE, AD in the holding memory 25
Input / output terminals are a data input terminal, a data output terminal, a write enable terminal, and an address input terminal, respectively.
Further, IHW is an input data highway, OHW is an output data highway, AHW is a holding memory input highway, and 33 is a speech path memory output register.

The operation will be described in detail with reference to FIGS. 1 and 2. The time division exchange is realized by changing the time order of the time slot data in a frame. According to the present invention, writing and reading are performed by different channel memories.
Writing and reading are simultaneously performed in parallel, and a writing method will be described first.

The data A having the time slot number # 0 transmitted on the input data highway IHW is latched in the communication path memory input register 27 at the rising timing of the first clock in FIG. Next, the input data highway IHW
The data B of the above time slot number # 1 is latched in the speech path memory input register 29 at the rising timing of the second clock, and at the same time, the data A in the speech path memory input register 27 is stored in the speech path memory input register 28. Forward. That is, in the first frame of FIG. 2, A, C, and
The data of E, G, ... And the data of B, D, F ,. The upper (n-1) bit of the output of the counter 26 is selected by the address selector 32 and input to the speech path memory / address register 30. The address selector 32 or 37 is switched for each frame, and the counter 2 is always operated in the writing frame.
Select the upper (n-1) bits of 6. Here, the counter 26 uses a counter that counts with n bits, for example, 3 bits. However, the count value of 3 bits is not sent to the channel memory address registers 30, 36 as it is, and the upper (n-1) bits, That is, in the case of 3 bits, only the upper 2 bits are transmitted, and the change cycle of the address to be transmitted is doubled to operate the address registers 30 and 36 at a 1/2 slower frequency. In FIG. 2, 0, 1, 2, 3, ... Are sequentially set in the speech path memory / address register 30. This channel memory / address register 3
Two channel memory input registers 2 based on the contents of 0
The data latched in 8 and 29 are simultaneously written in parallel to the two channel memories 21 and 22. The write timing is the write enable signal WE in the first frame of FIG.
-1 is performed during the low level. The write enable signal WE-1 has a cycle twice as long as the clock of the time slot, and the write operation to the communication path memories 21 and 22 is performed at a slow speed of 1/2. By a series of these operations, two consecutive data A and B on the input data highway can be written into the address 0 of each of the communication path memories 21 and 22 for 2 time slot time of the input / output highway. Similarly, the time slot number #
Two pieces of data C and D of No. 2 and # 3 are simultaneously written in parallel at address 1 of the channel memories 21 and 22. In this way, of the data of one frame, the data of which the time slot number is even is written in the channel memory 21 and the data of which the odd number is odd are sequentially written in the channel memory 22. That is, as a result, the communication path memory 21 stores A, C, E, G ... And the communication path memory 22 stores B, D, F, H. , 22 stores all input data.

At the frame timing of writing data in the two speech path memories 21 and 22, the other two speech path memories 23 and 24 perform the read operation. Next, the read operation will be described.

As described above, reading and writing are simultaneously performed in parallel in different channel memories.

The n bit output from the counter 26 is input to the holding memory / address register 39. Since the counter 26 used here has one bit more than the count value used for writing to the speech path memories 21 and 22, the timing of the count-up is also twice as fast. K of holding memory 25
Output data highway O at address (K is an arbitrary integer)
The address on the communication path memory of the data to be output to the HW time slot number #K is written. Holding memory
Based on the instruction of the address register 39, the order of the output time slots is read sequentially from the addresses on the channel memory,
The contents of the holding memory 25 are selected by the address selector 37 and input to the speech path memory / address register 36.
Arbitrary 1 bit of address set in this channel memory / address register 36 (usually lower 1 bit)
Is sent to the selector 35 as a selection signal for the two speech path memories 23 and 24 (the transfer path is shown by a wavy line), and based on the remaining contents in the speech path memory / address register 36, 2
The data of the same address is read from the one channel memory 23, 24. Of the two data, the required one is selected by the selector 35, and after passing through the selector 34,
It is input to the speech path memory output register 33 and sent to the output data highway OHW. That is, at the time of writing, for example, A and B that arrived at input time slots # 0 and # 1
Is written in address # 0 of each of the call path memories 21 and 22. If it is desired to output A at the time of reading, it reads # 0 in both channel memories, controls the selector 31, and outputs only A.

As shown in FIG. 2, in the next second frame, contrary to the first frame, the upper two speech path memories 21, 2 are
The data written in the first frame is read out in 2 and the data of the second frame is written in the lower two speech path memories 23 and 24. In the second frame, the address addresses A (0), A (1), A (2), ... Which are updated by n-bit counter output are input to the speech path memory / address register 30, and one speech path is input. Memory address register 36
The address addresses 0, 1, 2, 3, ..., Which are updated by the (n-1) bit counter output are input to. By designating the read address in the holding memory, time-division exchange connection on the data highway becomes possible.

An example of the actual exchange operation will be described with reference to FIG. Arrival data A, B, C, D, E, F, G, H, I, J ...
Is an example in which E, D, A, B, B, F, C, ... Are exchange-connected.

In the first frame, the arrival data A, B, C, D ... Are written in the corresponding channel memories 21 and 22, respectively. As described above, the channel memory 21 has an even number of time slots, that is, # 0, # 2, # 4, # 6, ...
Write time slot data A, C, E, G in the channel memory 22 with odd time slots, that is, # 1, # 3, # 5, # 7, ... Time slot data. Write some B, D, F, H, ...

The data arrived and written in the first frame is read in the second frame. The holding memory 25 stores the address # 4 and the second address of the data exchanged and output in the first time slot.
Address of data to be exchanged and output in each time slot #
3 etc. are written in order. That is, in the holding memory, for example, # 4, # 3, # 0, # 1, # 1, # 5, #
2 are sequentially written, and are sequentially read by the counter 26 and the address RG 39 at a speed twice as fast as writing, and the communication path memory and the address register (SADR) 3
Written to zero. Here, in the binary representation (100) of # 4 read in the first time slot, the upper 2 bits 10
Is a storage address on the channel memory, and the lower 1 bit controls the selector 31 to select the channel memory, that is, at 100, E is read from the channel memory 21 and F is read from the channel memory 22. , The lower 1 bit transfers only E to the output HW. Similarly, in the second time slot, it is read at # 3 (011) and the channel memory 2
C is read from 1 and D is read from the speech path memory 22, the speech path memory 22 is selected by the lower bit 1, and D is output. Data A, B, C, D, E, F, G arriving in this way
It is understood that ... Is output in time-division exchange with E, D, A, B, B, and F.

In the present invention, all the actual arrival data are read with a delay of one frame.

In the writing accompanying the change in the contents of the holding memory 25, the exchange of a time slot having one frame is stopped and the latch data is written in the holding memory input register 38.

As described above, in this embodiment, the writing time can be doubled as compared with the conventional communication path shown in FIG. 3, and accordingly, the writing time margin can be increased. Further, when the memory having the same operation speed is used, the replaceable throughput can be doubled.
As a result, it is possible to secure a timing margin for data and a write enable pulse when a communication path is formed by using an ultra-high-speed RAM that has a longer write cycle time than the read cycle time.

〔The invention's effect〕

As described above, according to the present invention, a plurality of data are simultaneously written in parallel and the same number of data are read in series at the same time. Therefore, the write cycle that has been a conventional speed-up network is Apparently, the read cycle time can be taken longer, and the operation speed of the time division communication path can be increased to the limit limited by the read cycle time.

[Brief description of drawings]

FIG. 1 is a block diagram of a time division speech path showing an embodiment of the present invention, FIG. 2 is an operation time chart of FIG. 1, FIG. 3 is a construction diagram of a conventional time division speech path, and FIG. 3 is an operation timing chart of FIG. FIG. 5 is an operation time chart for explaining the time division exchange of FIG. 1, 2, 21 to 24: channel memory, 3, 25: holding memory, 4, 26: counter, 5, 12, 27 to 29, 3
8: Input register, 6, 8, 13, 30, 36, 39:
Address register, 7, 33: Output register, 9 to 1
1, 31, 32, 34, 35, 37: selector, IH
W: input data highway, OHW: output data highway, AHW: holding memory input highway.

Front page continued (72) Inventor Hiroshi Miyanaga 1839, Ono, Atsugi, Kanagawa Pref., Atsugi Telecommunications Research Institute, Nippon Telegraph and Telephone Corporation (72) Masao Suzuki, 1839, Ono, Atsugi, Kanagawa Pref. In the laboratory

Claims (1)

[Claims] 1. A set of two channel memories for writing / reading data on an input highway, a counter for controlling a write address of the channel memory, and a holding memory for storing a read address of the channel memory. By using the time switch, the reading operation is performed in the other channel memory while the writing operation in one channel memory is performed, and the parallel operation is
In the time-sharing speech path that switches alternately for each frame,
Each set of speech path memories is divided into two, and two pieces of data are simultaneously written in parallel in a certain time tw to the two divided speech path memories of one of the pairs of the speech path memories. In addition, by the address read out from the holding memory, the data is read out from the two divided channel memories of the other set of channel memories at a rate of 1 data per tw / 2 hours. A time division speech path characterized by exchanging two data.