JPH0654862B2 - Waveform signal generation circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a waveform signal generation circuit using an up / down counter.

[Prior Art] As shown in FIG. 7, a conventional waveform signal generating circuit includes a clock signal generating circuit 1, an up / down counter 2, and a D / D counter.
A / A converter 3 in combination. According to this circuit, the digital waveform signal corresponding to the counting of the clock signal is obtained from the up / down counter 2, and the D / A converter 3
An analog waveform signal is obtained from.

By the way, with the period (frequency) of the waveform kept constant, the up-count operation period Ta and the down-count operation period Tb
Multiple types of waveforms with different ratios may be required. In order to meet this type of request, there is known a system in which a clock switching circuit 4 is provided between the clock signal generating circuit 1 and the up / down counter 2 as shown in FIG. The clock switching circuit 4 of this system is the clock signal generating circuit 1
And a decimal counter 5 for 1/10 frequency division, which is also connected to 1/4 frequency division and 1/16 frequency division, which are also connected to the clock signal generation circuit 1.
It consists of a hexadecimal counter 6 for frequency division and a clock signal selection circuit 7 for selecting the outputs of these. When the ratio of the up-counting operation period Ta to the cycle Ta + Tb of the waveform signal is defined as duty and the waveform signal with a duty of 20% is obtained by the circuit of FIG. 8, the clock signal selection circuit 7 is obtained from the up / down counter 2. It is controlled by an up / down (U / D) signal. Clock signal selection circuit 7
Responds to the up / down (U / D) signal obtained from the up / down counter 2 by 1 / during the up-count operation.
4 divided output is given to up / down counter 2, and 1/16 divided output is up / down counter 2 during down count operation.
Give to. As a result, a waveform signal with a duty of 20% is obtained from the up / down counter 2.

On the other hand, when obtaining a waveform signal with a duty of 50%, a signal indicating this is applied to the clock signal selection circuit 7 from the 50% operation instruction line 8 and the output of the decimal counter 5 is sent to the up / down counter 2. At this time, the same 1/10 frequency division signal is given to the up / down counter 2 in both the up-count operation period Ta and the down-count operation period Tb.

[Problems to be Solved by the Invention] By the way, in the system of FIG. 8, only two kinds of duties can be obtained, and many duties cannot be obtained, although the circuit configuration is complicated.

Therefore, it is an object of the present invention to provide a waveform signal generation circuit that can easily obtain a plurality of waveform signals having different cycles but the same cycle (frequency).

[Means for Solving the Problems] The present invention for achieving the above object is directed to an up-down counter input pulse generation circuit and a predetermined number after up-counting a predetermined number of pulses generated from the up-down counter input pulse generation circuit. In a waveform signal generation circuit including an up-down counter that counts down by a number and generates a waveform signal, the up-down counter input pulse generation circuit includes a clock pulse generation circuit and a clock pulse obtained from the clock pulse generation circuit. Incorporated in the up-down counter, a counter for counting the number of pulses, a duty-instruction-signal generating circuit for generating a duty-instruction signal indicating a ratio (duty) of an up-counting operation period to the cycle of the waveform signal obtained from the up-down counter. Or independently An up-down signal generating means for generating an up-down signal for distinguishing between an up-counting operation and a down-counting operation of the up-down counter, based on the duty instruction signal and the up-down signal The memory contents are output to obtain a desired waveform signal, and the memory contents are:
Duty instruction values for up-count operation of a plurality of stages are written corresponding to a signal indicating an up-count operation of the up-down signal and a value of the duty instruction signal in a plurality of steps, and the down-count of the up-down signal is performed. 10 indicating 100% duty corresponding to the signal indicating the operation and the values of the plurality of levels of the duty instruction signal
A memory in which a duty-instruction value for down-count operation, which is a value obtained by subtracting the duty-instruction value for up-count operation from 0 duty value, is written, and an output value of the counter and for up-count operation read from the memory. And a duty count value for down-count operation, and a comparator that clears the counter when both match, and a specific value obtained from the counter in synchronization with the clearing of the counter or the coincidence output of the comparator And an input means of the up / down counter for giving as the count input of the up / down counter.

[Operation] According to the above invention, the cycle of the input pulse of the up / down counter can be changed by changing the clearing point of the counter. Two kinds of values (data) are written in the memory in correspondence with a certain duty instruction signal. That is, a value (up data) indicating a target duty is written corresponding to a certain duty instruction signal and a signal indicating the up-count operation, and also corresponds to a certain duty instruction signal and a signal indicating the down-count operation. Then, a value (down data) indicating a value obtained by subtracting the target duty value from 100% duty is written. The memory outputs the up data during the up count operation period and outputs the down data during the down operation period. The comparator compares the output of the counter with the memory output and produces a coincidence output when both signals coincide. When the values of the up data and the down data are different, the cycle of the coincidence output pulse obtained from the comparator is also different. Since the sum of the up data and the down data is always constant, the cycle of the waveform signal obtained from the up / down counter does not change even if the duty instruction signal is changed.

[Embodiment] Next, a waveform signal generating circuit according to an embodiment of the present invention will be described with reference to FIGS.

As shown in FIG. 1, this waveform signal generating circuit includes an up / down counter input pulse generating circuit 11, an up / down counter 12, and a D / A converter 13. The up-down counter 12 repeats counting up to N counts (500 counts in this embodiment) and then down-counting to N counts (500 counts). Also, the up / down counter 12
Incorporates an up-down (U / D) signal generation circuit showing the up-counting operation period Ta and the down-counting operation period Tb, and outputs it to the line 14.

The up / down counter input pulse generation circuit 11 includes a clock pulse generation circuit 15, a counter 16, a duty instruction signal generation circuit 17, a ROM (read only memory) 18, a digital comparator 19, and an up / down counter 12. And a gate circuit 20 as an input means. The clock pulse generation circuit 15 generates a clock pulse having a constant period T shown in FIGS. 3, 4, and 5 (A). Since the input terminal a of the counter 16 is connected to the clock pulse generation circuit 15, the counter 1
Reference numeral 6 counts the clock pulses shown in FIGS. 3 to 5 (A) to generate the outputs shown in FIGS. 3 to 5 (B) (C) (D) at the output terminal b. The duty instruction signal generation circuit 17
A 4-bit signal consisting of A0 to A3 is converted to A3, A in FIG.
2, as shown in columns A1, A0. The duty instruction signals A0 to A3 serve as the address signal of the ROM 18 together with the up / down signal indicated by A4 in FIG.

The duty instruction signal generation circuit 17 and the up / down signal line 14 are connected. The ROM has a large number of addresses corresponding to the address signals, and values (data) corresponding to the contents shown in the memory contents column of FIG. 2 are written in each address. In the duty column of FIG. 2, the duty indicated by the duty instruction signal (A0 to A3) is shown in percentage. Also, the second
The X mark in the figure indicates that the content is unknown because it is not used.

By the way, as is clear from the relationship between the address signals A0 to A4 and the memory contents in FIG. 2, when the bit A4 is 0 due to the up-counting operation period Ta, as the duty instruction signals A0 to A3 increase. , The memory content is also increasing between 1 and 9. On the other hand, when the bit A4 is 1 due to the down-count operation period Tb, the memory content decreases between 9 and 1 as the duty instruction signals A0 to A3 increase. The sum of the memory content corresponding to a certain duty instruction signal during the up-counting operation period and the memory content corresponding to a duty instruction signal during the down-counting operation period is always 10. Therefore, the memory content corresponding to a certain duty instruction signal during the up-count operation period is up duty data, and the memory content corresponding to a certain duty instruction signal during the down-count operation period is for up-shifting from a 100% duty value. It is down duty data corresponding to a value obtained by subtracting the duty value.

One input terminal d of the comparator 19 is connected to the output terminal of the ROM 18, the other input terminal e is connected to the output terminal b of the counter 16, and the comparison output terminal f is connected to the clear terminal c of the counter 16. .

One input terminal of the gate circuit 20 is connected to the output terminal b of the counter 16, the other input terminal is connected to the clock pulse generation circuit 15, and the output terminal is connected to the count input terminal of the up / down counter 12.

[Operation] [0101] is converted to R from the duty instruction signal generation circuit 17 as the duty instruction signals [A3, A2, A1, A0].
It is given to OM18 and up / down signal A is sent to ROM18.
Assuming that 0 is inputted as 4 to instruct the up-counting operation, the memory content 5 written in the address corresponding to [00101] in FIG. 2 is read out. This memory content 5 is of course output as a digital value and input to the comparator 19. The counter 16 counts the clock pulses shown in FIG. 3 (A) and generates the outputs shown in FIGS. 3 (B) (C) (D). Counter 1 at time t1 in FIG.
When the output of 6 becomes the value corresponding to the decimal number 5, ROM
Since the output of 18 coincides with the output of the comparator 18, the coincidence output shown in FIG. 3 (E) is generated from the comparator 19, the counter 16 is cleared, the output of the counter 16 returns to zero, and counting is started again. Since gate circuit 20 is an OR gate, it produces a low level output only when all inputs are low. That is, when the clock pulse in FIG. 3 (A) becomes low level while the output of the counter 16 is zero, the low level output pulse is gated as shown in the period t2 to t3 in FIG. 3 (F). Obtained from circuit 20. This makes the third
The clock pal in Fig. (A) is divided into 1/5, and Fig. 3 (F)
Low frequency clock pulse of up-down counter 12
Given to. Since the up-down counter 12 is configured to repeat the up-count operation of 500 counts and then the down-count operation of 500 counts, the up-down counter 12 operates at a low frequency clock of 500 counts as shown in FIG. 3 (F).
Up operation is performed up to the count, and the waveform signal shown in the up count operation period Ta of FIG. 6 (A) is obtained. When the up-down counter 12 counts 500 and then shifts to the down-count operation, a 1 indicating down is obtained on the line 14, the addressing of the ROM 18 is changed to [10101], and the memory contents 5 as shown in FIG. Is read. Since this memory content (down duty data) has the same value as the up duty data up to now, the up / down counter 12 is driven by a clock pulse of a low frequency divided by 1/5, and FIG. A waveform signal shown in the down count period Tb of A) is generated. If the period of the clock pulse shown in FIG.
The up-count period Ta in FIG. 6A is 5T × 500.
And the down count period Tb is also 5T × 500.
And one cycle is 5000T.

When the duty instruction signal [A3 A2 A1 A0] is set to [0011] for instructing the duty of 30% and the up / down signal is 0 indicating up, the memory content 3 is output from the ROM 18, and as shown in FIG. At time t1 when the counter 16 counts three times, a coincidence output is generated from the comparator 19 as shown in FIG. 4 (E), and is divided into 1/3 at t2 to t3 as shown in FIG. 4 (F). The generated clock pulse is obtained from the gate circuit 20, and the up / down counter 12 is driven by this clock pulse to output the waveform signal shown in FIG. 6 (B) during the up-counting operation period Ta. When the up / down signal becomes 1 indicating down count, the memory content 7 is read from the address [A4 A3 A2 A1 A0] = [10011], and the counter 16 reads 7
At the time of counting, the comparator 19 produces the coincidence output shown at time t1 in FIG. 5 (E), the counter 16 is cleared, and the 1/7 frequency division pulse is generated in the period from t2 to t3 in FIG. 5 (F). Then, it becomes the input of the up / down counter 12, and the sixth
The waveform signal shown in the down count operation period Tb of FIG. The up-count operation period T of FIG. 6 (B)
a is 3T × 500, and the down count operation period is 7
T × 500, and the total time (one cycle) is FIG. 6 (A)
It is the same as 5000T.

The cycle of the waveform signal obtained from the up / down counter 12 and the D / A converter 13 does not change even if various duties set at 10% intervals in FIG. 2 are selected.

[Modification] The present invention is not limited to the above-described embodiments, and the following modifications are possible, for example.

(1) The memory contents of the ROM 18 can be set to 1% intervals or various intervals such as 1 to 99 corresponding to the up-counting operation and 99 to 1 corresponding to the down-counting operation.

(2) FIG. 3 to FIG. 5 (E) obtained from the comparator 19.
The coincidence output pulse shown in, or the pulse width expansion and / or delay pulse thereof may be input to the up / down counter 12.

(3) In this embodiment, the up / down signal is obtained from the up / down counter 12, but an independent up / down signal generating circuit may be provided in association with the up / down counter 12.

(4) In order to change the cycle of the waveform signal, the cycle of the output clock pulse of the clock pulse generation circuit 15 may be changed.

EFFECTS OF THE INVENTION As described above, according to the present invention, the duty value can be easily changed, and the cycle of the waveform signal can be kept constant regardless of the change of the duty value.

[Brief description of drawings]

FIG. 1 is a block diagram showing a waveform signal generating circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing a relationship between an address input of a ROM shown in FIG. 1, a designated duty value and a memory content, and FIG. A of FIG. 1 when the duty is 50%
FIG. 4 is a waveform diagram showing the state of point F, FIG. 4 is a waveform diagram showing the state of points A to F in FIG. 1 during the up-counting operation period when the duty is 30%, and FIG. FIG. 6 (B) is a voltage waveform diagram showing the states of points A to F in FIG. 1 during the down-counting operation period, FIG. 6 (A) is a diagram showing waveform signals at a duty of 50%, and FIG. 6 (B) is FIG. 7 is an explanatory diagram showing a waveform signal having a duty of 30%, FIG. 7 is a block diagram showing a conventional waveform signal generating circuit, and FIG. 8 is a block diagram showing another conventional waveform signal generating circuit. 11 ... Up-down counter input pulse generation circuit, 1
2 ... Up-down counter, 13 ... D / A converter,
15 ... Clock pulse generation circuit, 16 ... Counter,
17 ... Duty instruction signal generating circuit, 18 ... RO
M, 19 ... Comparator, 20 ... Gate circuit.

Claims (1)

[Claims] 1. An up-down counter input pulse generating circuit, and an up-down counter which up-counts a predetermined number of pulses generated from the up-down counter input-pulse generating circuit and then down-counts by a predetermined number to generate a waveform signal. In the waveform signal generating circuit consisting of
The up-down counter input pulse generation circuit includes a clock pulse generation circuit, a counter that counts clock pulses obtained from the clock pulse generation circuit, and an up-count operation period for the cycle of the waveform signal obtained from the up-down counter. A duty instruction signal generating circuit for generating a duty instruction signal indicating the ratio (duty) of the duty cycle, and an up-counting operation of the up-down counter, which is built in the up-down counter or provided independently. Up-down signal generating means for generating an up-down signal for distinguishing from a down-count operation, and addressing based on the duty instruction signal and the up-down signal, and outputting memory contents for obtaining a desired waveform signal The above-mentioned As contents, the duty instruction value for up-count operation of a plurality of stages is written corresponding to the signal indicating the up-count operation of the up-down signal and the value of a plurality of steps of the duty instruction signal, and the up-down operation is performed. A down count consisting of a value obtained by subtracting the duty instruction value for up-count operation from a 100% duty value showing a duty of 100% corresponding to a signal indicating a down count operation of a signal and a value of a plurality of stages of the duty instruction signal. A memory in which an operation duty instruction value is written is compared with the output value of the counter and the up-counting operation and down-counting operation duty instruction values read from the memory, and when the two coincide, the counter And a comparator that clears the counter and the counter synchronized with the clearing of the counter. Waveform signal generating circuit, characterized by comprising a specific value or a coincidence output of the comparator resulting from pointer from the up-down counter input means for providing a count input of the up-down counter.