JPH0654886B2 - Line characteristics measurement method - Google Patents
Line characteristics measurement methodInfo
- Publication number
- JPH0654886B2 JPH0654886B2 JP25032685A JP25032685A JPH0654886B2 JP H0654886 B2 JPH0654886 B2 JP H0654886B2 JP 25032685 A JP25032685 A JP 25032685A JP 25032685 A JP25032685 A JP 25032685A JP H0654886 B2 JPH0654886 B2 JP H0654886B2
- Authority
- JP
- Japan
- Prior art keywords
- line
- voltage
- circuit
- lines
- pair
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Locating Faults (AREA)
- Monitoring And Testing Of Exchanges (AREA)
- Monitoring And Testing Of Transmission In General (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は任意の入力インピーダンスを有する装置が接
続された線路を、その装置が接続された状態で、その装
置の影響を受けることなく、線路の特性を正確に測定す
る線路特性測定方法に関するものである。Description: TECHNICAL FIELD The present invention relates to a line to which a device having an arbitrary input impedance is connected, the line being connected to the device without being affected by the device. The present invention relates to a line characteristic measuring method for accurately measuring the characteristics of the.
たとえば、電話線の障害検出のためには、従来より線路
の絶縁抵抗、静電容量等の測定が行われているが、これ
らの測定は、測定回路の構成が簡易であることから直流
測定で行われている。任意の直流入力インピーダンスを
有する装置が線路に接続された場合の等価回路を第7図
に示す。一対の線路11の一端間に入力抵抗Riの装置
12が接続され、他端間に直流電源13が接続されてい
る。一対の線路11間の絶縁抵抗Rx(以下単に線路の
絶縁抵抗Rxと記す)が入力抵抗Riと並列に接続され
た状態になる。直流電源13の端子14,15から線路
11の絶縁抵抗Rxの測定を行う場合、測定結果は装置
の入力抵抗Riの影響を受け、RxとRiの並列接続抵
抗値Rx・Ri/(Rx+Ri)となる。従って線路1
1の絶縁抵抗Rxからの誤差は、−Rx 2/(Rx+
Ri)となり、装置12の入力抵抗Riが小さくなると
誤差が大きくなり、正確な測定ができないという問題が
あった。For example, in order to detect faults in telephone lines, line insulation resistance, capacitance, etc. have been conventionally measured, but these measurements can be performed by direct current measurement because the measurement circuit configuration is simple. Has been done. FIG. 7 shows an equivalent circuit when a device having an arbitrary DC input impedance is connected to the line. The device 12 having the input resistance R i is connected between one ends of the pair of lines 11, and the DC power supply 13 is connected between the other ends. The insulation resistance R x between the pair of lines 11 (hereinafter simply referred to as line insulation resistance R x ) is connected in parallel with the input resistance R i . When measuring the insulation resistance R x of the line 11 from the terminals 14 and 15 of the DC power supply 13, the measurement result is affected by the input resistance R i of the device, and the resistance value R x · R of the parallel connection of R x and R i is i / (R x + R i ). Therefore line 1
The error from the insulation resistance R x of 1 is −R x 2 / (R x +
R i ), and when the input resistance R i of the device 12 decreases, the error increases and there is a problem that accurate measurement cannot be performed.
この発明は、線路特性測定時には、前記任意の入力イン
ピーダンスを有する装置を線路に機械的には接続したま
まであるが、電気的に線路から切り離すように構成し、
正確な線路特性測定を可能にしたものである。The present invention, when measuring the line characteristics, the device having the arbitrary input impedance is mechanically connected to the line, but is configured to be electrically disconnected from the line,
This enables accurate line characteristic measurement.
この発明においては、通常の使用状態で線路に印加され
る電圧Voでは導通するが、Voよりも小さい所定電圧
VM以下では遮断する回路を、一対の線路と任意の入力
インピーダンスを有する装置との各間に挿入しておき、
線路特性測定時には、線路に前記所定電圧VM以下の電
圧を線路に印加して線路の特性を測定する。In the present invention, will be conducting in the voltage V o is applied to the line in normal use, the circuit for blocking a lower than the predetermined voltage V M than V o, devices having any of the input impedance and a pair of lines Insert it between each and
At the time of measuring the line characteristic, the line characteristic is measured by applying a voltage equal to or lower than the predetermined voltage V M to the line.
第1図はこの発明の原理を説明する図であって、第7図
と対応する部分に同一符号を付けてある。任意の入力イ
ンピーダンスRiを有する装置12と線路11との間
に、一対の線路11の装置12側端の印加電圧Viによ
り抵抗Rzが変化する回路16を挿入する。この抵抗R
zが変化する回路16の理想特性を第2図に示す。通常
は線路11にVoの電圧が印加され、前記装置12に給
電が行われるが、このとき抵抗が変化する回路16の抵
抗RzはO(Ω)、すなわち導通状態であり、給電作用
に何ら影響を与えない。また、一般に前記印加電圧Vo
の逆極性の電圧は、電話線の場合、着呼信号等に利用さ
れるが、この場合も回路16の抵抗RzはO(Ω)であ
るため影響はない。FIG. 1 is a diagram for explaining the principle of the present invention, in which parts corresponding to those in FIG. 7 are designated by the same reference numerals. Between the device 12 having an arbitrary input impedance R i and the line 11, a circuit 16 in which the resistance R z changes according to the applied voltage V i at the end of the pair of lines 11 on the device 12 side is inserted. This resistance R
The ideal characteristic of the circuit 16 in which z changes is shown in FIG. Normally the voltage V o is applied to the line 11, but power the device 12 is performed, the resistance R z of the circuit 16 whose resistance varies this time O (Omega), i.e. a conductive state, the power feeding action It has no effect. In general the applied voltage V o
In the case of a telephone line, the voltage of the opposite polarity is used for an incoming call signal or the like, but in this case as well, the resistance R z of the circuit 16 is O (Ω), and therefore has no effect.
さて、前記電圧Voより小さい電圧VMが線路11に印
加された場合、前記回路16の抵抗Rzは∞(Ω)、す
なわち遮断状態となる。従って端子14,15からは、
前記装置12の入力インピーダンスRiは観測されなく
なり、線路11の絶縁抵抗Rxが正確に測定できること
となる。Now, when a voltage V M smaller than the voltage V o is applied to the line 11, the resistance R z of the circuit 16 is ∞ (Ω), that is, a cutoff state. Therefore, from terminals 14 and 15,
The input impedance R i of the device 12 is no longer observed, and the insulation resistance R x of the line 11 can be measured accurately.
第3図は、回路16の具体的な実現例の1つであり、前
記印加電圧Viにより抵抗Rzが変化する回路16をツ
ェナーダイオードZDで構成した例である。ここで通常
端子14に正極性、端子15に負極性の電圧が印加さ
れ、ツェナーダイオードZDのカソードが端子14側と
されているものとする。ツェナーダイオードZDのツェ
ナー電圧を前記VMに設定すれば、実用上第2図に示し
た特性が実現できる。FIG. 3 is one of the concrete implementation examples of the circuit 16, and is an example in which the circuit 16 in which the resistance R z is changed by the applied voltage V i is configured by the Zener diode Z D. Here, it is assumed that a voltage having a positive polarity is normally applied to the terminal 14 and a voltage having a negative polarity is applied to the terminal 15, and the cathode of the Zener diode Z D is on the terminal 14 side. By setting the Zener voltage of the Zener diode Z D into the V M, practical characteristics shown in Figure 2 can be realized.
第4図は回路16の他の実現例であり、前記回路16と
して、ダイオード17、エンハンスメント形FET18
の並列回路を線路11と直列に接続し、その線路側接続
点にツェナーダイオード19、抵抗器20を介して線路
11に対してシャントに接続し、ツェナーダイオード1
9及び抵抗器20の接続点をFET18のゲートに接続
したものである。通常は端子14,15間にツェナーダ
イオード19のツェナー電圧以上の電圧Voが印加さ
れ、ツェナーダイオード19が導通し、この導通電流が
抵抗器20に流れ、その抵抗器20における電圧降下が
FET18のゲートに印加され、これによりFET18
はオン状態になる。しかし線路特性測定時には端子1
4,15間にツェナーダイオード19のツェナー電圧以
下の測定電圧が印加され、ツェナーダイオード19は不
導通になり、抵抗器20に電流が流れず、FET18の
ゲート、ソース間が同一電位となり、このFET18は
エンハンスメント形であるためオフ状態になり、装置1
2側が電気的に切離される。FIG. 4 shows another implementation example of the circuit 16. As the circuit 16, a diode 17 and an enhancement type FET 18 are used.
Is connected in series with the line 11, and a shunt is connected to the line 11 via a Zener diode 19 and a resistor 20 at the line side connection point.
The connection point of 9 and the resistor 20 is connected to the gate of the FET 18. Normally a Zener voltage higher than the voltage V o of the Zener diode 19 is applied between terminals 14 and 15, the Zener diode 19 is rendered conductive, the conduction current flows through the resistor 20, the voltage drop across the resistor 20 is FET18 Applied to the gate, which causes the FET 18
Turns on. However, when measuring line characteristics, terminal 1
A measurement voltage equal to or lower than the Zener voltage of the Zener diode 19 is applied between 4 and 15, the Zener diode 19 becomes non-conductive, no current flows through the resistor 20, and the gate and the source of the FET 18 have the same potential. Is in the off state because it is an enhancement type and the device 1
The two sides are electrically separated.
この例では第3図の構成に比べてツェナーダイオード1
9として容量の小さいものが適用できる特徴がある。In this example, the Zener diode 1 is different from the configuration shown in FIG.
9 has a feature that a small capacity can be applied.
第5図、第6図に、それぞれこの発明の実施例を示す。
一対の線路11と装置12との間にそれぞれ回路16を
挿入して平衡形式にする。第5図、第6図はそれぞれ装
置12の両端と線路11との間のそれぞれに、第3図、
第4図中の回路16が挿入され、一対の線路11の対地
インピーダンスが等しくなり、対地不平衡減衰量を確保
できる特徴がある。第6図においてFET18,18′
は導電形が逆のものが用いられ、同時にオン又はオフと
される。5 and 6 show embodiments of the present invention.
A circuit 16 is inserted between each of the pair of lines 11 and the device 12 to form a balanced type. 5 and 6 are respectively shown between both ends of the device 12 and the line 11, FIG.
The circuit 16 shown in FIG. 4 is inserted, and the ground impedances of the pair of lines 11 become equal to each other, so that it is possible to secure an unbalanced ground attenuation amount. In FIG. 6, FETs 18 and 18 '
Has the opposite conductivity type and is turned on or off at the same time.
以上説明したように、この発明によれば通常の印加電圧
Voより小さい電圧VM以下の電圧で線路特性測定を行
うことにより、任意の入力インピーダンスを有する装置
を機械的に接続したままで電気的に線路から切り離すこ
とが可能であるため、線路特性の正確な測定ができる利
点がある。しかも、平衡形式としているため、対地減衰
量が確保でき、広帯域なディジタル信号伝送システムに
適用してディジタル信号の波形伝送に影響を与えない。As described above, according to the present invention, the line characteristic measurement is performed at the voltage V M which is lower than the normal applied voltage V o , so that the device having an arbitrary input impedance can be electrically connected while being mechanically connected. Since it can be disconnected from the line, there is an advantage that the line characteristics can be accurately measured. Moreover, since it is of the balanced type, it is possible to secure the amount of attenuation to the ground, and it is applied to a wideband digital signal transmission system and does not affect the waveform transmission of the digital signal.
ここでは通信線路の測定を例として説明したが、この発
明は、電力線や他の各種線路の特性測定にも当然適用可
能である。Although the measurement of the communication line has been described here as an example, the present invention is naturally applicable to the characteristic measurement of the power line and other various lines.
第1図はこの発明の原理を示す回路図、第2図は印加電
圧Viにより抵抗Rzが変化する回路16の理想特性を
示す図、第3図は第1図中の回路16の実現例の1つを
示す回路図、第4図は第1図中の回路16の他の実現例
を示す回路図、第5図は第3図の実施例を平衡形式にし
た例を示す図、第6図は第4図の実施例を平衡形式にし
た例を示す図、第7図は任意の直流入力インピーダンス
を有する装置が線路に接続されたときの等価回路図であ
る。 11:線路、12:任意の入力インピーダンスRiを有
する装置、13:直流電源、16:印加電圧Viにより
抵抗Rzが変化する回路。FIG. 1 is a circuit diagram showing the principle of the present invention, FIG. 2 is a diagram showing ideal characteristics of a circuit 16 in which a resistance R z is changed by an applied voltage V i, and FIG. 3 is a realization of the circuit 16 in FIG. FIG. 4 is a circuit diagram showing one example, FIG. 4 is a circuit diagram showing another implementation example of the circuit 16 in FIG. 1, and FIG. 5 is a diagram showing an example in which the embodiment of FIG. FIG. 6 is a diagram showing an example in which the embodiment of FIG. 4 is made into a balanced form, and FIG. 7 is an equivalent circuit diagram when a device having an arbitrary DC input impedance is connected to a line. 11: line, 12: device having arbitrary input impedance R i , 13: direct current power supply, 16: circuit in which resistance R z changes according to applied voltage V i .
Claims (1)
ダンスを有する装置が接続され、前記一対の線路の他端
間に直流電源が接続され、その直流電源から前記一対の
線路間に通常はVoの電圧が印加されている伝送系にお
いて、 前記一対の線路と、前記任意の入力インピーダンスを有
する装置との間に、それぞれ前記直流電源からの通常の
印加電圧Voでは導通し、その印加電圧Voより小さい
所定の電圧VM以下では遮断する回路を挿入しておき、 線路特性測定時に前記電圧VM以下の電圧を前記一対の
線路間に印加して線路特性測定を行うことを特徴とする
線路特性測定方法。1. A device having an arbitrary input impedance is connected between one ends of a pair of lines, a DC power source is connected between the other ends of the pair of lines, and a normal power source is connected between the DC power source and the pair of lines. in the transmission system voltage V o is applied, the pair of lines, between the device having the arbitrary input impedance, conducting the normal applied voltage V o from each said DC power source, the applied A circuit for cutting off at a predetermined voltage V M or less smaller than the voltage V o is inserted, and a line characteristic measurement is performed by applying a voltage of the voltage V M or less between the pair of lines when measuring the line characteristic. Measuring method for line characteristics.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25032685A JPH0654886B2 (en) | 1985-11-08 | 1985-11-08 | Line characteristics measurement method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25032685A JPH0654886B2 (en) | 1985-11-08 | 1985-11-08 | Line characteristics measurement method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62110169A JPS62110169A (en) | 1987-05-21 |
| JPH0654886B2 true JPH0654886B2 (en) | 1994-07-20 |
Family
ID=17206244
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25032685A Expired - Lifetime JPH0654886B2 (en) | 1985-11-08 | 1985-11-08 | Line characteristics measurement method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0654886B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0633722Y2 (en) * | 1990-06-29 | 1994-08-31 | 株式会社白山製作所 | Remote carving device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60107967A (en) * | 1983-11-17 | 1985-06-13 | Nippon Telegr & Teleph Corp <Ntt> | Analog switch circuit |
-
1985
- 1985-11-08 JP JP25032685A patent/JPH0654886B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62110169A (en) | 1987-05-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |