JPH0654986B2 - Vertical center-position adjustment circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described below in the following order.

A. Industrial application fields B. SUMMARY OF THE INVENTION C. Conventional Technology D. Problems to be Solved by the Invention E. Means for Solving Problems F. Action G. Example G-1. Configuration of the present embodiment (FIGS. 3 and 4) G-2. Configuration of Vertical Center Position Adjusting Circuit (FIG. 1) G-3. Operation of Vertical Center Position Adjusting Circuit (FIGS. 1 and 2) Effect of Invention A. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical center position adjusting circuit of a picture tube used in a color television receiver or the like.

B. SUMMARY OF THE INVENTION The present invention automatically adjusts the position of a vertical center by controlling the current of a vertical deflection coil based on an index signal obtained by beam scanning from a beam position detecting means arranged inside a picture tube. It is a thing.

C. 2. Description of the Related Art Generally, in a color television receiver, the screen size may be slightly affected by fluctuations in the high voltage of the picture tube due to changes in luminance, and the raster may be affected by geomagnetism or the like. Therefore, these corrections are necessary, and for example, corrections of the vertical center, vertical amplitude, horizontal center, horizontal amplitude, etc. are performed.

The applicant has previously filed a vertical center position adjusting circuit for correcting the vertical center as one of the corrections (Japanese Patent Application No. 56-83023).

In the beam index type color television receiver, the above-mentioned correction is generally performed by using an index signal obtained from the index stripe.

For example, as shown in FIG. 5, an effective screen 5a is provided inside the picture tube.
From the signals detected by the index stripes 5b arranged in a wider range, the pulse signal S at the starting point of each horizontal scan
Get IH. This signal SIH is a vertical sync pulse VBLK.
The first pulse is generated after the time t _{1 at} which the horizontal scanning starts, and the pulse is generated at every horizontal period th during the time t ₂ after which the horizontal scanning ends. Further, no pulse is generated at time t ₃ from the end of horizontal scanning to the next vertical period pulse.

The vertical center is adjusted by detecting the time t ₁ and controlling it to reach a predetermined value, or by detecting the sum of the times t ₁ and t ₂ and controlling it to reach a predetermined value. It is done by Similarly, the vertical amplitude is adjusted at the same time using these times t ₁ or t ₂ .

D. Problems to be Solved by the Invention As described above, the time t ₁ from the vertical synchronization pulse VBLK to the start of horizontal scanning, the time t ₂ when horizontal scanning is performed, or the like is detected, and these are set to predetermined values. In the case of control, the times t ₁ , t _2, etc. are changed by the fluctuation of the vertical amplitude and the fluctuation of the vertical center position. For example, when the vertical amplitude changes due to a change in the high voltage of the picture tube, the vertical center position adjusting circuit operates even if the vertical centers match. Further, when the vertical center position adjustment and the vertical amplitude adjustment are performed at the same time, there is a problem that the operation of each circuit influences each other and the stability of control deteriorates.

An object of the present invention is to provide a vertical center position adjusting circuit which solves such a problem and has improved stability.

E. Means for Solving the Problems In order to solve the above-mentioned problems, in the present invention, at least one beam position detection mechanism provided on the scanning start side of the picture tube and the beam position detection based on the vertical synchronization signal. Detecting means for detecting the difference between the time to the first index signal obtained by the mechanism and the time from the last index signal to the next vertical synchronizing signal in one vertical scanning period including the index signal. A vertical center position adjusting circuit is configured by including control means for controlling the current of the vertical deflection coil according to the level.

F. In the vertical center position adjusting circuit of the present invention, the current of the vertical deflection coil is controlled by the control means so as to reduce the time difference according to the detection level of the time difference obtained by the detection means, The vertical center position is stabilized.

G. Embodiment An embodiment in which the present invention is applied to a beam index type color television receiver will be described below with reference to the drawings.

G-1. Structure of this Embodiment FIG. 3 is a block diagram showing the structure of this embodiment. In the figure, the picture tube 31 is of a beam index type, and an index stripe 4b for obtaining an index signal SI is formed inside the tube surface as shown in FIG. The index stripe 4b is arranged in a wider area than the effective screen 4a, and a line portion 4c is provided on the horizontal scanning start side and a line out portion 4d is provided on the horizontal scanning end side.

An index signal SI is obtained from the detector 32 by beam scanning of the index stripe 4b, and the index signal SI is supplied to a phase synchronization circuit (PLL) 34 via a bandpass filter (BPF) 33. From the phase synchronization circuit (PLL) 34, the index signal SI
A clock having a predetermined frequency synchronized with the clock is supplied to the ring counter 35, and the ring counter 35 switches the switching timing pulses CR, CG, CB of the respective signals of red R, green G and blue B based on this clock. Supply to 36.

The switch circuit 36 uses the timing pulses CR and C.
Controlled by G and CB, the R, G and B signals are sequentially supplied to the video amplifier 37. The output of the video amplifier 37 is supplied to a picture tube to reproduce a color image.

The index signal SI is also used in the vertical center position adjusting circuit 1 according to the present invention. That is, the index signal is the band pass filter (BPF).
It is supplied to the A / D converter 39 via 33, digitized here, and then supplied to the pulse processing circuit 40. In the pulse processing circuit, only the first pulse of the index signal SI in each horizontal scan (hereinafter referred to as index start pulse IDSP) is supplied to the vertical center position adjusting circuit 1.

The vertical center position adjusting circuit 1 comprises a vertical center detecting circuit 1a and a vertical center output circuit 1b. The vertical center detecting circuit 1a detects the shift of the vertical center based on the horizontal synchronizing pulse HBLK and the index start pulse IDSP. The vertical center output circuit 16 controls the current of the vertical deflection coil VDY 38 according to the level of the obtained detection signal to correct the deviation of the vertical center.

G-2. Configuration of Vertical Center Position Adjusting Circuit FIG. 1 is a circuit diagram of the vertical center position adjusting circuit 1.

As described above, the vertical center position adjusting circuit 1 is composed of the vertical center detecting circuit 1a and the vertical center output circuit 1b.

The vertical center detection circuit 1a is a logic IC (Integrated Circuits) such as a retriggerable monostable multivibrator 8, a D flip-flop 2, an inverter 6, and a NOR 7.
And differential transistors 3, 4 and 5, and transistors TR11 and TR12 used for controlling the differential amplifiers 3 and 4 and the like.

The index start pulse IDSP is supplied to the retriggerable monostable multivibrator 8. The output pulse width of the multivibrator 8 is the resistance R
9, determined by the time constant of the capacitor C3, here 1
It is set to about 1.5 times the horizontal cycle.

Output Q of the retriggerable monostable multivibrator 8
Is supplied to one input terminal of the NOR 7 and the inverter 6, and the output of the inverter 6 is supplied to the reset terminal of the D flip-flop 2.

The output of the D flip-flop 2 is fed back to the input D. When the reset terminal is "H", the output is inverted every time a pulse is applied to the clock input CK terminal. The vertical synchronizing pulse VBLK is supplied to the clock input CK terminal. The vertical synchronizing pulse VBLK is also supplied to the other input terminal of the NOR 7. The output of the NOR 7 is supplied via a resistor R8 to the base of the transistor TR11 whose emitter is grounded. The base of the transistor TR11 is grounded via the resistor R7.

The output Q of the D flip-flop 2 is supplied to the differential amplifier 3 formed of transistors TR1 and TR2. The differential amplifier 3 has an active load including transistors TR3 and TR4, and the transistors TR1 and TR2 are provided.
The emitters are commonly connected and connected to the collector of the transistor TR11 via the resistor R6. A power source E1 is connected to the base of the transistor TR2 to determine the operating point of the differential amplifier 3.

The output of the differential amplifier 3 is supplied to the differential amplifier 4 including transistors TR5 and TR6. That is, the collector of the transistor TR2 and the base of the transistor TR5 are connected. A capacitor C1 whose one end is grounded is connected to the base of the transistor TR5.

The differential amplifier 4 has an active load including transistors TR7 and TR8, and the transistors TR5 and T8.
The commutator of R6 is connected in common, and is connected to the collector of the transistor TR12 whose emitter is grounded through the resistor R3.

The transistor TR6 has a collector and a base connected to each other, and one end of which is grounded to the capacitor C2.
Are connected.

The base of the transistor TR12 is grounded through the resistor R4, and the base of the transistor TR12 is connected through the resistor R5.
The vertical synchronizing pulse VBLK is supplied.

The output of the differential amplifier 4 is the transistors TR9 and TR.
It is supplied to a differential amplifier 5 composed of 10. That is, the collector of the transistor TR6 and the transistor TR
Nine bases are connected. The differential amplifier 5 has a constant current circuit IC on the emitter side and a load resistor R1, on the collector side.
It has R2. A power source E2 is connected to the base of the transistor TR10 to determine the operating point of the differential amplifier 5.

The output of the differential amplifier 5 is supplied from the collector of the transistor TR9 to the base of the transistor TR13 of the vertical center output circuit 1b.

The vertical center output circuit 1b includes a transistor TR1.
3, TR14, TR15 and resistors R10, R for bias
11, R12, R13, R14, R15, variable resistor VR
1 and the voltage of the commonly connected collectors of the transistors TR14 and TR15 changes according to the base voltage of the transistor TR13. The voltage of the collector is given to the connection point of the series circuit of the vertical deflection coil VDY38 and the compensation capacitor Cs, and the current of the vertical deflection coil VDY38 driven by the vertical output circuit 41 is controlled.

G-3. Operation of Vertical Center Position Adjusting Circuit FIG. 2 is a timing chart of the vertical center detecting circuit 1a.

As shown in the figure, the vertical synchronizing pulse VBLK supplied to the D flip-flop 2 is a stable signal of the cycle tu, while the index start pulse ID supplied to the retriggerable monostable multivibrator 8 is
SP can fluctuate due to the deviation of the vertical center. The retriggerable monostable multivibrator 8 supplied with the index start pulse IDSP is connected to the resistor R
9. Since the width of the output pulse is set to about 1.5 times one horizontal cycle by the time constant of the capacitor C3, the output pulse VINDX is as shown in FIG. The period input to th is “H”, and the other periods are “L”.

Here, the time from the fall of the vertical synchronizing pulse VBLK to the rise of the index start pulse is τ ₁ , the period during which the index start pulse IDSP is “H” is τ ₂ , and the index start pulse I
If the time from the fall of the DSP to the rise of the next vertical synchronizing pulse VBLK is τ ₃ , then (τ ₁ −τ ₃ ) = 0 when the vertical center coincides with a predetermined position,
When it shifts upward (τ ₁ −τ ₃ )> 0, when it shifts downward (τ ₁ −τ ₃ ) <0.

The D flip-flop 2 outputs the output pulse VIND.
Since X is supplied to the reset terminal through the inverter 6, the output pulse VFRNT which becomes "H" at the rising of the vertical synchronizing pulse VBLK and becomes "L" at the rising of the output pulse VINDX is output to the differential amplifier 3
To the base of the transistor TR1.

Further, the NOR circuit 7 supplies the output pulse NOR which becomes "H" when both the vertical synchronizing pulse VBLK and the output pulse VINDX are "L" to the transistor TR11 through the resistor R8. The transistor TR11
Is ON during the output pulse NOR is "H", the differential amplifier 3 can operate during this period. That is, the differential amplifier 3 becomes operable at the times τ ₁ and τ ₃ .

The voltage of the power source E1 of the transistor TR2 is "H".
Since the output pulse VFRNT is “H” at the time τ ₁ , the transistor TR2 is turned off and the transistors TR1, TR3 and TR4 are in the operating state because the voltage is set lower than the level voltage. .
At this time, the capacitor C1 is charged through the transistor TR4, and its voltage gradually rises. At the time τ ₂ , the differential amplifier 3 does not operate, so this voltage V ₁ is held. This voltage V ₁ is the time τ ₁
Corresponding to.

On the other hand, at the time τ ₃ , the output pulse VFRNT is “L”, and the transistors TR1, TR3, TR
4 is turned off, and the transistor TR2 is connected to the power source E.
Since the bias current is supplied by 1 to operate, the capacitor C1 is connected to the transistor TR2 and the resistor R2.
6. It is discharged through the transistor TR11, and its voltage gradually decreases. When the voltage lowered here is V ₂ , this corresponds to the time τ ₃ .

Therefore, the voltage C which is the difference between V ₁ and V ₂ is applied to the capacitor C _1.
3 is obtained. This voltage V ₃ corresponds to the difference (τ ₁ −τ ₃ ) between the times τ ₁ and τ ₃ .

The voltage V _{3 of the} capacitor C1 is
The transistor TR12, the capacitor C2, and the like sample and hold the vertical synchronizing pulse VBLK during a period of "H". That is, while the vertical synchronizing pulse VBLK is "H", the transistor TR12 is turned on and the differential amplifier 4 becomes operable. At this time, when the voltage of the capacitor C2 is lower than the voltage of the capacitor C1, the transistor TR6 is off, the transistors TR5, TR7, TR8 are in the operating state, and the capacitor C2 is connected via the transistor TR8. It is charged until the voltage becomes equal to the voltage of the capacitor C1.

On the contrary, the voltage of the capacitor C2 is equal to that of the capacitor C1.
If the voltage is higher than the voltage of
7 and TR8 are turned off and the transistor TR6 is activated, so that the capacitor C2 is discharged until its voltage becomes equal to the voltage of the capacitor C1.

Therefore, the voltage of the capacitor C2 is obtained by sampling and holding the voltage of the capacitor C1 while the vertical synchronizing pulse VBLK is "H" as shown in FIG.

Since the voltage of the capacitor C2 corresponds to the above (τ ₁ −τ ₃ ), it corresponds to the fluctuation of the index start pulse IDSP, that is, the shift of the vertical center, and the detection signal from the differential amplifier 5 is obtained. The DVC is supplied to the vertical center output circuit 1b.

By controlling the current of the vertical deflection coil VDY38 in accordance with the level of the detection signal DVC in the vertical center output circuit 1b, eventually (τ ₁ −τ ₃ ) = 0, that is, there is no vertical center deviation. Maintained.

In this way, the vertical center position adjusting circuit 1 adjusts the position of the vertical center by detecting the above-mentioned time difference (τ ₁ −τ ₃ ), so that, for example, when the vertical amplitude is changed by the vertical amplitude adjusting circuit or the like. However, the time difference (τ ₁ −
τ ₃ ) is unaffected. Therefore, the vertical center position adjusting circuit 1 and the vertical amplitude adjusting circuit can operate independently of each other, and the stability of the vertical center position adjusting circuit 1 is improved.

H. As described above, according to the present invention, since the vertical center position adjusting circuit can be operated independently of the vertical amplitude adjusting circuit, the vertical center can be stabilized at a predetermined position regardless of the fluctuation of the vertical amplitude. can do. Therefore, the stability of the vertical center position adjusting circuit is improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a vertical center position adjusting circuit according to the present invention, and FIG. 2 is a timing chart for explaining the operation of a vertical center detecting circuit which constitutes the circuit. FIG. 3 is a block diagram of the present embodiment in which the present invention is applied to a beam index type color television receiver, and FIG. 4 is a schematic diagram of an index stripe provided on a picture tube used in the above receiver. Is. FIG. 5 is a diagram for explaining a conventional vertical center position adjusting method. 1 ... Vertical center position adjusting circuit 1a ... Vertical center detecting circuit 1b ... Vertical center output circuit 2 ... D flip-flop 3, 4, 5 ... Differential amplifier 6 ... Inverter 7 ... NOR TR1, TR2, ... TR15 ... Transistors R1, R2, ... R15 ... Resistors C1, C2, C3, Cs ... Capacitors E1, E2 ... Power supply 31 ... Picture tube 32 ... Detector 33 ... Bandpass filter 34 ... Phase synchronization circuit 35 ...... Ring counter 36 ...... Switch circuit 37 ...... Video amplifier 38 ...... Vertical deflection coil 39 ...... A / D converter 40 ...... Pulse processing circuit

Claims (1)

[Claims] 1. At least one beam position detecting means provided on a scanning start side of a picture tube, a time from a vertical synchronizing signal to a first index signal obtained by the beam position detecting means, and the index signal are included. A difference between the time from the final index signal to the next vertical synchronizing signal within one vertical scanning period, and a control means for controlling the current of the vertical deflection coil according to the detection level of the detecting means. A vertical center position adjusting circuit characterized by stabilizing the position of the vertical center by controlling the control unit to reduce the time difference.