JPH0655584B2 - Fault signal discrimination circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a failure discriminating circuit for discriminating and recording a collision signal and a failure signal input to an occupant protection device without error.

[Prior Art] There is an occupant protection device that protects an occupant by inflating an air bag or the like when a vehicle crashes.

In the event of a failure of this occupant protection device, the occupant protection device will not operate at the time of a collision, or the occupant protection device will operate even when there is no collision to inadvertently restrain the occupant. Cannot be secured. Therefore, conventionally, for example, as shown in Japanese Patent Publication No. 52-12456, an occupant is alerted when a failure occurs,
In addition to urging the repair of the failed part as soon as possible, the time from the occurrence of the failure to the collision and the time from the occurrence of the failure to the activation of the occupant protection device are recorded in a recorder to clarify the responsibility. I try to contribute to the investigation of the cause of the accident.

Conventionally, when recording on the recorder, a failure signal and a collision signal are discriminated and recorded by a failure signal discrimination circuit as shown in FIG.

That is, the configuration of this failure signal determination circuit is such that the two collision detection sensors S1 and S2 are connected to the DC power source D via the detonator R _S.
C is connected in series, and the collision detection sensor S1,
Failure detection resistors R ₁ and R ₂ are connected in parallel to S2.

Comparators CP ₁ and C are provided at both ends of the detonator R _S , respectively.
The input side of P ₂ is connected, and the output side of the comparator CP ₁ is connected to _one end of the logical product circuit AND and the input side of the logical sum circuit OR. The output side of the comparator CP ₂ is connected to the AND circuit AND,
And the other end on the input side of the OR circuit OR. The output sides of the logical product circuit AND and the logical sum circuit OR are connected to the bases of the transistors Q ₁ and Q ₂ via resistors R ₃ and R ₄ , respectively.

Emitter of the transistor Q ₁ is connected to the negative side of the DC power source DC, the collector of the transistor Q ₁ is connected to one end of Hiyuzu F _1, the Hiyuzu F ₁
The other end of is connected to one end of the collision detection sensor S1.

On the other hand, the output side of the OR circuit OR is connected to the base of the transistor Q ₂ via the resistor R _4, and the emitter of this transistor Q ₂ has one end of the collision detection sensor S1 and the minus side of the DC power supply DC. Connected with.

The collector of the transistor Q ₂ is connected to one end of Hiyuzu F _2, the other end of the Hiyuzu F ₂ is connected to one end of the collision sensors S2.

Next, the operation of the fault signal determination circuit having the above configuration will be described.

When the collision detection sensors S1 and S2 for monitoring the electric potential at both ends of the detonator R _S and detecting the collision are closed at the same time, this collision signal is output to the comparator C, respectively.
It is input to the AND circuit AND via P ₁ , the comparator CP ₂ and the inverter I, and the output is the transistor Q.
The base of _{No. 1} is driven, and the fuse F ₁ is melted by the collector-emitter current flowing through the transistor Q ₁ .
It is recorded as a collision in a recorder (not shown).

Also, collision detection sensors S1 and S2 for detecting a collision
Do not close at the same time and operate due to some failure, and when either of the collision detection sensors S1 and S2 closes, the base of the transistor Q ₂ is driven via the OR circuit OR, and the transistor Q ₂ The fuse F ₂ is blown out by the current between the collector and the emitter flowing through, and is recorded as a failure in a recorder (not shown).

[Problems to be Solved by the Invention] Since the conventional failure signal discriminating circuit is configured as described above, the collision detection sensors S1 and S for detecting a collision.
If 2 is not closed at the same time, it is not recorded as a collision, and even if a collision actually occurs, due to the impact of the difference in the mounting positions of the collision detection sensors S1 and S2 and the influence of chattering, Two collision detection sensors S1,
In addition, S2 operates at different timings, and in such a case, it is erroneously recorded as a failure.

The present invention has been made to solve the above problems, and even if two collision detection sensors operate at different timings, the collision signal and the failure signal can be clearly recognized without being mistaken as a failure signal. It is an object of the present invention to provide a failure signal discriminating circuit capable of discriminating and recording.

[Means for Solving the Problems] A failure signal discriminating circuit according to the present invention includes a receiving means for receiving two signals having different generation timings, and a holding means for holding the two signals received by the receiving means for a certain period of time. And a signal discrimination recording means for comparing two signals held by the holding means, discriminating a collision if they overlap with each other and recording, and discriminating a failure if they do not overlap with each other and recording. is there.

[Operation] In the failure signal discriminating circuit according to the present invention, the receiving means receives the collision signal and the failure signal having different generation timings, and these two collision signals and the failure signal are kept constant by the holding means. After holding for a period of time, the signal discrimination recording means compares the two collision signals with the failure signal, and if they do not overlap each other, it is determined as a failure and recorded.

[Embodiment] An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 is a circuit diagram of a fault signal discriminating circuit showing an embodiment of the present invention.

In the figure, monostable multivibrators 1 and 2 are provided as receiving means for receiving two collision signals and failure signals having different generation timings, and they are connected to each other as illustrated. Each of the monostable multivibrators 1 and 2 has a capacitor as a holding unit that is determined by a CR time constant in order to hold the collision signal and the failure signal input to the monostable multivibrators 1 and 2 for a certain period of time. C1,
It has C2 and resistors R1 and R2.

Reference numeral 3 is a monostable multivibrator having a capacitor C3 and a resistor R3. The output from the Q1 terminal of the monostable multivibrator 1 is input via the B3 terminal, and
The output from the Q2 terminal of the monostable multivibrator 2 is input through the A3 terminal.

At the output terminal Q3 of the monostable multivibrator 3,
The base of the transistor Tr is connected through the resistor R4, the emitter of the transistor Tr is grounded, and the fuse F which blows when a failure signal is input is connected to the collector.

In the figure, OR is Q1 of the monostable multivibrator 1.
OR output O of the monostable multivibrator 2 and the inverted output of Q2 of the monostable multivibrator 2 are input.
R and Sc are short-circuit trigger circuits which receive the output of the OR circuit OR, and AMP is an amplifier whose output side is connected to the C _D2 and C _D3 terminals of the monostable multivibrators 2 and 3.

Next, the operation of the fault signal discriminating circuit configured as described above will be described with reference to the operation waveform diagram of FIG.

In the figure, each waveform on the right side of the drawing shows a voltage waveform during normal operation, and the waveform on the left side of the drawing shows a waveform during abnormal operation. Also, in the figure, A1 to Q3 indicate the input / output voltage waveforms of the terminals of the monostable multivibrators 1, 2, 3 in FIG.

Therefore, the input terminals A of the monostable multivibrators 1 and 2 are
When a collision signal and a failure signal having the waveforms shown on the right side of FIG. 2 are input to A1 and A2 at different timings, a signal determined by the CR time constant in each monostable multivibrator 1 and 2. After performing the processing and holding both the collision signal and the failure signal for a certain period of time, the both signals are input to the monostable multivibrator 3 via the input terminals A3 and B3.

In this case, the collision signal and the failure signal input via the input terminals A3 and B3 are compared, and both signals overlap each other, so that there is no output from the Q3 terminal.

Therefore, the transistor Tr does not conduct, and the fuse F
Does not melt. That is, even if two collision signals and a failure signal having different timings are input, the failure is not determined, the failure is not recorded, and the collision is recorded in a recorder (not shown).

Next, the input terminals A of the monostable multivibrators 1 and 2
When a collision signal and a failure signal having waveforms as shown on the left side of FIG. 2 are input to 1, A2 at different timings, each monostable multivibrator 1, 2 is
After performing signal processing determined by the CR time constant and holding both the collision signal and the failure signal for a certain period of time, the both signals are input to the monostable multivibrator 3 via the input terminals A3 and B3.

In this monostable multivibrator 3, the collision signal and the failure signal are compared. In this case, since both signals do not overlap each other, it is determined as a failure and an output is output to the Q3 terminal.

The output from the Q3 terminal causes the transistor Tr to become conductive, and the fuse F is melted by the collector-emitter current flowing through the transistor Tr.

That is, when two collision signals and a failure signal having different timings of the waveform as described above are input, they are recorded as a failure without being erroneously determined as a collision.

In the above embodiment, the receiving means for receiving two signals having different generation timings, the holding means for holding the two signals received by the receiving means for a certain period of time, and the two signals held by the holding means are compared. Then, if they overlap each other, it is determined to be a collision and recorded, and if they do not overlap each other, it is determined to be a failure and the signal determination and recording means is recorded, and the monostable multivibrators 1, 2, 3 and the transistor Tr,
Although the fuse F or the like is used in combination, the present invention is not limited to these constituent parts, and can be replaced by a constituent part having a similar function.

[Effects of the Invention] As described above, the failure signal determination circuit of the present invention is
The receiving means receives the collision signal and the failure signal having different generation timings, the holding means holds the two collision signals and the failure signal for a certain period of time, and thereafter, the signal discrimination recording means holds the two collisions. The signal and the failure signal are compared, and if they overlap with each other, it is determined to be a collision and recorded, and if they do not overlap with each other, it is determined to be a failure and recorded, so that the two collision detection sensors operate at different timings. Even if it is not a fault signal, the collision signal and the fault signal are clearly distinguished, and during normal operation, the responsibility is clarified in the event of a collision without accidentally recording it as a fault. It has an excellent effect that it greatly contributes to the investigation.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a fault signal discriminating circuit showing an embodiment of the present invention, FIG. 2 is an operation waveform diagram at each terminal of the fault signal discriminating circuit, and FIG. 3 is a circuit diagram of a conventional fault signal discriminating circuit. Is. In the figure, 1, 2, 3 ... Monostable multivibrator, Tr ... Transistor, F ... Fuse.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Koichi Uechi 1-4-1 Chuo, Wako-shi, Saitama, Honda R & D Co., Ltd. (56) References JP-A-54-47244 (JP, A) Kai 61-24648 (JP, A) Japanese Patent Sho 48-9736 (JP, B1)

Claims (1)

[Claims] 1. A receiving means for receiving two signals having different generation timings, a holding means for holding the two signals received by the receiving means for a certain period of time, and two signals held by the holding means are compared. A fault signal discriminating circuit comprising: a signal discriminating and recording unit that discriminates and records a collision if they overlap each other, and discriminates a fault if they do not overlap each other and records them.