JPH065600B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an insulated gate field effect transistor (hereinafter referred to as MOS transistor) type which enables high integration and a simplified circuit system by operating at low temperature. The present invention relates to a semiconductor device.

[Background of the Invention]

Conventionally, regarding the operation of the MOS type semiconductor device in the low temperature range,
For example, (1) IEEE Trans. Electron Devices, ED-
24,218-229 (1977), "Very Small MOS FET's for Low-Temperatu" by FH Gaensslen et al.
re Operation ”, (2) Band 33, 229-235 (1979) by W. Link et al.,“ Eigenschaften Von MOS-Ein-
Transistor speicherzellen bei tiefen Temperature
n ”or (3) Proceedings of IEICE General Conference, 2-
283 (Showa 59) in "Movement analysis of dynamic RAM at low temperature" by Tsuyoshi Morooka et al.

In the literature of (1) above, the characteristics of the device are analyzed in the low temperature range.For example, the relationship between the electron velocity and the electric field changes with temperature, and the threshold voltage is The threshold voltage V _T rises at low temperatures and the charge stored at the junction is 296
K and 77K (low temperature region), which has less leakage (leakage of electric charge is lower in the low temperature region) is described. Further, the above-mentioned document (2) shows the temperature characteristics in the dynamic RAM, and describes, for example, the relationship between the refresh time and the temperature (the refresh time interval may be long in the low temperature region). However, in both documents (1) and (2), the MO operating at low temperature
We are not aware of any problems when the S element is applied to a circuit.

Next, the literature of (3) above shows the operating characteristics of a dynamic RAM at low temperature. For example, when the mode is pause refresh (when other circuits are not operating), the temperature should be low. For example, although the refresh time becomes longer in proportion to it, it is stated that in the case of disturb refresh (when other circuits are operating), the refresh time does not change at a temperature lower than a low temperature range. However, no reference is made to a circuit system most suitable for a MOS device operating in a low temperature range.

[Object of the Invention]

In order to meet the demands as described above, an object of the present invention is to provide a semiconductor device of an integrated circuit which has a high degree of integration equivalent to that of a dynamic circuit and has the simplicity of a static circuit which does not require a complicated internal or external timing signal. To provide.

[Outline of Invention]

In order to achieve the above object, a semiconductor device of the present invention has a supply means for inputting a signal processing start signal and supplying an electric charge to a predetermined circuit node when the state of an input signal to the signal processing circuit changes. It is characterized in that the supply means and the signal processing circuit are operated in a temperature range of 200 K or less.

A semiconductor device according to an exemplary embodiment of the present invention disclosed in the present application includes a signal processing circuit (14, 17) and input signals (X ₁ , X ₂ , ..., Xm to the signal processing circuit (14, 17). Detection circuit (15, 18) for detecting a change in the state of (4), and a predetermined circuit of the signal processing circuit (14, 17) in response to the detection signal (φ,) from the detection circuit (15, 18). Node (21,25,2
Supply control means (20,23,30) for controlling the charge supply to (6,34)
And a first conductivity type first impurity region formed in a second conductivity type first well region (9) formed on the first conductivity type semiconductor substrate (4). A circuit node for holding charges of the signal processing circuit is formed by (10), and the second well region (6) of the second conductivity type formed on the semiconductor substrate (4) of the first conductivity type is formed. The drain region of the MOS transistor performing the saturation operation of the signal processing circuit is formed by the second impurity region (8) of the first conductivity type formed in the drain region (8) immediately below the drain region (8) of the MOS transistor. In the second well region (6) of the second conductivity type, by forming the protrusion region (13) of the first conductivity type protruding from the semiconductor substrate (4) of the first conductivity type, The protrusion region (13) absorbs minority carriers from the drain region (8), and the second conductivity type The first well region (9) and the second well region
Insulator region between the second well region (6) of conductivity type
By forming (12), the minority carriers are prevented from passing from the second well region (6) to the first well region (9), and the signal processing circuit (in the temperature range of 200 K or less). 14, 17) and the supply control means (20, 23, 30) are operated.

According to such a representative embodiment of the invention, by operating the signal processing circuit (14, 17) and the supply control means (20, 23, 30) in a temperature range of 200 K or less, the leakage current of each circuit is reduced. Can be remarkably reduced, and the refresh operation for compensating for the potential fluctuation of the circuit node for holding charges of the signal processing circuit due to the leak current can be made unnecessary.

Furthermore, since minority carriers due to ionization in the vicinity of the drain region of the MOS transistor that performs the saturation operation of the signal processing circuit may destroy the charge information at the circuit node for holding the charge of the signal processing circuit, this MOS transistor Of the first conductivity type formed in the second well region (6) of the second conductivity type immediately below the drain region (8) of the first conductivity type.
3) and the insulator region (12) formed between the first well region (9) and the second well region (6) are the charge information destruction of the circuit node for charge retention of the signal processing circuit. The risk of can be reduced.

A more preferred embodiment of the present invention is that the second conductivity type circuit is provided directly below the first impurity region (10) of the first conductivity type as a circuit node for holding charges.
By forming the second conductivity type high-impurity concentration buried layer (11) in the conductivity type first well region (9), the arrival of minority carriers at the circuit node (10) for holding charges is reduced. It is characterized by.

According to a more specific embodiment of the present invention, the circuit node for holding charges is formed in the memory array region, the MOS transistor performing the saturation operation is formed in the peripheral circuit region, and the memory array region and the peripheral circuit region are It is characterized by being separated by an insulator region.

Example of Invention

Hereinafter, the principle and embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a diagram showing the temperature dependence of the junction leakage current based on the measurement results.

One characteristic in the low-temperature region of the MOS device, the source, there is a temperature dependence of the leakage current I _L at the drain junction. FIG. 2 shows the result of actual measurement (leakage current I with respect to temperature T). The leakage current, that is, the leakage current I _{L with} respect to the temperature of the charge accumulated in the source / drain junction is almost the intrinsic carrier temperature n. proportional to _i . At room temperature, for example, when the leak current value at 293K is I,
It can be seen that the value becomes about 10 ^{−28 in the} low temperature region, for example, 70 K, and the value decreases by about 28 digits in the low temperature region as compared with the normal temperature. Therefore, when the circuit is operated in such a state, the potential change due to the leak current at the circuit node is almost eliminated.

In the present invention, by operating the circuit in the low temperature region, the potential change due to the leak current at the circuit node is eliminated, and it is not necessary to constantly supply the electric charge to the circuit node. give. That is, it is possible to realize a semiconductor integrated circuit having the same degree of integration as a dynamic circuit and having the simplicity, operating speed, and power consumption of a static circuit.

FIG. 1 is a block diagram of a semiconductor device and an operation time chart showing an embodiment of the present invention.

X _{1 to} Xm are input signals, Y _{1 to} Yn are output signals, φ is a signal processing start signal (a signal applied when the state of the input signal changes), Vcc is a power supply voltage, Vss is a ground potential,
N _{1 to} Ni are circuit nodes, 1 is a signal processing circuit, 2 is a power supply unit that supplies electric charges to the nodes, and 3 is a logic processing unit.

In FIG. 1 (b), T ₂ represents a time during which the input signal does not change, and T ₁ represents a constant period irrelevant to the input signal.

In the embodiment shown in FIG. 1, a power supply unit 2 for supplying electric charges to the circuit nodes N _{1 to} Ni in the electric charge holding state in the signal processing circuit 1 by the signal processing start signal φ is provided,
The main constituent condition is to operate the signal processing circuit 1 in a low temperature range of 200 K or less. Here, the signal processing circuit 1
Is an integrated circuit, and the input signals X _{1 to} Xm and the signal processing start signal φ are generated and input by an external circuit.

The signal processing start signal φ activates the power feeding unit 2 for a predetermined time in synchronization with the state change of the input signals X _{1 to} Xm (static operation), or activates the power feeding unit 2 for a predetermined time according to a predetermined cycle T ₁ . The predetermined circuit node N ₁
Since electric power is supplied from the power source Vcc to Ni, the circuit 1 enters the operating state and the logic processing unit 3 starts the signal processing operation.

In FIG. 1 (b), as an example, the case where the input signals of X _{1 to} Xm show the state change as shown in the figure is shown. The signal processing start signal φ is a predetermined pulse rising at the time of change of the input signal. Input as a width signal. During the period _{T 2} are not the state change of the input signal _X 1 through XM, but the circuit node _N 1 _~Ni
Input signal X ₁ ~
A signal processing start signal φ (refresh) generated at a predetermined cycle T ₁ not related to Xm is input. When a series of signal processing in this state is completed, output signals Y _{1 to} Yn corresponding to the input signals X ₁ to Xm are output, and when the signal φ is turned off next, the circuit nodes N _{1 to} Ni are connected to the logic processing unit 3. The state shifts to the electric charge holding state in accordance with the state. The above is normal temperature (for example,
Operation at 300K).

Next, when the circuit of FIG. 1 (a) is operated in the low temperature region of 200 K or less, the leakage current is significantly reduced, and the electric charges held at the circuit nodes N _{1 to} Ni are hardly reduced. Therefore, even when the time T ₂ during which the input signals X _{1 to} Xm do not change is sufficiently longer than the signal processing time, the circuit 1 operates stably and no current flows in the circuit 1 during the period of T _2. It is possible to reduce power consumption. In addition, due to the relationship between the operating temperature (low temperature range) and the operating frequency, T ₁ = ∞,
That is, the refresh operation is not necessary even if there is no change in the state of the input signal for a long time.

3 and 4 are block diagram of a semiconductor device showing another embodiment of the present invention.

The embodiment shown in FIGS. 3 and 4 is a partial modification of the embodiment shown in FIG. 1. In FIG. 1, the generation circuit of the signal processing start signal φ is provided in the external circuit. In FIGS. 3 and 4, the signal generation circuit 1 which detects the state change of the input signals X _{1 to} Xi to the signal processing circuit and generates the signal processing start signal φ
5, 18 are provided on the same semiconductor substrate as the signal processing circuits 14, 17.

In FIG. 3, 14 is a signal processing circuit, 15 is a circuit for detecting a state change of the input signals X _{1 to} Xm and generating a signal processing start signal φ, and 16 is an activation of the φ generation circuit 15 at a predetermined cycle T _1. The input signal terminal for is shown. Since no external signal operation such as input signal monitoring is required, the ease of use is greatly improved.

In FIG. 4, 17 is a signal processing circuit, 18 is a circuit for generating a signal processing start signal φ, and 19 is a circuit for generating a timing signal of a predetermined cycle T ₁ . The φ generation circuit 18 is
In synchronization with the state change of the input signals X _{1 to} Xm, or
The signal processing start signal φ is generated in synchronization with the timing output of the cycle T ₁ of the built-in signal generation circuit 19.

Since the φ signal generating circuit 18 including the circuit 19 for generating a predetermined periodic signal is provided on the same substrate as the signal processing circuit 17, the external periodic signal generating circuit is different from that in the case of FIG. Since it is not necessary and the number of input terminals is reduced, the convenience of use is further improved.

5 and 6 are concrete logic circuit diagrams of the signal processing start signal generating circuit and the timing signal generating circuit of a predetermined cycle in FIG. 3 and FIG. 4, respectively, and FIG. 7 is the operation of FIG. It is a time chart.

In FIG. 5, X _{1 to} Xm are input signals, C ₁ is a timing signal having a predetermined period T ₁ , 37 is a delay circuit (delay time t ₀ ), 39 is an inverter, 40 is an exclusive NOR circuit, 41 Is an OR circuit, and 42 is a NOR circuit.

In response to changes in the input signals X _{1 to} Xm and the timing signal C ₁ having a predetermined period T ₁ , a signal φ having a pulse width of time t ₀ set by the delay circuit 37 and (Inversion signal of φ) is generated. For example, when the input signal X ₁ is generated with the waveform shown by X ₁ in FIG. 7, this is delayed by the delay circuit 37 by t ₀ as shown by (37) in FIG.
On the other hand, the input signal X ₁ is output from the inverter 39 as shown in FIG.
The signal is inverted as shown in (39) and input to the exclusive NOR circuit 40 together with the waveform in (37), and becomes a signal having a pulse width t ₀ as shown by X _1t in FIG. 7. By inputting this to the OR circuit 41 and the NOR circuit 42, respectively,
Signal processing start signal φ and Is output.

Similarly, the input signals X ₂ , X ₃ , ..., Xm become X ₁
When they are input with a delay of t ₂ , t ₃ , ... _Tm , respectively, the delay circuit 37, the inverter 39, and the logic circuit 40 all cause the pulse X _1t as shown by X _2t ,. Pulses are generated at time positions delayed by t ₂ , t ₃ ... T _m , respectively. Further, the timing signal C ₁ having the predetermined time T ₁ is also generated in exactly the same manner at a time delayed by tc from the input signal X ₁ and at a time interval of T _{1 from the} next pulse. .

FIG. 6 shows a specific example of the timing signal (C ₁ ) generation circuit 19 of FIG. 4, which is incorporated in the signal processing start signal (φ) generation circuit 18.

The self-excited oscillator includes an odd number of stages (2N-1) of inverters 39 and a delay circuit 38 that generates a delay having negative temperature dependence. If the delay time t _d of the delay circuit 38 is set to be t _d ∝1 / I _L compared to the junction leak current I _L described above, when I _L is small, that is, when the charge holding time is long. , A long cycle timing signal, and vice versa, a short cycle timing signal is obtained.

FIG. 8, FIG. 9 and FIG. 12 are configuration diagrams showing specific examples of the signal processing circuit in FIG. 1, FIG. 3, and FIG.

FIG. 8 shows a 3-input NOR circuit portion. When the signal processing start signal activates the charge supply circuit 20, the circuit node 21 is supplied with the charge from the power supply Vcc, and the circuit performs the static operation corresponding to the inputs i _{1 to} i ₃ . After a predetermined time Deactivates the charge supply circuit 20, the charge is accumulated at the node 21 only when all of i _{1 to} i ₃ do not activate the logic processing unit, and then Holds its charge until activating the supply circuit 20.

In FIG. 8, a circuit with low power consumption can be realized as easily as a conventional static circuit. The element 22 (shown by a broken line) connected in parallel to the supply circuit 20 in FIG. 8 is a high resistance element having a resistance value of 1 GΩ or more, and is connected when used at room temperature. That is, since there is almost no leak current in the low temperature region, the resistor 22 is unnecessary, but at normal temperature, the leak current is large and the electric charge at the node 21 leaks. Is replenished from the power source Vcc. As a result, the charge retention characteristics can be compensated up to room temperature or higher, and the stable operation of the circuit can be enhanced.

In FIG. 8, the charge supply circuit 20 has a PMOS.
An nMOS transistor is used for the transistor and a transistor controlled by the inputs i _{1 to} i ₃ .

FIG. 9 shows the configuration of a 1-bit portion of a random access memory (RAM) as another example of the signal processing circuit, and FIG. 11 is a voltage state diagram of the memory cell of FIG.

When the signal processing start signal activates the charge supply circuit 23, charges are supplied from the power supply Vcc to the bit lines b, and the signal on the word line w activates the nMOS transistor 24, so that the charges are generated. It is supplied to the circuit nodes 25 and 26 in the information holding state. Here, elements (nMOS transistors) 2 which are cross-connected to each other
7, 28 activate one and deactivate the other in accordance with the charge amount of the nodes 25, 26, so that a signal corresponding to that is output to both bit lines to start reading.

When a write operation is performed, electric charges corresponding to write information are applied to the bit lines b and at this point and are forcibly supplied to each node through the transistor 24. After a predetermined time, word line w, signal processing start signal Deactivates transistors 23 and 24 respectively,
The electric charge of the node 25 or 26 becomes a holding state, and then , W hold their charges until they activate the transistors 23, 24. When operated in the low temperature range, a long time, w
Even if the transistors 23 and 24 are not activated, there is no charge leakage, and stable operation is possible. In the example of FIG. 9, high integration of about 1.5 times can be realized as compared with the conventional static circuit. The element 29 shown by the broken line in FIG. 9 is a high resistance element having a resistance value of 1 GΩ or more, and by inserting it as shown in the figure, like the element 22 in FIG. Can be compensated up to room temperature or higher to improve the stability of the circuit.

FIG. 10 is a diagram showing a configuration of a 1-bit portion of a RAM including a dummy cell as another example of the signal processing circuit.

Since the charge signal accumulated in the capacitance Cs of the memory cell is small, a dummy cell having a differential amplifier 36 and a capacitance Cs / 2 for comparison is provided, and the difference signal is amplified to read information.

Signal processing start signal φ, However, the charge supply circuit 30 is deactivated, the supply of the charge from the power supply Vcc to the bit line b, which has been performed until then, is stopped, and the potential of the circuit node 32 of the dummy cell is set to Vcc until then. The corresponding element 31 is deactivated. Next, when the elements 33 and 35 are activated by the signals applied to the word lines w _A and w _D , a signal corresponding to the charge amount of the nodes 34 and 32 is generated on the bit line b, and the difference is generated. By differentially amplifying with the dynamic amplifier 36,
Start reading information. In order to perform the write operation, the electric charge corresponding to the information at this time may be forcibly supplied from the outside through the amplifier 36. W _A , w after a predetermined time
_The elements 33 and 35 are deactivated by the signal _D , and signals φ, When the elements activate the elements 30 and 31, the node 34 enters the charge holding state, and holds the charge until the signal of w _A activates the element 33 next.

At a low temperature of 200 K or less, since the charge holding time is sufficiently long, no special refresh operation is required, and therefore no special signal is required, and even a dynamic circuit can be as simple as a static circuit. realizable.

11 and 12 are a characteristic view and a sectional view of a semiconductor device showing another embodiment of the present invention.

FIG. 11 is a diagram showing the relationship between the junction leak I _L shown in FIG. 2 and the noise current I _N of the MOS transistor operating in saturation. That is, in the saturated MOS transistor, when the electric field is concentrated near the drain,
Electron collisions occur and ionization produces electron-hole pairs. When minority carriers (noise current _IN ) due to ionization are injected into the semiconductor substrate, they destroy other information of the retained charges.

Since the noise current I _N strongly depends on the magnitude of the electric field near the drain, it cannot be generally matched with the leak current I _L , but with respect to the absolute temperature T, L _N ∝ exp (φ _B
/ KT) since it is considered to represent the exponential dependence, in low temperature region, the state of I L _<< I _N appears.

Under such a situation, as described above, the noise current I _N
Discharges the electric charge of the circuit node in the electric charge holding state, causing the circuit to malfunction. To prevent this noise current I _N, the embodiment for increasing the effect of the present invention shown in FIG. 12.

In FIG. 12, 4 is a high-concentration first-conductivity-type semiconductor substrate, 5 is a low-impurity-concentration layer having the same conductivity-type as 4, 6 is a low-impurity-concentration layer having a conductivity type opposite to 4, and 7 is a gate electrode. 8
Is a drain region of a MOS transistor in a saturation operation state, which is the opposite conductivity type to 6, 9 is a conductivity type opposite to 5, a well region having a concentration gradient such that the impurity concentration on the surface is high, 10 is a conductivity type opposite to 9 Type MOS transistor having a circuit node in a charge holding state in the drain or source region, 11 is a buried layer of the same conductivity type as the region 9 provided inside the region 9 and facing the region 10, and having a high impurity concentration,
Reference numeral 12 denotes an insulator region that separates a MOS transistor in a saturated operation state from a circuit connection point in a charge holding state, and 13 denotes a protruding region of a region 4 provided inside the layer 6 facing the region 8, respectively. It represents. Further, a bias that does not become the forward direction is applied to each region.

In FIG. 12, minority carriers due to ionization are injected into the substrate 1 in the vicinity of the drain region 8 of the MOS transistor in the saturated operation state, which becomes the noise current _IN, and the other MOS transistor has a noise current IN. The circuit node 10 may be reached and the stored charge information may be destroyed.

By using the structure of FIG. 12, the noise current due to the minority carriers generated in the vicinity of the region 8 is (i) the protrusion region 1
3 is absorbed by the substrate 4. (ii) Insulation is provided by the insulator region 12, and carriers are not passed. (iii) It is difficult for carriers to reach the circuit node 10 due to the barrier due to the junction between the well region 9 and the low impurity concentration layer 5 or the barrier due to the impurity concentration gradient in the well region 9. (iv) Embedded layer 1
A barrier is created by the difference in impurity concentration between 1 and the well region 9 to make it difficult for carriers to reach the circuit node 10.

FIG. 13 shows an embodiment in which the structure of FIG. 12 is applied to the memory circuit of FIG. The figure shows a memory cell in the memory array region, which includes a gate connected to the word line w _A , a drain connected to the bit line b, a source connected to the storage capacitor Cs, and a storage capacitor Cs, and a peripheral circuit. The channel MOS and the P channel MOS during the saturation operation in the region are shown. 37 is an n ⁺ type or n type substrate,
38 is an n-type region, 39 is a P-type well region, 40 is an n ⁺ type drain / source region, 41 is a P ⁺ type drain / source region, 42 is a gate, 43 and 44 are isolation regions of an insulator, 45 Is a P ⁺ -type buried layer, and 46 is an n-type protrusion region. In this embodiment, the N-channel MOS of the noise charge generation source is used.
Are provided in a well having a concentration gradient, and an n-type protrusion region is provided in the well to absorb noise charges in the substrate, and a peripheral circuit region where a noise charge generation source exists and a memory.
The array region is separated by the isolation region 44, and interference due to noise charges between the memory cells is isolated by the isolation region 4.
No. 3 is eliminated, and the P ⁺ -type buried region serving as a barrier against noise charges is provided in the P-type well of each cell to prevent the noise charges from flowing into the charge storage capacitance section.

Although FIG. 12 and FIG. 13 show an example in which all the above-mentioned regions (i) to (iv) are provided, it is needless to say that even if each region is provided independently, it is effective. .

〔The invention's effect〕

As described above, according to the present invention, the electric charge is supplied to the circuit node in the electric charge holding state in the signal processing circuit by the signal processing start signal to operate in the temperature range of 200 K or less, so that the leak current is reduced. As a result, a high degree of integration equivalent to that of a dynamic circuit can be provided, and the simplicity of a static circuit that does not require complicated internal and external timing signals can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram of a semiconductor device showing an embodiment of the present invention and an operation time chart, FIG. 2 is a temperature dependence characteristic diagram of junction leakage current, and FIGS. 3 and 4 are other examples of the present invention. 5 is a block diagram of a semiconductor device showing an embodiment, FIG.
6 and 6 are logic circuit diagrams of the timing signal generation circuit of the signal processing start signal generation circuit of FIGS. 3 and 4, respectively. FIG. 7 is an operation time chart of FIG. 3, and FIG. 8 is FIG. ，
FIG. 9 is a diagram showing a specific example of the signal processing circuit shown in FIGS.
FIG. 10 and FIG. 10 are RAMs showing other specific examples of the signal processing circuit.
FIG. 11, FIG. 12, FIG. 13 and FIG. 13 showing the structure of the 1-bit portion of FIG. 11 are a characteristic view and a sectional view of a semiconductor device showing another embodiment of the present invention. 1, 14, 17: signal processing circuit, 2, 20, 23, 3
0: charge supply circuit, 15, 18: signal processing start signal generation circuit, 19: timing signal generation circuit, 21, 25
26 and 34: charge holding nodes, 37 and 38: delay circuits.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI Technical display location 6741-5L G11C 11/40 Z 8728-4M H01L 27/10 325 R

Claims (3)

[Claims] 1. A signal processing circuit, a detection circuit for detecting a change in the state of an input signal to the signal processing circuit, and a predetermined circuit node of the signal processing circuit in response to a detection signal from the detection circuit. Supply control means for controlling the charge supply of the first conductivity type, the first conductivity type first well region formed in the second conductivity type first well region formed on the first conductivity type semiconductor substrate. Circuit regions for holding charges of the signal processing circuit are formed by the impurity region of the signal processing circuit, and are formed in the second well region of the second conductivity type formed on the semiconductor substrate of the first conductivity type. The drain region of the MOS transistor performing the saturation operation of the signal processing circuit is formed by the second impurity region of the first conductivity type, and the second well region of the second conductivity type is provided immediately below the drain region of the MOS transistor. Within By forming the first conductivity type protrusion region protruding from the first conductivity type semiconductor substrate, minority carriers from the drain region are absorbed by the protrusion region, and the second conductivity type first region is formed. Is formed between the second well region of the second conductivity type and the second well region of the second conductivity type to prevent the minority carriers from passing from the second well region to the first well region. A semiconductor device, characterized in that the signal processing circuit and the supply control means are operated in a temperature range of 200 K or less. 2. A high impurity of the second conductivity type in the first well region of the second conductivity type immediately below the first impurity region of the first conductivity type as the circuit node for holding the charge. The semiconductor device according to claim 1, wherein the formation of the concentration-embedded layer reduces the number of minority carriers reaching the circuit node for holding the electric charge. 3. The circuit node for holding the charge is a memory
The MOS transistor formed in an array region and performing the saturation operation is formed in a peripheral circuit region, and the memory array region and the peripheral circuit region are separated by the insulator region. The semiconductor device according to the first or second range.