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JPH0656845B2 - Method for manufacturing semiconductor device - Google Patents
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JPH0656845B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JPH0656845B2
JPH0656845B2 JP58038571A JP3857183A JPH0656845B2 JP H0656845 B2 JPH0656845 B2 JP H0656845B2 JP 58038571 A JP58038571 A JP 58038571A JP 3857183 A JP3857183 A JP 3857183A JP H0656845 B2 JPH0656845 B2 JP H0656845B2
Authority
JP
Japan
Prior art keywords
wafer
wafers
semiconductor
photosensitive resin
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58038571A
Other languages
Japanese (ja)
Other versions
JPS59161825A (en
Inventor
幸夫 園部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP58038571A priority Critical patent/JPH0656845B2/en
Publication of JPS59161825A publication Critical patent/JPS59161825A/en
Publication of JPH0656845B2 publication Critical patent/JPH0656845B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices

Landscapes

  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は酸素ガスプラズマを用いて感光性樹脂を除去
するウエハプロセスにおいて、反応器内に挿入されたウ
エハへの物理的損傷を防止するようにした半導体素子の
製造方法に関するものである。
Description: TECHNICAL FIELD The present invention is intended to prevent physical damage to a wafer inserted in a reactor in a wafer process of removing a photosensitive resin using oxygen gas plasma. The present invention relates to a method of manufacturing the semiconductor device.

〔従来技術〕[Prior art]

最近の半導体素子,特に集積回路の高性能化は飛躍的な
進歩があり、ドライエツチング法あるいはイオン注入法
などのプロセス技術の必要上、感光性樹脂を除去するウ
エハプロセスにおいて、酸素ガスプラズマを用いる方法
が必須の方法として定着している。そして、この種の感
光性樹脂を除去するウエハプロセスでは、その処理能力
あるいは単なる除去作用の目的から複数のウエハを同時
に処理するバツチ方式が用いられる。第1図は従来の半
導体素子の製造方法を示す断面図であり、特に感光性樹
脂を除去するウエハプロセスを示す。同図において、
(1)は石英製の反応管、(2)は複数枚のウエハ(3)を支持
する石英ガラス製のウエハ架台、(4)は酸素ガスの導入
口、(5)は酸素ガスの排気口である。
Owing to the recent progress in the performance improvement of semiconductor elements, especially integrated circuits, oxygen gas plasma is used in the wafer process for removing the photosensitive resin due to the need for process technology such as dry etching or ion implantation. The method is established as an essential method. In a wafer process for removing this type of photosensitive resin, a batch method is used in which a plurality of wafers are simultaneously processed for the purpose of its processing capacity or simple removal action. FIG. 1 is a cross-sectional view showing a conventional method for manufacturing a semiconductor element, and particularly shows a wafer process for removing a photosensitive resin. In the figure,
(1) is a quartz reaction tube, (2) is a quartz glass wafer platform that supports a plurality of wafers (3), (4) is an oxygen gas inlet, and (5) is an oxygen gas outlet. Is.

なお、前記ウエハ(3)に示した矢印はウエハ表面の向き
を示し、ウエハ(3)はすべて一定の方向に向つて配置さ
れている。
The arrows shown on the wafer (3) indicate the direction of the wafer surface, and the wafers (3) are all arranged in a fixed direction.

次に、上記構成による感光性樹脂を除去するウエハプロ
セスでは、例えば周波数13.56MHZ,放電出力1K
W,酸素ガス圧2Torrの条件下で操作される。
Next, in the wafer process for removing the photosensitive resin having the above configuration, for example, the frequency is 13.56 MHz, the discharge output is 1 K.
It is operated under the conditions of W and oxygen gas pressure of 2 Torr.

しかしながら、従来の半導体素子の製造方法では、極在
するプラズマ放電の不均一により、励起された分子ある
いは電子などの衝撃がウエハ間で不均一になる。この衝
撃により受けるウエハへの物理的損傷により、半導体素
子の電気的特性が変化し、ウエハ間での電気的特性が不
均一になる。時にMOS型トランジスタを用いた半導体
素子ではシリコンウエハ基板上のシリコン酸化膜中への
影響により、シリコン酸化膜のエネルギー準位を変化さ
せ、代表的な素子の特性である閾値電圧(VTH)を変化
させる。すなわち、第2図は例えば周波数13.56MH
Z,放電出力1KW,酸素ガス圧2Torrの条件下で、MO
S型トランジスタの製造工程中、ゲート用のシリコン酸
化膜生成後、60分間プラズマ放電中に暴露させたときの
閾値電圧(VTH)を、ウエハ架台(2)上のウエハ(3)の位
置により、プロツトしたものである。この第2図におい
て、横軸のNo.1〜No.25はウエハ架台(2)上のウエハ
(3)の順番を示し、縦軸は閾値電圧(VTH)を示すが、
(A)はNチヤネルMOSトランジスタの場合を示し、(B)
はPチヤネルMOSトランジスタの場合を示す。この第
2図により、ウエハ架台(2)上の最も端に位置するNo.1
のウエハの特性が異常であることがわかり、しかも片側
端であることがわかる。このように、従来ではウエハ架
台(2)上のウエハの位置が最も端に位置するウエハの閾
値電圧(VTH)が変化する欠点があつた。
However, in the conventional method of manufacturing a semiconductor device, the impact of excited molecules or electrons becomes non-uniform between wafers due to the non-uniformity of the localized plasma discharge. Due to the physical damage to the wafers caused by this impact, the electrical characteristics of the semiconductor elements change, and the electrical characteristics between the wafers become non-uniform. At times, in a semiconductor device using a MOS transistor, the energy level of the silicon oxide film is changed due to the influence on the silicon oxide film on the silicon wafer substrate, and the threshold voltage (V TH ) which is a typical device characteristic is changed. Change. That is, FIG. 2 shows a frequency of 13.56 MH, for example.
MO under the conditions of Z, discharge output 1KW and oxygen gas pressure 2 Torr
During the manufacturing process of the S-type transistor, the threshold voltage (V TH ) when exposed for 60 minutes during plasma discharge after the silicon oxide film for the gate is formed depends on the position of the wafer (3) on the wafer mount (2). , Is a plot. In FIG. 2, Nos. 1 to 25 on the horizontal axis are wafers on the wafer mount (2).
The order of (3) is shown, and the vertical axis shows the threshold voltage (V TH ).
(A) shows the case of N channel MOS transistor, (B)
Shows the case of a P channel MOS transistor. According to this FIG. 2, No. 1 located at the end on the wafer mount (2)
It can be seen that the wafer characteristic is abnormal, and that it is one side edge. As described above, conventionally, there is a drawback that the threshold voltage (V TH ) of the wafer located at the end of the wafer pedestal (2) changes.

〔発明の概要〕[Outline of Invention]

したがつて、この発明の目的は反応器内に挿入された複
数枚のウエハを物理的損傷させることなく、しかもウエ
ハの置かれた位置にかかわらず、すべてのウエハが一定
の閾値電圧(VTH)をもつように形成することができる
半導体素子の製造方法を提供するものである。
Therefore, the object of the present invention is to prevent a plurality of wafers inserted in a reactor from being physically damaged, and to make sure that all wafers have a constant threshold voltage (V TH The present invention provides a method for manufacturing a semiconductor device that can be formed so as to have

このような目的を達成するため、この発明は半導体素子
の製造工程中、酸素ガスプラズマにより感光性樹脂を除
去する工程において、複数枚のウエハを反応器内に均等
に平行に、かつそのウエハ表面が一方向に向くように配
置すると共に最端部にある1枚のウエハのみ、そのウエ
ハ表面が隣接する半導体ウエハの表面と対向するように
上記一方向とは反対方向に配置するものである。さらに
また、最端部にあるウエハ表面に対向して半導体ウエハ
間隔とほぼ同じ間隔で遮蔽板を配置したものである。以
下実施例を用いて詳細に説明する。
In order to achieve such an object, according to the present invention, in the process of removing a photosensitive resin by oxygen gas plasma during a process of manufacturing a semiconductor device, a plurality of wafers are evenly parallel in a reactor and the wafer surface thereof is Are arranged so as to face in one direction, and only one wafer at the outermost end is arranged in a direction opposite to the one direction so that the wafer surface faces the surface of an adjacent semiconductor wafer. Furthermore, a shielding plate is arranged so as to face the wafer surface at the outermost end and at an interval substantially the same as the semiconductor wafer interval. This will be described in detail below with reference to examples.

〔発明の実施例〕Example of Invention

第3図はこの発明に係る半導体素子の製造方法の一実施
例を示す概略断面図であり、特にMOS型トランジスタ
の製造工程中、ウエハ架台(2)に複数枚のウエハ(3)を配
置し、感光性樹脂を除去するウエハプロセスを示す。こ
の実施例では複数枚のウエハ(3)をウエハ架台(2)上に均
等に平行に、かつそのウエハ表面が一方向に向くように
配置すると共に最端部にある1枚のウエハのみ、そのウ
エハ表面が内側に向くように配置する。これにより、両
端のウエハともその表面が内側に向くことになる。
FIG. 3 is a schematic cross-sectional view showing an embodiment of a method for manufacturing a semiconductor device according to the present invention. Particularly, during the manufacturing process of a MOS type transistor, a plurality of wafers (3) are arranged on a wafer mount (2). Shows a wafer process for removing the photosensitive resin. In this embodiment, a plurality of wafers (3) are evenly arranged on the wafer pedestal (2) so that their wafer surfaces face in one direction, and only one wafer at the end is Arrange so that the wafer surface faces inward. As a result, the surfaces of the wafers at both ends face inward.

そして、感光性樹脂を除去する場合、例えば周波数1
3.56MHZ,放電出力1KW,酸素ガス圧2Torrの条件
下で、MOS型トランジスタの製造工程中、ゲート用の
シリコン酸化膜生成後60分間プラズマ放電中に暴露さ
せたときの閾値電圧(VTH)をウエハ架台(2)上のウエ
ハ(3)の位置によりプロツトしたものを第4図に示す。
この第4図において、横軸のNo.1〜No.25はウエハ架
台(2)上のウエハ(3)の順番を示し、縦軸は閾値電圧(V
TH)を示すが、(A)はNチヤネルMOSトランジスタの
場合を示し、(B)はPチヤネルMOSトランジスタの場
合を示す。この第4図により、ウエハ架台(2)上に配置
された複数枚のウエハ(3)の感光性樹脂を除去すること
ができ、しかもその閾値電圧(VTH)をほぼ均一にする
ことができる。
When removing the photosensitive resin, for example, frequency 1
Under the conditions of 3.56 MHZ, discharge output of 1 KW, and oxygen gas pressure of 2 Torr, the threshold voltage (V TH ) when exposed to plasma discharge for 60 minutes after the formation of the silicon oxide film for the gate during the manufacturing process of the MOS transistor. FIG. 4 shows a plot of the wafer depending on the position of the wafer (3) on the wafer mount (2).
In FIG. 4, No. 1 to No. 25 on the horizontal axis indicate the order of the wafer (3) on the wafer mount (2), and the vertical axis indicates the threshold voltage (V
Show TH), (A) shows the case of N channel MOS transistors, shows the case of (B) is P-channel MOS transistor. According to this FIG. 4, the photosensitive resin of the plurality of wafers (3) arranged on the wafer mount (2) can be removed, and the threshold voltage (V TH ) can be made substantially uniform. .

第5図は他の実施例を示す概略断面図である。同図にお
いて、(6a)および(6b)は前記ウエハ架台(2)の両端部に
設置した例えば厚さ1mm程度で、ウエハ(3)の形状とほ
ぼ同一形状の遮蔽板である。
FIG. 5 is a schematic sectional view showing another embodiment. In the figure, (6a) and (6b) are shielding plates installed at both ends of the wafer mount (2), having a thickness of, for example, about 1 mm and having substantially the same shape as the shape of the wafer (3).

なお、この遮蔽板(6a)および(6b)はウエハ(3)の配置間
隔とほぼ同じ間隔で設置した場合を示す。
The shield plates (6a) and (6b) are shown installed at substantially the same intervals as the wafer (3).

このように、遮蔽板(6a)および(6b)を配置することによ
り、例えば周波数13.56MHZ,放電出力1KW,酸素
ガス圧2Torrの条件下で、MOS型トランジスタの製造
工程中、ゲート用のシリコン酸化膜生成後、60分間プ
ラズマ放電中に暴露させたとき、第4図と同様な特性が
得られた。このように、ウエハ架台(2)上に配置された
複数枚のウエハ(3)の感光性樹脂を除去することがで
き、しかも、その閾値電圧(VTH)をほゞ均一にするこ
とができる。
By arranging the shielding plates (6a) and (6b) in this manner, for example, under the conditions of frequency 13.56MHZ, discharge output 1KW, oxygen gas pressure 2 Torr, silicon for gate during the manufacturing process of the MOS type transistor. When exposed to plasma discharge for 60 minutes after the oxide film was formed, the same characteristics as in FIG. 4 were obtained. Thus, the photosensitive resin of the plurality of wafers (3) arranged on the wafer mount (2) can be removed, and the threshold voltage (V TH ) can be made almost uniform. .

なお、上述の実施例では遮蔽板を2枚設けた場合を示し
たが、そのウエハ表面が必ず一定の方向に向くように配
列した場合、例えば図示の方向に配列した場合には遮蔽
板(6b)は必ずしも必要とせず、同様に、図示の方向の反
対の方向に配列する場合には遮蔽板(6a)は必ずしも必要
としないことはもちろんである。また、前記遮蔽板(6
a),(6b)は着脱自在に設けても,固定して設けてもよ
い。
In the above-described embodiment, the case where two shield plates are provided is shown. However, when the wafer surfaces are arranged so as to always face in a certain direction, for example, when the wafer surfaces are arranged in the illustrated direction, the shield plates (6b ) Is not always necessary, and similarly, the shield plate (6a) is not necessarily required when the elements are arranged in the direction opposite to the illustrated direction. In addition, the shielding plate (6
A) and (6b) may be provided detachably or fixedly.

〔発明の効果〕〔The invention's effect〕

以上詳細に説明したように、この発明に係る半導体素子
の製造工程によれば酸素ガスプラズマを用いた感光性樹
脂を除去するウエハプロセスにおいて、複数枚のウエハ
の特性を均一にすることができるので、高集積度,高性
能化素子のゲート酸化膜の薄膜化など、プラズマ損傷を
受けやすいプロセスに特に効果がある。
As described in detail above, according to the semiconductor element manufacturing process of the present invention, the characteristics of a plurality of wafers can be made uniform in the wafer process of removing the photosensitive resin using oxygen gas plasma. It is especially effective for processes susceptible to plasma damage, such as thinning of the gate oxide film for high integration and high performance devices.

【図面の簡単な説明】[Brief description of drawings]

第1図は従来の半導体素子の製造方法を示す断面図、第
2図は第1図の各ウエハ位置における各ウエハの閾値電
圧(VTH)を示す図、第3図はこの発明に係る半導体素子
の製造方法の一実施例を示す概略断面図,第4図は第3
図の各ウエハ位置における各ウエハの閾値電圧(VTH)を
示す図、第5図は他の実施例を示す概略断面図である。 (1)……反応管、(2)……ウエハ架台、(3)……ウエハ、
(4)……導入口、(5)……排気口、(6a),(6b)……遮蔽
板。
FIG. 1 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device, FIG. 2 is a view showing a threshold voltage (V TH ) of each wafer at each wafer position in FIG. 1, and FIG. 3 is a semiconductor according to the present invention. FIG. 4 is a schematic sectional view showing an embodiment of a method for manufacturing the device,
FIG. 5 is a diagram showing the threshold voltage (V TH ) of each wafer at each wafer position in the figure, and FIG. 5 is a schematic sectional view showing another embodiment. (1) …… Reaction tube, (2) …… Wafer mount, (3) …… Wafer,
(4) …… Inlet port, (5) …… Exhaust port, (6a), (6b) …… Shield plate.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】半導体素子の製造工程中、酸素ガスプラズ
マにより、半導体ウエハ表面に形成された感光性樹脂を
除去する工程において、複数枚の上記半導体ウエハを反
応器内に均等に平行に、かつその半導体ウエハ表面が一
方向に向くように配置すると共に最端部にある1枚の半
導体ウエハのみ、その半導体ウエハ表面が隣接する半導
体ウエハの表面と対向するように上記一方向とは反対方
向に配置され、酸素ガスプラズマにより感光性樹脂を除
去することを特徴とする半導体素子の製造方法。
1. A method of removing a photosensitive resin formed on a surface of a semiconductor wafer by oxygen gas plasma during a manufacturing process of a semiconductor device, wherein a plurality of the semiconductor wafers are evenly parallel in a reactor, and The semiconductor wafer surface is arranged so as to face in one direction, and only one semiconductor wafer at the end is arranged in a direction opposite to the one direction so that the semiconductor wafer surface faces the surface of an adjacent semiconductor wafer. A method of manufacturing a semiconductor element, wherein the semiconductor element is disposed and the photosensitive resin is removed by oxygen gas plasma.
JP58038571A 1983-03-07 1983-03-07 Method for manufacturing semiconductor device Expired - Lifetime JPH0656845B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58038571A JPH0656845B2 (en) 1983-03-07 1983-03-07 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58038571A JPH0656845B2 (en) 1983-03-07 1983-03-07 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS59161825A JPS59161825A (en) 1984-09-12
JPH0656845B2 true JPH0656845B2 (en) 1994-07-27

Family

ID=12528976

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58038571A Expired - Lifetime JPH0656845B2 (en) 1983-03-07 1983-03-07 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH0656845B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01137529U (en) * 1988-03-14 1989-09-20

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS511732U (en) * 1974-06-19 1976-01-08
JPS5143718U (en) * 1974-09-27 1976-03-31
JPS542670A (en) * 1977-06-08 1979-01-10 Nec Corp Plasma etching method
JPS5752907Y2 (en) * 1979-05-24 1982-11-17
JPS5735322A (en) * 1980-08-13 1982-02-25 Fujitsu Ltd Removal of photo-resist film
JPS5738920U (en) * 1980-08-14 1982-03-02

Also Published As

Publication number Publication date
JPS59161825A (en) 1984-09-12

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