JPH0656879B2 - Semiconductor integrated circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit used for a semiconductor memory, a semiconductor logic or the like.

[Conventional technology]

Conventionally, in this kind of semiconductor integrated circuit, when the power is turned on (especially, when the power is cut off and then turned on again), unnecessary charges are left in or remain at nodes (so-called nodes) of various parts of the circuit. Sometimes.

In such a case, there is a problem that the charge interferes with the initialization of the circuit, and the circuit operation thereafter may not be performed normally.

[Problems to be solved by the invention]

The present invention has been made in view of the above problems, and based on the idea of removing unnecessary charges existing at the circuit node only when the power is turned on, the potential of the circuit node is once set to the reference potential when the power is turned on. , Is designed to ensure that the circuit is properly initialized.

[Means for solving problems]

According to the present invention, a means for generating a signal for detecting that the power is turned on, and a potential of the circuit node by removing an unnecessary charge existing in a predetermined circuit contact when the power is turned on based on the detection signal. And a means for temporarily setting the voltage to a reference potential.

[Work]

According to the above configuration of the present invention, it is possible to remove an unnecessary charge existing at a predetermined circuit node when the power is turned on based on a signal for detecting that the power is turned on. Once set to the reference potential, normal initialization of the circuit is surely performed when the power is turned on.

〔Example〕

FIG. 1 shows, as an embodiment of a semiconductor integrated circuit according to the present invention, a circuit for removing unnecessary charges from a predetermined circuit node (Nφ) at power-on and temporarily setting the potential of the circuit node Nφ to a reference potential. 1 shows an example.

As shown in the figure, the power source V _CC (normally 5 V) side and V _SS
A capacitor 3 (usually formed between the gate and the source / drain of the MOS transistor) is connected to the (normal ground potential) side, and an MO whose gate is connected to the V _CC side.
A MOS transistor whose S transistor 2 is connected in series, and whose gate is connected to a connection point N ₁ between the capacitor 3 and the MOS transistor 2 between the circuit node Nφ and the V _SS. 1 is connected.

When the power is turned on in this circuit, the potential at the point N ₁ capacitively coupled to the V _CC side by the capacitor 3 once rises as the power supply voltage V _CC rises, as shown in FIG. As a result, the gate potential of the transistor 1 becomes high level, the transistor 1 becomes conductive, and the node Nφ is discharged. Therefore, the potential of the node Nφ gradually decreases and reaches Ov as shown in FIG. 3, and the circuit is initialized.

On the other hand, the gate potential of the transistor 2 also gradually becomes high level and the transistor 2 also becomes conductive. In this case, by selecting the transistor 2 through which a current of an appropriate value flows, it becomes equivalent to connecting a resistor of a predetermined value between the N ₁ point and the V _SS , and the N ₁ point is It will be charged to the V _SS side, that is, the negative side through the resistor, and the N ₁
The potential at the point often drops to Ov. In this way, if the potential at the N ₁ point is set to be equal to or lower than the threshold voltage of the transistor 1 by the time the normal operation of the circuit is started, the adverse effect on the node N φ during normal operation is eliminated.

FIG. 2 shows another embodiment of the semiconductor integrated circuit according to the present invention. As shown in FIG.
Instead of directly connecting the gate of V _CC to the V _CC side, a transistor 4 whose gate is connected to the V _CC side is further added between the gate of the transistor 2 and the V _CC . When the power supply voltage V _CC fluctuates during normal operation and further rises above the steady value (5 V), the operation for removing the charge at the node Nφ, which is the case when the power is turned on, is not performed. .

That is, when the power is first turned on in the circuit shown in FIG. 2, the potential of the point N ₁ capacitively coupled to the V _CC side by the capacitor 3 becomes equal to the power supply voltage V _CC as shown in FIG. It rises once with rising, whereby the gate potential of the transistor 1 becomes high level, the transistor 1 becomes conductive, and the charge at the node Nφ is discharged. Therefore, the potential of the node Nφ gradually decreases to reach Ov as shown in FIG. 4, and the circuit is initialized as in the circuit shown in FIG. 1.

However, in the structure shown in FIG. ₂ , the potential at the connection point N ₂ between the gate of the transistor 2 and the transistor 4 is approximately (V _CC −V _TH ), where V _TH is
And the threshold voltage of 4], the transistor 2 becomes conductive when the power supply voltage V _CC becomes approximately 2V _TH or more, and the potential at the N ₁ point is discharged by the current flowing through the transistor 2 and drops to Ov. However, the transistor 1 is turned off (in this case, the characteristics of the transistor 2 are selected so as to drop relatively quickly).

Therefore, when the power supply voltage V _CC rises to 2 V _TH or more, the potential at the N ₁ point does not rise any more. Therefore, during normal operation, the power supply voltage fluctuates as shown in FIG. If the voltage rises above the steady value (5V), the potential at the point N ₁ does not rise and the transistor 1 does not conduct, so that the node Nφ is not adversely affected.

Next, application examples in which the above-described circuit of the present invention is actually applied will be described with reference to FIGS.

The circuit shown in FIG. 5 is a circuit (normally called a buffer circuit) for outputting a signal TO having a fixed width for a certain purpose in response to a short pulse of an external input signal.
Such a circuit simplifies the method of inputting an external input signal in a semiconductor memory integrated circuit or a semiconductor logic integrated circuit, and even if a short pulse is input, a certain circuit operation, for example, a memory read operation is completed. This is useful for allowing the time to be determined by the integrated circuit itself.

FIG. 6 shows the operation waveform of each part in this circuit. When the power is turned on, the external input signal applied to the gate of the transistor Q ₂ shown in FIG. 5 (a) changes from high level to high level. If it changes to low level, A1
As shown in FIG. 6, the potential at the point has a waveform obtained by substantially inverting the external input signal, while the potential at the point A2 drops as the potential at the point A1 rises. Then the output signal TO of the dynamic buffer 13 the potential of the point A2 is shown in FIG. 5 (b) at the time of the drop is applied to the gate of the transistor Q ₅ in the high level state, subsequent the point A1 Even if the potential drops, the potential at the point A2 is maintained at a low level. The potential at the point A3 is almost the same as the potential at the point A2.

Next, the potential at the point A3 is input to the dynamic buffer 11 shown in FIG. The dynamic buffers 11 to 12 function as a delay circuit as will be described later, whereby the input A3 of the dynamic buffer 11 is delayed by a predetermined time to produce an output A4, and similarly delayed sequentially. Dynamic type buffer 1
An output R is generated from the output side of 2 and the output R is applied to the dynamic buffer 13 as a first reset signal.

The dynamic type buffer 13 has A in FIG. 5 (a).
The potential at one point (inverted external input signal) is input, and after the potential at the A1 point becomes high level, a high level output TO is produced with a delay for a predetermined time, and as shown in FIG. The high level is maintained until the first reset signal R is applied. When the output TO becomes low level, the potential at point A2 in FIG. 5 (a) becomes high level, and the potential A2 changes to the dynamic buffers 11 to 12.
And the second reset signal of the dynamic buffer 13 to initialize each dynamic buffer.

Here, each of the dynamic buffers 11 to 12 is constructed, for example, as shown in FIG. 9, and the operation waveform of each part thereof is shown in FIG. The first
As is apparent from FIG. 0, by inputting a high level input signal φi (for example, corresponding to the input A3 of the dynamic buffer 11), the output signal φ _O after a predetermined time has elapsed
Therefore, this can also be used as a delay circuit. The output signal φ _O (e.g., corresponding to the output A4 of the dynamic buffer 11) is kept at a high level until a high-level reset signal φ _R (e.g., corresponding to the reset signal A2 of the dynamic buffer 11) is applied. It

This dynamic buffer has a high level input signal φ.
It is necessary to set the reset signal φ _R to a high level before i is applied. This signal causes the potentials at points B1, B4 and B5 in FIG. 9 to go to a low level.
On the other hand, the potentials at points B2 and B3 must be reset to a high level, and after being reset to this state, the reset signal φ _{R is set} to a low level and the input signal φi is set to a high level, the potentials at the points in FIG. The output φ _O is obtained after a predetermined time after the change as shown in FIG.

Further, the dynamic type buffer 13 is generally constructed as shown in FIG. 11, and when a high level input signal A1 is inputted, an output signal TO having a constant width is generated after a lapse of a predetermined time. Then, when the high-level reset signal R is applied, the output TO becomes low level and is in a reset state, but it is reset by the reset signal A2 when the power is turned on.

As described above, when the power is turned on, the output TO of the dynamic buffer 13 is normally at a low level in FIG. 5, and in such a case, as shown in FIG. The reset signal A2 corresponding to the potential at the point A2 becomes high level, and the dynamic buffers 11 to 12 and 13 are reset. Then, after the reset signal A2 is set to the low level and the external input signal is set to the low level (that is, the signal A1 is set to the high level), the series of circuits shown in FIG. 5 will operate normally as shown in FIG. , And outputs an output signal TO having a constant width determined by the dynamic buffers 11 to 12.
Thus, in order for the circuit of FIG. 5 to operate normally when the light bulb is turned on, it is necessary to reset each buffer once by the reset signal A2.

In this way, if the power is turned off for a long time, when the power is turned on again, the output signal TO is at the low level, so that the circuit of FIG. When the power supply is cut off in the level state, the output signal TO may remain at the high level. In such a case, the reset signal A2 does not become high level as shown in FIG.
Therefore, after that, even if an external input signal appears (becomes low level), the circuit of FIG. 5 does not operate normally, and the situation does not change even if the external input signal is input a plurality of times.

On the other hand, FIG. 12 shows a circuit of the present invention applied to a dynamic buffer 13 having a conventional structure as shown in FIG. 11 so that its output signal TO is always at a low level when power is turned on. is there.

That is, in the structure shown in FIG. 12, compared with the conventional example shown in FIG. 11, a transistor Q ₄₈ and a transistor Q ₄₈ are provided to the output side TO and the gate (point C4) of Q ₄₆ to charge up the output side, respectively. Q ₄₉ (Fig. 1 or 2
The transistor 1 of the circuit of the present invention shown in the figure is connected (the gate side N of each transistor 48, 49).
₁ corresponds to point N _{1 in} FIG. 1 or FIG. 2), so that even if the output side TO is at the high level when the power is turned on as described above, the output side TO is always set to the low level once. The circuit operation in this case is shown in FIG. 8), and the above-mentioned inconvenience is avoided.

〔The invention's effect〕

According to the present invention, unnecessary charges existing at a predetermined circuit node of a semiconductor integrated circuit can be removed when the power is turned on, so that the potential of the circuit node can be once set to the reference potential, and when the power is turned on. The normal initialization of the circuit can be surely performed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing one embodiment of a semiconductor integrated circuit according to the present invention, FIG. 2 is a circuit diagram showing another embodiment of a semiconductor integrated circuit according to the present invention, and FIG. FIG. 4 is a diagram showing operation waveforms of respective parts of the circuit shown in FIG. 4, FIG. 4 is a diagram showing operation waveforms of respective parts of the circuit of FIG. 2, and FIGS. 5 (a) and 5 (b) are semiconductor integrated circuits of the present invention. FIG. 6 is a diagram showing a buffer circuit as an example that is actually applied, FIG. 6 is a diagram showing operation waveforms of respective parts when the circuit of FIG. 5 operates normally at power-on, and FIG. FIG. 8 is a diagram showing operation waveforms of each part when the output side remains high level at power-on in the circuit shown in FIG. 8 (FIG. 8). FIG. 9 is a diagram showing operation waveforms of respective parts in the case of avoiding the above, FIG. 9 shows dynamic type buffers 11 through 11 in the circuit of FIG. 2 is a circuit diagram showing a configuration example of FIG. 2, FIG. 10 is a diagram showing operation waveforms of respective parts of the circuit of FIG. 9, and FIG. 11 is a circuit diagram showing a conventional example of the dynamic buffer 13 in the circuit of FIG. FIG. 12 is a circuit diagram showing an example in which the present invention is applied to the dynamic buffer 13 in the circuit of FIG. (Description of symbols) 1,2,4 ... MOS transistor, 3 ... Capacitor, 11,12,13 ... Dynamic buffer, Nφ ... Circuit node,

Claims (1)

[Claims] 1. A means for generating a signal for detecting that a power source is turned on, and an unnecessary charge existing at a predetermined circuit node is removed at the time of turning on the power source based on the detection signal so as to set a potential of the circuit node. A semiconductor integrated circuit comprising means for once setting a reference potential.