JPH0656950B2 - Gate circuit - Google Patents
Gate circuitInfo
- Publication number
- JPH0656950B2 JPH0656950B2 JP61181614A JP18161486A JPH0656950B2 JP H0656950 B2 JPH0656950 B2 JP H0656950B2 JP 61181614 A JP61181614 A JP 61181614A JP 18161486 A JP18161486 A JP 18161486A JP H0656950 B2 JPH0656950 B2 JP H0656950B2
- Authority
- JP
- Japan
- Prior art keywords
- mosfet
- output terminal
- electrode
- source
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000005684 electric field Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000007599 discharging Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
Landscapes
- Logic Circuits (AREA)
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Electronic Switches (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は、ＭＯＳＦＥＴ集積回路で用いられるゲート回
路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate circuit used in a MOSFET integrated circuit.
（従来の技術） ＭＯＳＦＥＴ集積回路が高密度化されるにつれ、それを
構成するＭＯＳＦＥＴも微細になってきた。それに伴な
い、いわゆるホットキャリア効果が問題になってきた。
これは素子内の電界が強まることによって、ＭＯＦＦＥ
Ｔの信頼性が低下するものである。この効果を抑えるた
めには、電源電圧を下げ電界を弱めれば良いが、集積回
路を組込む装置内でそのような特殊な電源電圧を用意し
にくい等の種々の理由で実行が難かしい。この為、電源
電圧を下げずにホットキャリア効果を回路的に抑制する
方法として、第２図に示すものが提案されている（日経
マイクロデバイス１９８５年夏号４８頁）。(Prior Art) As the density of the MOSFET integrated circuit has been increased, the MOSFETs constituting it have become finer. Along with that, the so-called hot carrier effect has become a problem.
This is because the electric field in the device is strengthened and MOFFE
The reliability of T decreases. In order to suppress this effect, it is sufficient to lower the power supply voltage and weaken the electric field, but it is difficult to execute it for various reasons such as it is difficult to prepare such a special power supply voltage in the device incorporating the integrated circuit. Therefore, a method shown in FIG. 2 has been proposed as a method for suppressing the hot carrier effect in a circuit without lowering the power supply voltage (Nikkei Microdevice, Summer 1985, p. 48).
第２図に於て、ＭＯＳＦＥＴ２１はＮチャネルであり、
ゲート電極に接続された電源２４の電位により常に導通
するようにバイアスされている。ＭＯＳＦＥＴ２２はＮ
チャネルであり、ゲート電極が入力端子１３に接続され
ており、入力端子１３に印加される入力により導通した
り遮断したりし、出力端子１４上の出力はＭＯＳＦＥＴ
２２の状態により変化する。この回路によると、出力端
子１４と電源ＶSSの間の電圧がＭＯＳＦＥＴ２１と２２
により分割され、ＭＯＳＦＥＴ２１及び２２の各々のソ
ース・ドレイン間には大きな電圧は加わらず、従ってＭ
ＯＳＦＥＴ内の電界が低く抑えられ、ホットキャリア効
果を抑制できる。In FIG. 2, the MOSFET 21 is an N channel,
It is biased so as to be always conductive by the potential of the power supply 24 connected to the gate electrode. MOSFET 22 is N
A channel, whose gate electrode is connected to the input terminal 13, conducts or cuts off by the input applied to the input terminal 13, and the output on the output terminal 14 is a MOSFET.
It changes according to the state of 22. According to this circuit, the voltage between the output terminal 14 and the power supply V SS is MOSFETs 21 and 22.
And a large voltage is not applied between the source and drain of each of the MOSFETs 21 and 22.
The electric field in the OSFET can be suppressed low, and the hot carrier effect can be suppressed.
（発明が解決しようとする問題点） しかしながら、第２図の回路には、実用上次の問題点が
ある。(Problems to be Solved by the Invention) However, the circuit of FIG. 2 has the following practical problems.
第１に、出力端子１４に接続された負荷容量をＭＯＳＦ
ＥＴ２１と２２を通して放電する際に、ＭＯＳＦＥＴ２
１が無く出力端子１４が直接ＭＯＳＦＥＴ２２のドレイ
ン電極に接続されている場合に比較し、動作速度が遅く
なる。第２に、回路の状態が変化する時に、ＭＯＳＦＥ
Ｔ２１と２２の各電極に過渡的に加わる電位は、出力端
子１４に接続される負荷容量の大きさと、入力端子１３
に印加される入力の波形の複雑な関数であり、第２図の
回路はどのような場合に対しても電界を充分小さく抑え
ることを保証するものではない。First, the load capacitance connected to the output terminal 14 is connected to the MOSF.
When discharging through ET21 and 22, MOSFET2
The operation speed becomes slower than in the case where the output terminal 14 is directly connected to the drain electrode of the MOSFET 22 because there is no 1. Second, when the state of the circuit changes, the MOSFE
The potential that is transiently applied to the electrodes of T21 and T22 depends on the magnitude of the load capacitance connected to the output terminal 14 and the input terminal 13
2 is a complex function of the input waveform applied to, and the circuit of FIG. 2 does not guarantee that the electric field will be kept sufficiently small in any case.
本発明はこの点に鑑み、電源電圧を下げることなくホッ
トキャリア効果を抑制し、かつ動作速度も低下せず、ど
のような場合にもＭＯＳＦＥＴ内の電界が充分小さいこ
とを原理的に保証する、ゲート回路を提供することを目
的とする。In view of this point, the present invention theoretically guarantees that the hot carrier effect is suppressed without lowering the power supply voltage, the operating speed does not decrease, and the electric field in the MOSFET is sufficiently small in any case. An object is to provide a gate circuit.
（問題点を解決するための手段） 本発明が前述の問題点を解決するために提供する手段
は、ドレイン電極を第１の電源に接続しゲート電極とソ
ース電極を互いに接続した第１のＭＯＳＦＥＴと、ドレ
イン電極を前記第１のＭＯＳＦＥＴのゲート電極とソー
ス電極に接続しゲート電極を第２の電源に接続しソース
電極を出力端子に接続した第２のＭＯＳＦＥＴと、ドレ
イン電極を前記出力端子に接続しゲート電極を入力端子
に接続した第３のＭＯＳＦＥＴと、ドレイン電極とゲー
ト電極を前記第３のＭＯＳＦＥＴのソース電極に接続し
た第４のＭＯＳＦＥＴと、ドレイン電極を前記第４のＭ
ＯＳＦＥＴのソース電極に接続しゲート電極とソース電
極を第３の電源に接続した第５のＭＯＳＦＥＴとを具備
し、前記第１及び第５のＭＯＳＦＥＴはデプレッション
型素子でなることを特徴とするゲート回路である。(Means for Solving the Problems) The means provided by the present invention for solving the above-mentioned problems is a first MOSFET in which a drain electrode is connected to a first power supply and a gate electrode and a source electrode are connected to each other. A second MOSFET having a drain electrode connected to a gate electrode and a source electrode of the first MOSFET, a gate electrode connected to a second power source, and a source electrode connected to an output terminal; and a drain electrode connected to the output terminal. A third MOSFET having a gate electrode connected to the input terminal, a fourth MOSFET having a drain electrode and a gate electrode connected to the source electrode of the third MOSFET, and a drain electrode having the fourth M
A gate circuit comprising a fifth MOSFET having a gate electrode connected to a source electrode of the OSFET and a source electrode connected to a third power supply, wherein the first and fifth MOSFETs are depletion type elements. Is.
（実施例） 次に実施例を挙げ本発明を一層詳しく説明する。(Example) Next, an Example is given and this invention is demonstrated in more detail.
第１図は本発明の一実施例を示す回路図である。この実
施例に於いて、ＭＯＳＦＥＴ１，５はデプレッション型
素子であり、ＭＯＳＦＥＴ２，３，４はエンハンスメン
ト型素子である。FIG. 1 is a circuit diagram showing an embodiment of the present invention. In this embodiment, the MOSFETs 1 and 5 are depletion type elements, and the MOSFETs 2, 3 and 4 are enhancement type elements.
まず、入力端子１３に印加される入力が変化し、ＭＯＳ
ＦＥＴ３が遮断状態から導通状態に変る場合を考える。
この場合、出力端子１４からＭＯＳＦＥＴ３，４，５を
通して電圧源ＶSSに電流が流れ出力端子１４の電位はＶ
SSに向かって変化する。しかし、ＭＯＳＦＥＴ４の閾値
電圧をＶT4とすると、接続点１１の電位がＶSS＋ＶT4に
なるとＭＯＳＦＥＴ４が遮断し、出力端子14の電位はそ
れ以上変化しない。従って、出力端子１４の電位は、Ｖ
SS＋ＶT4までしか変化しない。またこの変化の間ゲート
・ソース間電圧がＯＶに一定のＭＯＳＦＥＴ５の働きに
より流れる電流は一定に保たれ、またこの電流値はＭＯ
ＳＦＥＴ４の有無によらない。First, the input applied to the input terminal 13 changes and the MOS
Consider the case where the FET 3 changes from the cutoff state to the conduction state.
In this case, current flows from the output terminal 14 through the MOSFETs 3, 4, and 5 to the voltage source V SS, and the potential of the output terminal 14 is V
Change towards SS . However, assuming that the threshold voltage of the MOSFET 4 is V T4 , when the potential of the connection point 11 becomes V SS + V T4 , the MOSFET 4 is cut off and the potential of the output terminal 14 does not change any more. Therefore, the potential of the output terminal 14 is V
Only changes up to SS + V T4 . Further, during this change, the current flowing through the MOSFET 5 whose gate-source voltage is constant at OV is kept constant, and this current value is MO.
It does not depend on the presence or absence of SFET4.
次に、入力端子１３に印加される電位によりＭＯＳＦＥ
Ｔ３が導通状態から遮断状態に変化する場合を考える。
この場合、電源ＶDDからＭＯＳＦＥＴ１と２を通じて出
力端子１４に電流が流れ、出力端子１４の電位がＶDDに
向かって変化する。Next, according to the potential applied to the input terminal 13, the MOSFE
Consider the case where T3 changes from the conductive state to the cutoff state.
In this case, a current flows from the power supply V DD through the MOSFETs 1 and 2 to the output terminal 14, and the potential of the output terminal 14 changes toward V DD .
しかし、出力端子１４の電位がＶ１−ＶT2まで上昇した
時ＭＯＳＦＥＴ２が遮断するのでそれ以上上昇しない。
ここで、Ｖ１はＭＯＳＦＥＴ２のゲート電極に印加され
る一定電位、ＶT2はＭＯＳＦＥＴ２の閾値電圧である。
この変化の間、出力端子１４に流れる電流はＭＯＳＦＥ
Ｔ１の働きによりほぼ一定に保たれる。またこの電流値
はＭＯＳＦＥＴ２の有無によらない。However, when the potential of the output terminal 14 rises to V 1 -V T2, the MOSFET 2 shuts off, so that it does not rise any further.
Here, V 1 is a constant potential applied to the gate electrode of MOSFET 2, and V T2 is a threshold voltage of MOSFET 2.
During this change, the current flowing through the output terminal 14 is
It is kept almost constant by the action of T1. Further, this current value does not depend on the presence or absence of MOSFET 2.
以上のように、第１図の回路に於ては出力端子１４の電
位は、ＭＯＳＦＥＴ２及び４の働きにより、ＶSS＋ＶT4
とＶ1−ＶT2との間でしか変化しない。従って、ＭＯＳ
ＦＥＴ１と２のソース・ドレイン間にはＶDD−（ＶSS−
ＶT4）以上の電圧は加わらない。またＭＯＳＦＥＴ３と
４と５のソース・ドレイン間にはＶ1−ＶT2−ＶSS以上
の電圧は加わらない。この為ＶT4，ＶT2，Ｖ1の値を調
整しこれらの電圧を充分低くすることで、ＭＯＳＦＥＴ
内の電界をホットキャリア効果が問題にならない様に弱
くすることができる。また、ＭＯＳＦＥＴ１と５の働き
により、ＭＯＳＦＥＴ２及び４により動作速度が遅くな
るのを防ぐことができる。As described above, in the circuit of FIG. 1, the potential of the output terminal 14 is V SS + V T4 due to the functions of the MOSFETs 2 and 4.
And V 1 -V T2 only. Therefore, MOS
Between the FET1 and the second source-drain V DD - (V SS -
A voltage above V T4 ) is not applied. Further, no voltage higher than V 1 -V T2 -V SS is applied between the sources and drains of the MOSFETs 3, 4 and 5. Therefore, by adjusting the values of V T4 , V T2 , and V 1 to make these voltages sufficiently low, the MOSFET
The internal electric field can be weakened so that the hot carrier effect is not a problem. Further, the functions of the MOSFETs 1 and 5 can prevent the operation speed from being slowed by the MOSFETs 2 and 4.
（発明の効果） 以上に述た如く、本発明によれば、電源電圧を下げずに
ホットキャリア効果を必ず抑制でき、かつ動作速度が遅
くなることのないゲート回路が得られ、微細な素子を用
いたＭＯＳＦＥＴ集積回路に於いて大きな効果がある。(Effects of the Invention) As described above, according to the present invention, it is possible to obtain a gate circuit in which the hot carrier effect can be suppressed without lowering the power supply voltage, and the operation speed does not slow down. There is a great effect in the MOSFET integrated circuit used.
第１図は本発明の一実施例を示す回路図、第２図は従来
例を示す回路図である。 １，２，３，４，５，２１，２２，２３……ＭＯＳＦＥ
Ｔ、１３……入力端子、１４……出力端子。FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional example. 1,2,3,4,5,21,22,23 ... MOSFE
T, 13 ... Input terminal, 14 ... Output terminal.
Claims (1)
電極とソース電極を互いに接続した第１のＭＯＳＦＥＴ
と、ドレイン電極を前記第１のＭＯＳＦＥＴのゲート電
極とソース電極に接続しゲート電極を第２の電源に接続
しソース電極を出力端子に接続した第２のＭＯＳＦＥＴ
と、ドレイン電極を前記出力端子に接続しゲート電極を
入力端子に接続した第３のＭＯＳＦＥＴと、ドレイン電
極とゲート電極を前記第３のＭＯＳＦＥＴのソース電極
に接続した第４のＭＯＳＦＥＴと、ドレイン電極を前記
第４のＭＯＳＦＥＴのソース電極に接続しゲート電極と
ソース電極を第３の電源に接続した第５のＭＯＳＦＥＴ
とを具備し、前記第１及び第５のＭＯＳＦＥＴはテプレ
ッション型素子でなることを特徴とするゲート回路。1. A first MOSFET having a drain electrode connected to a first power supply and a gate electrode and a source electrode connected to each other.
And a drain electrode connected to the gate electrode and source electrode of the first MOSFET, a gate electrode connected to a second power supply, and a source electrode connected to an output terminal
A third MOSFET having a drain electrode connected to the output terminal and a gate electrode connected to the input terminal, a fourth MOSFET having a drain electrode and a gate electrode connected to the source electrode of the third MOSFET, and a drain electrode Is connected to the source electrode of the fourth MOSFET, and the gate electrode and the source electrode are connected to a third power source, a fifth MOSFET
A gate circuit comprising: a first and a fifth MOSFET, each of which is a tepletion type element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61181614A JPH0656950B2 (en) | 1986-07-31 | 1986-07-31 | Gate circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61181614A JPH0656950B2 (en) | 1986-07-31 | 1986-07-31 | Gate circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6337715A JPS6337715A (en) | 1988-02-18 |
| JPH0656950B2 true JPH0656950B2 (en) | 1994-07-27 |
Family
ID=16103880
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61181614A Expired - Lifetime JPH0656950B2 (en) | 1986-07-31 | 1986-07-31 | Gate circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0656950B2 (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57158240U (en) * | 1981-03-31 | 1982-10-05 | ||
| JPS58207728A (en) * | 1982-05-28 | 1983-12-03 | Nec Corp | Transistor circuit |
| JPS60233931A (en) * | 1984-05-07 | 1985-11-20 | Toshiba Corp | Inverter circuit |
-
1986
- 1986-07-31 JP JP61181614A patent/JPH0656950B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6337715A (en) | 1988-02-18 |
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