JPH0656990B2 - Channel pulse generator - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a channel pulse generator used in a PCM terminal device or the like.

[Technical background of the invention]

In the PCM terminal device, a plurality of voice signals are digitized, multiplexed and transmitted as data D having a frame structure as shown in FIG. That is, digitized 8-bit audio data is sequentially arranged for the number of channels (here, 24 channels) after the synchronization signal SYNC.
For this reason, when arranging an 8-bit audio signal on each channel or separating an 8-bit audio signal from each channel, it is necessary to arrange or separate on the corresponding time slot.

Therefore, in the PCM terminal device, as shown in FIG. 4, a transmission synchronization signal (TSYNC), a transmission clock (TCLK), a reception synchronization signal (RSYNC), a reception clock (RCLK) are added to the PCM codec (CODEC) 1 for each channel. Is giving. In the PCM codec 1, the arrangement of the audio signal is started at the rising edge of the transmission cycle signal (TSYNC), and the 8-bit audio signal of the transmission clock (TCLK) is arranged and output. At this time, an analog audio signal is input to the PCM codec 1 from the input terminal AIN, and a digital audio signal is output from the output terminal PCMOUT.
When separating the audio signal, the PCM codec 1 starts the separation of the audio signal in synchronization with the rising edge of the reception synchronization signal (RSYNC), and separates the 8-bit audio signal of the reception clock (RCLK). At this time, a digital audio signal is input from the input terminal PCMIN of the PCM codec 1 and an analog audio signal is output from the output terminal AOUT.

Thus, in the PCM terminal device, the P of one channel is
Transmission sync signal (TSYNC) for CM codec 1
It is necessary to give two channel pulses, that is, a reception synchronization signal (RSYNC). Therefore, since the number of channels is 24 in the PCM terminal equipment of the US-Japan series and 30 in the PCM terminal equipment of the European series, it is necessary to give 48 and 60 channel pulses respectively. .

Conventionally, in a PCM terminal device, all the channel pulse generating parts are provided in a common part, and the PCM codec 1 is provided in the voice channel board for each channel. The transmission of the channel pulse from the common section to each audio channel board has been performed by the connector cable. However, in this device, the number of pins of the connector of the common part is extremely large, such as 48 and 60, and the size of the connector becomes large, which causes a problem that the downsizing of the PCM terminal device is hindered.

Therefore, in order to solve this problem,
Two signals, that is, a frame signal for instructing the start of a frame and a channel clock for instructing the start of each channel are transmitted, and the channel section is initialized by the frame signal and one cycle corresponds to one channel. A counter that counts up with a clock is provided. When one channel is mounted on one channel part, the address of that channel is given to the counter as an initial value, and when multiple channels are mounted on one channel part, the address of the first channel is set as an initial value. It was given to the counter and each channel pulse was generated when the counter was counted up to a certain value by the channel clock.

[Problems of background technology]

However, the counter provided in the channel section
Since the channel clock is counted up by the channel clock for the number of channels and the channel pulse is output when the count value reaches a certain value, the initial value set in each counter must correspond to the total number of channels. did not become. Therefore, the number of signal lines for setting the initial value is equal to the number of bits corresponding to the total number of channels, for example, when the total number of channels is 24, the number of signals is required to be 5, and when the total number of channels increases. , The number of signal lines connected was increasing accordingly. Therefore, the number of connectors to which the signal lines are attached also increases, which hinders the miniaturization of the channel pulse generator.

[Object of the Invention]

It is an object of the present invention to eliminate the above drawbacks and to obtain a channel pulse generator having a small number of signal lines connected to set an initial value of a counter when a plurality of channels are mounted in one channel section. To do.

[Outline of Invention]

According to the present invention, the first channel clock supplied from the channel clock generating means is divided into N (N is a divisor of the total number of channels) to be the second channel clock, and the counter is the timing of the second channel clock. The object is achieved by counting up and outputting a channel pulse when the count value reaches a predetermined value.

Example of Invention

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. 10
Common unit, frame signal generating means 11, 12 is a channel clock generating unit, 13 ₁ to 13 ₃ are channel section 1
4 _{1 to} 14 ₃ are frequency dividers, 15 _{1 to} 15 ₃ are counters, 16 _{1 to} 16 ₃ are 8-bit shift registers, 1
7 ₁ 17 ₃ is a signal line.

The channel pulse generator 20 is assumed to be used in a PCM terminal station device having 24 channels, and the shift registers 16 _{1 to} 16 _{3 are used.}
The channel pulse output from the PCM codec 1 to the PCM codec 24 (not shown) is input.

The frame signal generation means 11 generates a frame signal instructing the start of one frame, and the channel clock generation means generates a first channel clock instructing the start of each channel of one frame. The frequency dividers 14 _{1 to} 14 ₃ frequency-divide the first channel clock by 8 and output it to the counters 15 _{1 to} 15 ₃ as second channel clocks, respectively. The counters 15 _{1 to} 15 ₃ are provided with signal lines 17 _{1 to} 17 _{3 respectively.}
Is given an initial value of 2 bits, and is incremented by 1 by the second channel clock given from the frequency divider 14 _{1 to} frequency divider 14 ₃ so that the count value is “0”.
When it becomes “0”, the first channel pulse is output to the shift registers 16 _{1 to} 16 ₃ . The shift registers 16 _{1 to} 16 ₃ are the first
The channel pulse is shifted at the timing of the first channel clock given from the channel clock generating means 12 and eight channel pulses are output. The above operation will be described with reference to the time chart shown in FIG. Counter 15 by the frame signal outputted from the frame signal generator 11 of the common unit 10 ₁ to the counter 1
5 ₃ is initialized, the count value is 2-bit signal line 17
Set initial value by ₁ to a signal line 17 ₃ "1
It is set to 1 ”,“ 10 ”, and“ 01 ”. Next, by the second channel clock obtained by dividing the first channel clock generated by the channel clock generating means by eight,
The counter values of the counters 15 _{1 to} 15 ₃ are incremented by 1, and are “00”, “11”, and
It becomes "10".

Then the count value is first channel pulse from counter 15 ₁ becomes "00" is input to the shift register 16 _1, the shift register 16 ₁ is shifted to the first channel pulse at the timing of the first channel clock Channel pulses corresponding to channels 1 to 8 are output to PCM codec 1 to PCM codec 8 not shown.

The next second channel clock, counter 15 ₁
To the counter value of the counter 15 ₃ is counted up by one, respectively "01", "00", and "11".

Then the count value is first channel pulse from counter 15 ₂ becomes "00" is input to the shift register 16 _2, the shift register 16 ₂ is shifted to the first channel pulse at the timing of the first channel clock Channel pulses corresponding to channels 9 to 16 are output to PCM codec 9 to PCM codec 16 not shown.

Then the counter value of the counter 15 ₁ to the counter 15 ₃ by the second channel clock is incremented by 1, respectively "10", "01", and "00".

Then the count value is first channel pulse from counter 15 ₃ becomes "00" is input to the shift register 16 _3, the shift register 16 ₃ is shifted to the first channel pulse at the timing of the first channel clock Channel pulses corresponding to the channels 17 to 24 are output to the PCM codec 17 to PCM codec 24 (not shown).

Next, the counters 15 _{1 to} 15 ₃ are initialized by the frame signal output from the frame signal generating means 11, and the count values are initial values “11” and “10” set by the signal lines 17 _{1 to} 17 ₃ . , "01" is reset.

After that, the above operation is repeated to generate channel pulses for channels 1 to 24.

As described above, in this embodiment, the channel pulse generator is composed of the common section and the three channel sections having the channel pulse generating section for generating eight channel pulses, and the channel pulse generating section is sent from the common section. A frequency divider that divides the first channel clock by 8 and outputs it as a second channel clock, and counts up by 1 at the timing of this second channel clock, and when the predetermined count value is reached, the first channel A counter that outputs pulses and a first channel pulse that is shifted at the timing of the first channel clock to output eight channel pulses 8
It consists of a bit shift register. The number of channel parts is three, and when expressed in a binary number, it is "11". Therefore, only two signal lines are required to set the initial value of the counter.
A channel pulse generator having a small number of signal lines connected to set the initial value of the counter can be obtained.

In this embodiment, the shift register is used as the channel pulse output means, but N channel pulses (N is a divisor of the total number of channels) based on the first channel pulse output from the counter are output from the common section. It suffices that it can be output at the timing of the first channel clock that is generated, and the invention is not particularly limited to the shift register.

In this embodiment, the number of channel pulses generated from the channel pulse generating means is 8 and the number of channel portions is 3.
The frequency divider divides the first channel clock by 8
However, the number of channel pulses generated from the channel pulse generating means and the number of frequency dividers that divide the first channel clock are the same number "N", and this number "N" is the total number of channels. It is sufficient that the number obtained by multiplying the number “N” by the number “M” of the channel parts is the total number of channels. Therefore, it is not limited to N = 8 and M = 3, but N = 2 and M
= 12 may be used.

Incidentally, the frequency divider in the channel region 131 _to the channel portion 13 ₃ is a frequency dividing means in the present embodiment 14 ₁ to the frequency divider 14 ₃
However, the frequency dividing means may be provided, for example, independently of the channel portion, without being limited to this example.

〔The invention's effect〕

As described above in detail, in the present invention, the first channel clock supplied from the channel clock generating means is divided by N (N is a divisor of the total number of channels) to be the second channel clock, and the counter is It counts up at the timing of the channel clock 2 and outputs a channel pulse when the count value reaches a predetermined value. Therefore 1
When a plurality of channels are mounted in one channel section, it is possible to obtain a channel pulse generator having a small number of signal lines connected to set the initial value of the counter.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a time chart showing an operating state of the channel pulse generator 20 shown in FIG. 1, and FIGS. 3 and 4 are general PCs.
It is a figure for demonstrating M terminal station apparatus. 10 ...... common part, 13 ₁ to 13 ₃ ...... channel unit, 1
4 _{1 to} 14 ₃ ... frequency divider, 15 _{1 to} 15 ₃ ... counter, 16 _{1 to} 16 ₃ ... shift register, 17 _{1 to} 17 ₃ ... signal line, 20 ... channel pulse generator.

Claims (2)

[Claims] 1. A frame signal generation means for generating a frame signal for instructing the start of one frame including a plurality of channels, and a channel clock generation for generating a first channel clock for instructing the start of each channel of the one frame. A common section including means, and N (N is a divisor of the total number of channels) channels having a pulse width corresponding to each channel section of the plurality of channels based on the frame signal and the first channel clock. M (M = total number of channels / N) number of channel parts having a channel pulse generating means for generating a pulse, and frequency dividing means for dividing the first channel clock by N and outputting it as a second channel clock. The channel pulse generating means is initialized by the frame signal, and the predetermined second channel input after the initialization is input. A counter for outputting a first channel pulse channel clock based on the first channel pulse at the timing of the first channel clock N
A channel pulse generation device comprising: a channel pulse output means for outputting individual channel pulses. 2. The channel pulse output means is an N-bit shift register which shifts the first channel pulse at the timing of the first channel clock and outputs N channel pulses. Range of
The channel pulse generator according to the item (1).