JPH0656997B2 - Erasable buffer circuit - Google Patents

Description

The present invention relates to a digital data communication system in which, when there is a speed difference or a phase difference between transmitted and received data, the speed difference and the like are absorbed to transmit and receive the transmitted and received data. To an elastic buffer circuit for coupling to.

(Prior Art) Generally, an elastic buffer circuit has an appropriate number of bits in each station that transmits and receives digital data so that duplication or loss of information bits does not occur when transmitting and receiving data having a speed difference or a phase difference. It is used to temporarily store the information of. As the elastic buffer circuit, a plurality of storage elements are provided in parallel and information bits of received data are cyclically written to the storage elements in the order of arrival, while the storage is performed by a read clock independent of a write clock. A type in which information bits are read from an element and sent as transmission data is mainly used.

(Problems to be solved by the invention) However, in the conventional elastic buffer circuit of this kind, a phase comparator for detecting a phase difference between write data and read data to a storage element corresponding to transmission / reception data, A control circuit for writing or reading is required, and the circuit configuration is complicated and expensive.

Further, therefore, the conventional elastic buffer circuit is often used only for the control station among all the stations constituting the communication system, and is not suitable for being arranged in a large number of stations in a distributed control local network or the like. There was a problem such as being.

The present invention has been proposed in order to solve the above problems, and an object of the present invention is to simplify the circuit configuration by eliminating a complicated circuit such as a phase comparator, and to perform digital transmission of various forms. It is to provide an elastic buffer circuit that can be applied to a system.

(Means for Solving Problems) In order to achieve the above object, according to the present invention, write data obtained by delaying input data in synchronization with a write clock is selected in synchronization with the write clock according to its count value. An elastic buffer circuit that temporarily writes data in any of a plurality of storage elements in the order of arrival of bits and uses as output data the data read in the order of arrival of bits from the plurality of storage elements selected by the count value of the read clock. In, the input data has a time fill inserted between the frames of the input data at a period of a divisor of the number of bits equal to the capacity of the storage element, and a start flag of the frame. A start flag detection circuit that saves the count value of the write clock at that point in the register and an open flag detection circuit. A latch circuit that holds the output of the storage element for a certain period after detecting the start flag, and a hold time counter that loads the count value of the write clock in the register as the count value of the read clock when the hold time in this latch circuit elapses. It is characterized by having and.

(Operation) In the present invention, by detecting the start flag in the frame of the input data, the bit pattern of the time fill written in each storage element is held in the latch circuit for a certain period. With the lapse of this hold time, the count number of the write clock at the time when the start flag is detected is loaded into the read counter, and thereafter, each time the count is incremented by the read clock, each memory is stored via the latch circuit in the through state. Each bit in the frame of input data is read from the element in the order of arrival.

That is, the read bit position is initialized by a series of operations starting from the detection of the start flag.

(Example) An example of the present invention will be described below with reference to the drawings. In this embodiment, the buffer capacity is composed of n bits.
First, in FIG. 1, 1 is input data (received data) Di
In the delay circuit 1, the input data Di is delayed in synchronization with the write clock CKw to generate write data Dw for _n flip-flops 2 ₁ to 2 _n described later. The output of the delay circuit 1 is n flip-flops 2 ₁ to _{2 2} , ..., 2
It is added to each D input terminal of _n .

On the other hand, the write clock CKw obtained from the received data is input to the write counter 3, and the count value output of the write counter 3 is input to the n-bit decoder 4. In addition, the write clock CKw is the n AND gates 5 ₁ provided on the input side of the flip-flops 2 ₁ to 2 _n.
.About.5 _n respectively, and the output of the decoder 4 is applied to each of the other input terminals. Then, the output terminals of the AND gates 5 ₁ to 5 _n are respectively connected to the clock input terminal of the flip-flop 2 ₁ to 2 _n, Q output terminal of flip-flop 2 ₁ to 2 _n via the latch circuit 6 data The data selector 7 is connected to the input side of the selector 7, respectively, and the output data (transmission data) Do is output from the data selector 7.

Further, the input data Di is input to the start flag detection circuit 8, and the start flag detection circuit 8 outputs the latch signal S ₁ and the hold signal S ₂ . The latch signal S ₁ is input to the register 9 provided on the output side of the write counter 3, and the hold signal S ₂ is input to the hold time counter 10 and the enable terminal EN of the latch circuit 6.

Here, the latch circuit 6 has an enable input of “L”.
(Or "H"), the through state in which the input data from the flip-flops 2 ₁ to 2 _n is passed as it is, and conversely, when the enable input is "H" (or "H"), the input data is input. Is held.

Load signal S ₃ as output of hold time counter 10
Is added to the start flag detection circuit 8 and the read counter 11. The read counter 11 is supplied with the read clock CKr independent of the write clock CKw and the output of the register 9, and the output of the read counter 11 is It is added to the data selector 7.

Next, the basic operation of this embodiment will be described. The latch circuit 6 is normally in the through state.

First, the operation at the time of reception will be described. The input data Di sent from the transmitting station becomes the write data Dw synchronized with the write clock CKw via the delay circuit 1. On the other hand, the write counter 3 uses the write clock CK.
The w is counted, and the count value output is decoded by the decoder 4 and output. This output is one in which any one of the n output terminals becomes “H”, and the flip-flop 2 ₁ is connected via the AND gate corresponding to the output terminal.
~ 2 _n is selected. That is, the selected flip-flop writes the write data Dw in synchronization with the write clock CKw by the output of the AND gate to its clock input terminal.

Further, since the write counter 3 counts up in synchronization with the write clock CKw, the write data Dw
Are flip-flops in the order of arrival of the data bits ..., 2
Cyclic writing is performed in the order of ₁ , 2 ₂ , ..., 2 _n , 2 ₁ ,.

Next, at the time of transmission, the read counter 11 counts the read clock CKr and sends the count value output to the data selector 7. The data selector 7 selects an input terminal according to the count value output, and the flip-flops 2 ₁ to 2 _n via the latch circuit 6 in the through state.
One of the outputs is sent as output data Do to another station. Since the read counter 11 counts up in synchronization with the read clock CKr, the data is flip-flops ..., 2 ₁ , 2 ₂ , ..., 2 _n , 2 ₁ ,.
In this order, the bits are cyclically read bit by bit.

Therefore, in this embodiment, as shown in FIG. 2, the transmitting station transmits a signal (hereinafter, referred to as "time fill") to compensate for this between the frames of the input data Di, that is, during the period when there is no valid data. Shall be sent. This time fill has a bit pattern having a cycle with a bit number equal to a divisor of the capacity (bit number) n of the buffer circuit according to the present invention. For example, if n = 8 bits, the time fill cycle is 1 Bit, 2 bit, 4
Either bit or 8 bits may be used.

By setting the time fill cycle in this way,
The data written in the flip-flops 2 ₁ to 2 _n between the frames of the input data Di is constant for each of the flip-flops 2 ₁ to 2 _n .
That is, in the above example, as long as the time-fill cycle is a divisor of 8 bits, for example, the output of the flip-flop 2 ₁ is always "H" or "L", and the flip-flops 2 ₂ to 2 _The same applies to _n . Therefore, even if the count values of the write counter 3 and the read counter 11 do not match and are irrelevant, it is possible to obtain the output data Do in which the bit pattern of the time fill in the input data Di is accurately read.

After the time fill is read in this way, a specific bit pattern of m-bit length (hereinafter, referred to as a start flag) indicating the start of the frame is preceded by the second data bit.
It is detected by the start flag detection circuit 8 at time t ₁ in the figure. As a result, the start flag detection circuit 8 outputs the latch signal S ₁ , and the register 9 outputs the latch signal S ₁
In response to this, the count value k of the write counter 3 at that time is fetched.

On the other hand, write data D to the flip-flops 2 ₁ to 2 _n
If w is the input data Di delayed by m bits through the delay circuit 1, at time t ₁ , the start flag is shown in the k-th flip-flop among the flip-flops 2 ₁ to 2 _n. The _first bit F _{1 of the} is written.

Further, the start flag detecting circuit 8 outputs the latch signal S ₁ and at the same time, outputs the hold signal S ₂ , and the hold signal S ₂ is input to the enable terminal EN of the latch circuit 6. As a result, the latch circuit 6 enters the hold state,
Start flag detection prior to the output of each flip-flop 2 ₁ to 2 _n, that is so that the bit pattern of the time fill is maintained. Therefore, although the count value of the read counter 11 is irrelevant to the count value of the write counter 3 at this time, the bit pattern of the time fill is continuously read and output as it is.

The hold time counter 10 counts the time during which the hold signal S ₂ is in the active (hold) state, and it is now assumed that the speed relationship between the write clock CKw and the read clock CKr is indefinite. , Hold signal S in hold time counter 10
The count value until ₂ becomes inactive is (n /
2) -1, and at this time (time t ₁ ′ in FIG. 2), the load signal S ₃ is output to the read counter 11. Due to this load signal S ₃ , the count value of the write counter 3 saved in the register 9 at the time t ₁ is changed to the read counter 11 at the time t ₂ ′ in FIG.
Is set to.

Here, the load signal S ₃ is also applied to the start flag detection circuit 8, and the start flag detection circuit 8 is reset by the load signal S ₃ and the hold signal S ₃ is inactive after time t ₂ ′. It becomes a state. Therefore, the latch circuit 6 switches from the hold state until then to the through state, and at time t ₂ ′, the _first bit F _{1 of the} start flag is read from the flip-flop of the number k.

After that, when the read counter 11 counts up,
Flip-flops from the (k + 1) th order ..., 2 _n , 2 ₁ ,
Since the input data Di is cyclically read as 2 ₂ , ..., The output data Do has the same bit pattern as the input data Di. This state is write clock CKw
It continues until the count value of the write counter 3 and the count value of the read counter 11 match due to the speed difference between the read clock CKr and the read clock CKr. Therefore, the elastic buffer circuit according to the present invention can be configured with the minimum necessary hardware by selecting the minimum necessary buffer capacity n so that the reading of the maximum length frame can be completed within this period. it can.

When the magnitude relationship between the speeds of the write clock CKw and the read clock CKr is indefinite as described above, the delay of the read counter 11 with respect to the write counter 3 at the start of reading (time t ₂ ′ in FIG. ₂ ) is delayed. The buffer capacity n can be minimized when n / 2 bits are set. Further, when the speed of the write clock CKw is faster than the speed of the read clock CKr, the delay of the read counter 11 is reduced, and conversely, when the speed of the read clock CKr is faster than the speed of the write clock CKw, the read is performed. The buffer capacity n can be minimized by increasing the delay of the counter 11.

The delay of the read counter 11 can be arbitrarily changed by setting the count number in the hold time counter 13.

Next, a case where this embodiment is applied to a token (transmission right) type ring-shaped data way will be described with reference to FIG. In the figure, reference numerals 100, 200, ..., 900 denote stations for transmitting and receiving data via the transmission path 20, and these stations 100, 200, ..., 900 all have the same configuration. Therefore, for convenience, the configuration of the station 100 will be described. 101 is a receiving circuit that performs retiming and decoding, 102 is an elastic buffer circuit according to the present invention, 103 is a read clock CKr of the elastic buffer circuit 102, In other words, a master clock oscillator that supplies the transmission clock of the transmission circuit 105 described later, 104 is a selection circuit that selects either the output data of the elastic buffer circuit 102 or the internal transmission data, and 105 does not send encoding or the like. Transmitter circuit, CK
As described above, w, Di, and Do are the write clock for the elastic buffer circuit 102, the input data and the output data, Do 'is the internal transmission data, and Do "is the transmission data selected by the selection circuit 104 (that is, the output). Data Do or internal transmission data Do ') are shown.

Here, it is assumed that the selection circuit 104 controls selection of the transmission data Do ″ by a microprocessor (not shown) or the like inside the station 100.

In the other stations 200 and 900, 202 and 902 respectively represent elastic buffer circuits according to the present invention.

Now, only the station 100 has the transmission right, the internal transmission data Do 'is selected by the selection circuit 104, and the elastic buffer circuits 202, ..., 902 in all the other stations 200, ..., 900. If the output from the station is selected and output as the transmission data Do ″, the internal transmission data Do ′ in the station 100 is the transmission data D ″.
As o ″, the data way is cycled in the order of stations 200, ..., 900. At this time, each station 200 ,.
…, 900 elastic buffer circuits 202,…, 90
By the above-described operation in 2, the speed difference and the phase difference between the reception data and the transmission data can be removed.
Therefore, it is possible to construct a highly reliable data way without duplication or loss of data bits, and it is possible to further extend the distance of the transmission path.

(Effect of the Invention) As described above, according to the present invention, the start flag in the input data is detected, the time fill sent until then is held for a certain period, and then the data after the start flag is read. Since the read bit position is initialized by detecting the start flag, a start flag detection circuit, a hold time counter, etc. can be used without using a phase comparator for write data and read data as in the past. An elastic buffer circuit can be realized with a simple configuration of. Therefore, it is possible to reduce the cost, and it is possible to arrange the stations in each station in a distributed network or the like.

In addition, since the input / output data is not controlled like the pulse stuffing method, it can be applied to many kinds of digital transmission systems.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing chart showing an operation, and FIG. 3 is a configuration diagram of a data way showing an application example of the embodiment of FIG. 1 ...... delay circuit, 2 ₁ to 2 _n ...... flip-flop 3 ...... write counter, 4 ...... decoder 5 ₁ to 5 _n ...... AND gate, 6 ...... latch circuit 7 ...... data selector, 8 ...... start Flag detection circuit 9 …… Register, 10 …… Hold time counter 11 …… Read counter CKw …… Write clock CKr …… Read clock Di …… Input data, Do …… Output data Dw …… Write data, S ₁ …… Latch signal S ₂ …… Hold signal, S ₃ …… Load signal

Claims (1)

[Claims] 1. Write data, which is obtained by delaying input data in synchronization with a write clock, is temporarily stored in any of a plurality of storage elements selected by the count value in synchronization with the write clock in the order of arrival of bits. In the elastic buffer circuit that outputs the data read from the plurality of storage elements selected by the count value of the read clock in the order of arrival of the bits as the output data, while the input data is the capacity of the storage element. It has a time fill inserted between the frames of the input data at a period of a divisor of an equal number of bits, and a start flag of the frame, and when this start flag is detected, the count value of the write clock at that time point. Start flag detection circuit that saves the start flag to the register and a fixed value after the start flag is detected. Period of
A latch circuit that holds the output of the storage element; and a hold time counter that loads the count value of the write clock in the register as the read clock count value when the hold time in the latch circuit elapses. Characteristic elastic buffer circuit.