JPH065711B2 - Method for manufacturing CMOS semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a CMOS semiconductor device, and more particularly to N
The present invention relates to a method for forming a source / drain region of a channel and a P channel MOS transistor.

[Conventional technology]

A conventional method for manufacturing a CMOS semiconductor device will be described with reference to FIG.

First, as shown in FIG. 3A, the N-type silicon substrate 1
After the P-type well region 2 is formed on the substrate, a thick field oxide film 3 for element isolation is formed by a normal selective oxidation method.
In FIG. 3 (a), 4 is the thick field oxide film 3
Prior to formation, a P ⁺ type diffusion layer for a channel stopper is formed below the field oxide film in the P type well region 2, 5 is a thin silicon oxide film, and 6 is a nitride film.

Next, as shown in FIG. 3 (b), after removing the nitride film 6 and the silicon oxide film 5, a thin gate oxide film 7 is formed, and phosphorus-doped polycrystalline silicon is grown by the CVD method, and well-known photo-corrosion is performed. A gate electrode 8 made of polycrystalline silicon is formed by an engraving method.

Next, as shown in FIG. 3C, a photoresist pattern 10 is formed by a photo-etching method, and using the photoresist pattern 10 as a mask, arsenic is introduced into the P-type well region 2 by an ion implantation method.

Next, as shown in FIG. 3D, the photoresist pattern 10 is removed by etching with oxygen plasma, and the arsenic implantation region is annealed to form the N ⁺ type source / drain region 1.
1 is formed, a photoresist pattern 10A is formed by a photo-etching method, and the photoresist pattern 10A is formed.
Is used as a mask to introduce boron into the N-type silicon substrate 1 by an ion implantation method.

Next, as shown in FIG. 3 (e), the photoresist pattern 10A is removed by etching with oxygen plasma, the boron-implanted region is annealed to form a P ⁺ -type source / drain region 12, and then CVD is performed on the entire surface. A phosphor glass layer (PSG layer) 13 by a method, and a contact opening is formed on each source / drain region by a known method.
After that, the Al wiring 14 is formed to complete the CMOS semiconductor device.

[Problems to be solved by the invention]

In the conventional method for manufacturing a CMOS semiconductor device described above, in the formation of the source / drain regions of the N-channel MOS field effect transistor, arsenic is introduced by an ion implantation method using the photoresist as a mask, and then the oxygen plasma is used as the photoresist. However, in this case, the photoresist for the mask in which a large amount of arsenic is implanted to form the source / drain is deteriorated and is difficult to be etched, and an etching residue is generated to cause a yield. It has the drawback of causing a decrease.

Further, a method such as increasing the power of oxygen plasma etching is used to reduce the above-mentioned etching residue, but this is not preferable because it also increases damage to the semiconductor element itself.

An object of the present invention is to eliminate the above-mentioned drawbacks and provide a method for manufacturing a CMOS semiconductor device with improved yield.

[Means for solving problems]

According to the method of manufacturing a CMOS semiconductor device of the present invention, the source / drain regions of the N-channel transistor are formed by ion implantation of N-type impurities using a silicon oxide film formed by the CVD method as a mask to form the source / drain regions of the P-channel transistor. It is formed by ion implantation of P-type impurities through the silicon oxide film using the photoresist film as a mask.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

1A to 1G are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the first embodiment of the present invention.

First, as shown in FIG. 1A, after a P-type well region 2 is formed on an N-type silicon substrate 1 by a known method, boron is selectively formed in the element isolation region of the P-type well region 2. After being introduced by an ion implantation method and annealed to form a P ⁺ type diffusion layer 4 for a channel stopper, a thin silicon oxide film 5 is formed on the substrate surface by a thermal oxidation method.
After that, the boron-phosphorus glass layer 15 is formed by the CVD method, and the photoresist pattern 16 is formed by the well-known photo-etching method.
Are formed in the element isolation region.

Next, as shown in FIG. 1B, the boron-phosphorus glass layer 15 is formed using the photoresist pattern 16 as a mask.
After the silicon oxide film 5 is removed by etching, the photoresist pattern 16 is removed, a thin gate oxide film 7 is formed by a thermal oxidation method, and the etching step of the boron-phosphorus glass layer 15 is reflowed to be gentle. Furthermore, phosphorus-doped polycrystalline silicon 8 is formed by the CVD method.
A is formed on the entire surface, and a photoresist pattern 16A is formed by a known photo-etching method.

Next, as shown in FIG. 1 (c), the phosphorus-doped polycrystalline silicon 8A is removed by etching using the photoresist pattern 16A as a mask to form a gate electrode 8 made of polycrystalline silicon, and then the photoresist pattern 1 is formed.
Remove 6A.

Next, as shown in FIG. 1D, a thin silicon oxide film 5A is formed on the entire surface by a CVD method so as to have a film thickness of about 1000 to 2000Å, and then a photoresist pattern 16B is formed by a known photo-etching method.

Next, as shown in FIG. 1 (e), using the photoresist pattern 16B as a mask, the silicon oxide film 5A is removed by etching with buffered hydrofluoric acid or the like, and then the photoresist pattern 16B is removed with an organic solvent.
A thin silicon oxide film 5B having a film thickness of 100 to 200Å is formed on the surface of the silicon substrate and the surface of the gate electrode 8 of polycrystalline silicon by the thermal oxidation method. Then, using the patterned silicon oxide film 5A formed by the CVD method as a mask, arsenic of 50 to 50 is formed through the thin silicon oxide film 5B.
It is introduced into the silicon substrate 1 by the ion implantation method with the energy of 70 keV.

Next, as shown in FIG. 1 (f), a photoresist pattern 16c is formed by a well-known photo-etching method, and the photoresist pattern 16c is used as a mask to remove boron from 40 to 40 through the silicon oxide film 5A by the CVD method. 60ke
It is introduced into the silicon substrate 1 by the ion implantation method with the energy of V.

Next, as shown in FIG. 1 (g), the ion-implanted layer of arsenic and boron is annealed to form the N ⁺ type source / drain region 11 of the N channel transistor and the P ⁺ type source / drain region of the P channel transistor. 12 is formed.

In the following, the PSG layer 13 is formed on the entire surface by the known method by the CVD method, the contact opening is formed by the photo etching method, and then the Al wiring 14 is formed, and the CMOS is formed.
Complete the semiconductor device.

In the above manufacturing method, the silicon oxide film 5A formed by the CVD method, which serves as a mask for arsenic ion implantation for forming the source / drain regions of the N-channel transistor, has a etching rate for buffered hydrofluoric acid of boron phosphorus glass on the element isolation region. Since it is sufficiently larger than the layer 115, slight overetching during the etching of the silicon oxide film 5A has almost no effect on the reduction in the thickness of the boron-phosphorus glass layer 15 on the element isolation region.

In the above manufacturing method, the arsenic ion implantation for forming the source / drain regions of the N-channel transistor is performed by using the silicon oxide film by the CVD method as a mask and leaving the ion implantation as it is. As seen in the method, when the photoresist is used as a mask, there is no etching residue due to alteration of the photoresist, and it is possible to prevent the yield reduction.

2A to 2C are cross-sectional views of a semiconductor chip for explaining the second embodiment of the present invention.

This second embodiment of the N-channel transistors in the first embodiment described in FIG. 1 (a) ~ (g) N +
This is a case where the process steps of arsenic ion implantation for forming the p-type source / drain regions and boron ion implantation for forming the P ⁺ -type source / drain regions of the P-channel transistor are reversed. The description of the part overlapping with the example is omitted.

In FIG. 2 (a), a gate electrode 8 made of polycrystalline silicon is formed in the same manner as in the first embodiment, and a thin silicon oxide film 5A formed by the CVD method is formed on the entire surface to a film thickness of 1000 to 2000Å.
Formed by a known photo-etching method to form a photoresist pattern 16D having an opening including the source / drain regions of the P-channel transistor, and using the photoresist pattern 16D as a mask, a thin silicon oxide film formed by the CVD method. 40-60keV of boron through 5A
The energy up to the point where it is introduced into the silicon substrate by the ion implantation method is shown.

Next, as shown in FIG. 2B, the photoresist pattern 16D is removed by etching using oxygen plasma. In this case, although a large amount of boron is implanted into the photoresist pattern 16D, boron has a smaller atomic weight than arsenic and the alteration of the photoresist is small, so that it can be easily removed by etching. Further, a well-known photo-etching method is used to form a photoresist pattern 16E having an opening including the source / drain regions of the N-channel transistor.

Then, as shown in FIG. 2C, the silicon oxide film 5A formed by the CVD method is removed by etching with buffered hydrofluoric acid using the photoresist pattern 16E as a mask, and then the photoresist pattern 16E is formed with an organic solvent. Removed and film thickness 100-200 by thermal oxidation method
A thin silicon oxide film 5B of Å is formed on the surface of the silicon substrate and the surface of the gate electrode 8 made of polycrystalline silicon, and the patterned silicon oxide film 5 is formed by the CVD method.
Using A as a mask, arsenic is introduced into the silicon substrate 1 through the silicon oxide film 5B with an energy of 50 to 70 keV by an ion implantation method.

The following steps are performed in the same manner as in the first embodiment to complete the CMOS semiconductor device.

Also in this second embodiment, the arsenic ion implantation for forming the source / drain regions of the N-channel transistor is performed by using the silicon oxide film by the CVD method as a mask and leaving it as it is after the ion implantation. When the photoresist as used in the manufacturing method is used as a mask, there is no etching residue due to alteration of the photoresist, and the yield reduction can be prevented. In each of the first and second embodiments of the present invention, the element isolation insulating film has a two-layer structure of a thin silicon oxide film and a boron phosphorus glass layer, but a thick silicon oxide film formed by a normal selective oxidation method is used. You may use. It is also possible when the substrate is P-type.

〔The invention's effect〕

As described above, according to the present invention, in the method for manufacturing a CMOS semiconductor device, the source / source of the N-channel transistor is
The drain region is formed by ion implantation of N-type impurities using a silicon oxide film formed by the CVD method as a mask, and P
The source / drain regions of the channel transistor are formed by ion implantation of P-type impurities through the thin silicon oxide film formed by the CVD method using the photoresist film as a mask, so that the photoresist does not remain unlike the conventional case. There is an effect that the manufacturing yield of the CMOS semiconductor device can be improved.

[Brief description of drawings]

1 (a) to 1 (g) are sectional views of a semiconductor chip shown in the order of steps for explaining the first embodiment of the present invention, and FIGS. 2 (a) to 2 (c) are second embodiment of the present invention. 3A to 3E are sectional views of the semiconductor chip for explaining the embodiment of the present invention, and FIGS. 3A to 3E are sectional views of the semiconductor chip for explaining the conventional method for manufacturing the CMOS semiconductor device. 1 ... N type silicon substrate, 2 ... P type well region, 3 ... field oxide film, 4 ... P ⁺ type diffusion layer, 5,5A, 5B ... silicon oxide film, 6 ... nitride film, 7 ... gate oxide film, 8A …
Polycrystalline silicon, 8 ... Gate electrode, 10, 10A ... Photoresist pattern, 11 ... N ⁺ type source / drain region, 12 ... P ⁺ type source / drain region, 13 ... PSG
Layer, 14 ... Al wiring, 15 ... Boron phosphorus glass layer, 16,
16A, 16B, 16C, 16D, 16E ... Photoresist pattern.

Claims (2)

[Claims] 1. A source / drain region of an N-channel transistor is formed by ion implantation of N-type impurities using a silicon oxide film formed by a CVD method as a mask, and a source / drain region of a P-channel transistor is used as a mask of a photoresist film. P through the silicon oxide film
A method for manufacturing a CMOS semiconductor device, which is characterized in that it is formed by ion implantation of type impurities. 2. N for forming source / drain regions
The method for manufacturing a CMOS semiconductor device according to claim (1), wherein the p-type and p-type impurities are arsenic and boron, respectively.