JPH065747B2 - MOS semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Field of Industrial Application) The present invention relates to a MOS type semiconductor device, and is particularly used for applications requiring high-speed and low-power-consumption operation at low voltage. It is a thing.

(Prior Art) A MOS type semiconductor device has a cross-sectional structure as shown in FIG. 6 as well known, and a source (S) 12 and a drain (D) 13 are formed on the surface of a semiconductor substrate 11. The high-concentration impurity diffusion regions are provided at a predetermined channel interval, and a gate (G) electrode 15 is provided on the high-concentration impurity diffusion regions with a gate insulating film 14 interposed therebetween. The general static characteristic of this MOS type semiconductor device is shown in the graph of FIG. 7, and the drain current flows only when the gate voltage exceeds a certain threshold value V _th .

Conventionally, in the MOS type semiconductor device, the voltage applied to the substrate is fixed to the source voltage or a certain voltage.
The threshold value V _{th under} this voltage condition is 0.6 to 1.0.
It is set to V. Also, 5V is often used as the power supply voltage.

However, as miniaturization of the device progresses, the decrease in reliability due to hot carriers in the n-channel transistor has become remarkable, so that it is necessary to decrease the power supply voltage. For example, in a transistor having a gate length of 0.8 μm or less, it is desirable that the power supply voltage is about 3 V, but simply lowering the power supply voltage will result in a lower operating speed. It is effective to avoid lowering the operating speed and to further increase the operating speed, but it is effective to lower the threshold value. However, the so-called leak current at the gate voltage of 0 V increases, which causes malfunction and power consumption. The problem occurs.

(Problems to be Solved by the Invention) As described above, in the conventional MOS semiconductor device, it is not possible to simultaneously satisfy the characteristics of element miniaturization, high-speed operation, and low power consumption.

The present invention has been made to solve such a problem, and an object thereof is to provide a high speed and low power consumption MOS semiconductor device.

[Structure of Invention]

(Means for Solving the Problems) The present invention relates to a MOS type semiconductor device capable of independently controlling the voltages of the source, drain and gate regions of a MOS transistor and the bias voltage of a semiconductor substrate with respect to the source voltage. The bias voltage is reversed in phase in synchronization with the change in the voltage applied to the gate so that the threshold value of the MOS transistor decreases when the MOS transistor operates and increases when the MOS transistor does not operate. It is characterized in that it comprises a potential control means for changing it.

(Operation) It is known that the threshold value of a MOS transistor changes depending on the voltage applied to the semiconductor substrate. FIG. 8 is a graph showing the relationship between the substrate voltage applied to the semiconductor substrate and the threshold value, showing that the threshold shift amount increases as the absolute value of the substrate voltage increases. . For example, in an n-channel MOS type transistor, the threshold value is deepened by about 0.5 V by applying -2 V as shown in FIG.
In the S transistor, the threshold value becomes deeper by about 0.5V by applying 2V.

The present invention utilizes such a phenomenon to lower the threshold value when the transistor is in the operating state and increase the threshold value when the transistor is in the off state to reduce the leakage current. The source potential with respect to the semiconductor substrate is changed. Therefore, a semiconductor device which operates at high speed and consumes less power can be obtained.

(Embodiment) FIG. 1 is a circuit diagram showing a configuration of an embodiment of a semiconductor device according to the present invention, and a CMOS will be described here as an example.

The gate of the p-channel MOS type transistor P ₁ is connected to a two-stage inverter consisting of n-channel MOS type transistors N ₂ and N ₃ and resistors R _2a and R _3a , and both resistors are provided with a voltage supply circuit using a charge pump, for example. A bias voltage of 1 to 7 V is supplied. Similarly, the gate of the n-channel MOS type transistor is connected to a two-stage inverter composed of p-channel MOS type transistors P ₂ and P ₃ and resistors R _2b and R _3b . Bias voltage is supplied. The connection point between the resistor R _3a and the transistor N ₃ is connected to the substrate of the p-channel MOS transistor P ₁ , and similarly, the connection point between the resistor R _3b and the transistor P ₃ is an n-channel MOS transistor N _1.
Connected to the board. Of the two-stage inverters used here, the first stage may be an inverter with a large amplification factor β that is normally used, but the second stage inverter may be the load resistance R
It is necessary to set the values of _3a and R _3b as follows.

However, N ₃ and P ₃ are resistance values when the respective transistors are operating. This is because the output voltage of the second-stage inverter needs to fluctuate between the voltages generated by the voltage generating circuit according to the gate voltage.

As a result, when the gate voltage is applied to the inverter, the same voltage as the source voltage is applied to the substrate, and when the gate voltage is not applied to the inverter, the bias voltage output from the voltage supply circuit is applied to the substrate. become.
This state is shown in FIG. 2, and the gate voltage V _g and the substrate voltage V _sub have opposite phases to each other.

By doing so, since the substrate potential is the source potential during the operation of the transistor, the threshold value is lowered and the operation speed is increased. On the other hand, when the transistor is off, a bias voltage is applied to the substrate by the voltage supply circuit, so that the threshold value becomes high and the generation of leak current is suppressed.

FIG. 3 is a graph showing the relation of the drain current Ids with respect to the threshold value V _th, and shows the case where 3 V is applied to the drain. According to the figure, by applying the present invention, the threshold value Vt when the transistor is ON is 0.1 V for the n-channel transistor and −0.1 V for the p-channel transistor, so the drain current Ids It can be seen that is increased by about 40% compared with a transistor having a normal threshold value of about 0.8V.

On the other hand, by applying the substrate bias, the current change rate S in the region below the threshold value increases in addition to the increase in the threshold value as described above (FIG. 4). Here, S is the amount of voltage change required to decrease the current by one digit in the region below the threshold value, and the smaller S is, the more rapidly the current changes, and the leak current decreases. Therefore, by applying -2V to the n-channel transistor or + 2V to the p-channel transistor as the substrate bias, the threshold value is increased from ± 0.1V to ± 0.6V, which is equal to the conventional threshold value ±. A leak current almost equal to that of a normal transistor of 0.8V can be obtained.

Note that the above explanation is about the source, drain, and
It is premised that voltage can be applied to the gate and the substrate independently. However, it is generally difficult to apply a bias to the substrate for each transistor, and structural modification may be necessary to apply a bias voltage.

By the way, a CMOS semiconductor device has an n-channel transistor and a p-channel transistor, but from the viewpoint of speeding up, it is often sufficient to speed up only one of the transistors. Generally p
Since the channel transistor has a smaller current driving capability than the n-channel transistor, the present invention may be applied to the p-channel transistor.

FIG. 5 is a sectional view showing an embodiment in which the present invention is applied to a CMOS type semiconductor device, in which a substrate 21 surrounded by field oxide films 20 and 2 is provided with an n well 22 and is formed on the surface thereof. An n-type impurity high-concentration diffusion region 24, which is an extraction part from the well, a source region 25 and a drain region 26, which are p-type impurity high-concentration diffusion regions, are provided. A gate electrode 28 is provided on the semiconductor substrate in a region between the source region 25 and the drain region 26 with a gate oxide film 27 interposed therebetween. By providing the extraction electrodes A, B, C, and D respectively from these respective regions, it is possible to independently apply a voltage to each region. Similarly, in order to change the substrate voltage of only the p-channel MOS type transistor, a p-well may be provided.

Furthermore, the present invention is a so-called SOI (Silicon On Insulator) in which a semiconductor device is formed on an insulator.
or) or SOS (Silicon On Sap)
It can also be applied to a (phire) structure. In this case, since the voltage of each region of both n-channel and p-channel transistors can be controlled independently, a substrate bias can be applied to any transistor.

〔The invention's effect〕

As described above, according to the present invention, in synchronization with a change in the voltage applied to the gate, the threshold value of the MOS transistor decreases when the MOS transistor operates and increases when the MOS transistor does not operate. Since the bias voltage is changed to the opposite phase, it is possible to obtain a semiconductor device which operates at high speed and consumes less power.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram showing changes in substrate voltage, FIGS. 3 and 4 are graphs showing the operation of the present invention, and FIG. Applying CMO
FIG. 6 is a sectional view showing the structure of an S-type semiconductor device, FIG. 6 is a sectional view showing the structure of a conventional general MOS semiconductor device, FIG. 7 is a graph showing the relationship between gate voltage and drain current, and FIG. 8 is a substrate voltage. 7 is a graph showing the relationship between the threshold and the threshold. 1, 2 ... Voltage supply circuit, 11, 21 ... Semiconductor substrate, 1
2, 25 ... Source, 13, 26 ... Drain, 15, 28
…Gate.

Claims (4)

[Claims] 1. A source and a drain of a MOS transistor,
In a MOS semiconductor device capable of independently controlling a voltage of each region of a gate and a bias voltage of a semiconductor substrate with respect to the source voltage, a threshold value of the MOS transistor decreases when the MOS transistor is operating, and a non-operation of the MOS transistor is performed. A MOS type semiconductor device comprising a potential control means for changing the bias voltage to a reverse phase in synchronization with a change in voltage applied to the gate so that the threshold value thereof rises. 2. A MOS type semiconductor device according to claim 1, wherein the potential control means has a charge pump circuit. 3. The semiconductor device is a CMOS type, and the potential control means is provided in at least the p-channel transistor of the p-channel transistor and the n-channel transistor, and the potential control means is provided in at least the p-channel transistor. Item 6. A MOS semiconductor device according to item. 4. The MOS type semiconductor device according to claim 1, wherein the semiconductor substrate region is a semiconductor layer formed on an insulating substrate.