JPH065756B2 - Semiconductor device manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention relates to a MISFET manufacturing method.

[Conventional technology]

In recent years, laminated devices using SOI substrates have been actively developed. As an example, a stacked CMOS S by AHShah etc.
RAM (1984. Symposium on B.S.I.
Symposium, Digest of Technical Papers, 1984. Symposium on VLSI Technology Digest o
f Technical papers). Its structure is shown in FIG. In the figure, 3 is a gate electrode, 4 is a gate insulating film,
21 is an n ⁺⁺ diffusion layer, 22 is a p ⁺ diffusion layer, 23 is an n ⁺ layer, and 24 is
It is an Al electrode. From the figure, the gate electrode 3 is shown as nMOSFET and pMOSF.
You can see that it is used in common with ET. At this time, since the surface of the semiconductor film for the pMOSFET located in the upper layer is not flattened, the exposure accuracy of the photoresist used as the ion implantation mask does not increase when the source / drain regions are formed. Has become a drawback.

[Problems to be solved by the invention]

To solve this problem, it is necessary to form the source and drain regions by the self-alignment method. Also,
A source-drain current that cannot be controlled by the gate electrode 3 may flow near the above-mentioned interface due to the interface state generated at the interface where the semiconductor film surface of the pMOSFET and SiO ₂ for surface protection are in contact. In order to
There is a drawback that the second gate electrode (back gate electrode) must be provided on the surface of the semiconductor film for use.

The object of the present invention is to eliminate the above-mentioned conventional defects.
It is to provide a manufacturing method. Further, since the semiconductor film to be the channel region is thinned by flattening, it becomes possible to make the slope of the subthreshold current steeper in the drain current-drain voltage characteristics of the manufactured MOSFET.

[Means for solving problems]

The present invention is a method of manufacturing a MISFET using an SOI substrate,
A step of forming a first gate electrode after forming an insulating film on the semiconductor substrate, and a step of forming a first gate electrode on the surface of the first gate electrode.
Growing a gate insulating film, forming a thicker semiconductor film with a total film thickness of the first gate electrode film thickness and the first gate insulating film thickness, and forming a thick semiconductor film on the surface of the semiconductor film by ion implantation. Forming an impurity layer, and thereafter removing the impurity layer on the first gate electrode, and
The step of polishing and flattening the surface of the semiconductor film to the extent that an impurity layer other than on the gate electrode is not removed, a second gate insulating film is formed, and a channel of the MISFET formed by the first gate electrode And a step of forming a second gate electrode having a shape that covers the entire region.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

Here, an nMOSFET using silicon as the MISFET will be described as an example. Silicon is another semiconductor film,
In addition to nMOSFETs, pMOSFETs are also possible.

In FIG. 1 (a), 1 μm SiO ₂ 2 is first formed on the Si substrate 1 by a thermal oxidation method. Next, after growing n ⁺ poly-Si by 0.5 μm by the LPCVD method, the gate electrode 3 is formed by a resist process and an etching process. Next, an oxide film is grown as a gate insulating film 4 on the surface of the gate electrode 3 by 400 Å using a thermal oxidation method. Thereafter, as shown in FIG. 1 (b), a LPF method is used to deposit a Si thin film 5 having a thickness of 0.7 μm on the surface. Next, As is introduced into the Si thin film 5 by using an ion implantation method. The injection condition at this time is that the acceleration voltage is 180K.
The eV and dose amount are 5 × 10 ¹⁵ cm ^-2 . This Si thin film 5
Since there is unevenness corresponding to the shape of the gate electrode 3 on the surface of, the surface is polished by a mechanical chemical polishing method in order to flatten it. As a result, the surface of the Si thin film 5 is flattened, and the Si thin film 7 shown in FIG. 1 (c) is obtained. At this time, the degree of polishing does not expose the gate insulating film 4 and serves as the source region 8 and the drain region 9.
It will be finished leaving. Next, a back gate insulating film 10 is grown on the surface of the Si thin film 7 by 400 Å, and then a back gate 11 having a shape covering the entire channel region 16 of the MISFET is formed by 0.5 μm LPCVD poly-Si.

Next, in FIG. 1 (d), SiO ₂ 12 which becomes a surface protective film is removed.
After growing by 0.5 μm by LPCVD method, contact holes are formed in the source region 8, the drain region 9 and the back gate 11, and the source electrode 13, the drain electrode 14 and the gate electrode 15 made of Al are formed to complete the MISFET. To do.

In the above embodiments, As is used as the ion-implanted impurities and Si oxide film is used as the gate insulating film, but it is obvious that other materials may be used.

〔The invention's effect〕

The present invention is a MIS having a structure having a gate electrode on the back surface of an SOI thin film.
The present invention relates to a method for manufacturing a FET, in which the source and drain regions can be formed in a self-aligned manner by planarizing the surface of the SOI thin film by polishing or the like. In addition, since the flattened SOI thin film surface has the second gate electrode (back gate), it cannot be controlled by the gate electrode, which occurs when the SOI thin film surface and SiO _{2 which} is the surface protection film come into direct contact with each other. It is possible to control the source-drain current. Particularly, according to the present invention, since the SOI thin film surface is sufficiently flattened, there is an effect that the second gate electrode can be accurately processed in the resist process.

[Brief description of drawings]

1 (a) to 1 (d) are sectional views showing an embodiment of the present invention in the order of steps, and FIG. 2 is a sectional view showing a conventional example. 1 ... Si substrate 2, 12 ... SiO ₂ 3 ... Gate electrode 4 ... Gate insulating film 5, 7 ... Si thin film 6 ... Ion implantation layer 8 ... Source region 9 ... Drain region 10 ... Back gate insulating film 11 ... Back gate 13 ... Source electrode 14 ... Drain electrode 15 ... Back gate electrode 16 ... Channel region

Claims (1)

[Claims] 1. A method of manufacturing a MISFET using an SOI substrate, comprising the steps of forming an insulating film on a semiconductor substrate and then forming a first gate electrode, and forming a first gate on the surface of the first gate electrode. Growing an insulating film; forming a semiconductor film thicker than the total film thickness of the first gate electrode film and the first gate insulating film; and forming an impurity layer on the surface of the semiconductor film by ion implantation. Forming step, and thereafter, polishing and flattening the surface of the semiconductor film to the extent that the impurity layer on the first gate electrode is removed and the impurity layer other than on the electrode of the first gate is not removed. And a step of forming a second gate insulating film and further forming a second gate electrode having a shape that covers the entire channel region of the MISFET formed by the first gate electrode. Semiconductor device manufacturing Law.