JPH065883B2 - Signal processor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a signal processing technique and a technique particularly effective when applied to a signal output from an image sensor. For example, the present invention is applied to an image signal processing device in a facsimile. And effective technology.

[Background Art] Generally, in a facsimile, an image signal (analog video signal) from an image sensor such as a CCD is displayed along an original scanning direction in FIG. 3 due to unevenness of a lens of an optical system and a light source in an original reading unit. So-called shading distortion occurs as shown in A). In other words, even when a blank original is scanned by the image sensor, the level of the image signal of the sensor becomes lower at both ends of the original than at the central portion.

If the original is read with the shading distortion left as it is, the sensitivity is lowered at both ends of the original, and a reading error occurs.

Therefore, in order to eliminate the influence of the shading distortion, the image signal is flattened as shown by the broken line B in FIG. 3A, or the slice level (binary value is changed according to the shading distortion as shown by the broken line B in FIG. A method for correcting the threshold level) has been proposed.
An invention relating to measures against shading distortion is, for example, Japanese Patent Application No. 57-24442.

By the way, the defect of the image signal obtained from the image sensor is not limited to the above-mentioned shading distortion, but is caused by, for example, scratches of the image sensor, dust attached to the sensor, stains on the original document, or the like, as indicated by symbol n in FIG. 3 (A). , Noise may appear on the white potential side. In addition, noise may occur on the black potential side due to a leak inside the image sensor or a leak light at the reading unit.

If such noise is picked up, there is a problem that good image quality cannot be obtained.

[Object of the Invention] An object of the present invention is to provide a signal processing technique in a signal processing device such as a facsimile machine capable of removing noise carried on an image signal to obtain a good image quality.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[Outline of Invention] The outline of a typical invention disclosed in the present application will be described below.

In other words, paying attention to the fact that the noise due to scratches on the image sensor or adhered dust is relatively small, compress the upper limit on the white potential side and the lower limit on the black potential side of the image signal to such an extent as to hide the noise. However, by determining the slice level (detection level) based on this compressed voltage, it is possible to obtain a good image quality that is not affected by the noise on the white potential side and the noise on the black potential side. It achieves the purpose.

[Embodiment] FIG. 1 shows an embodiment in which the present invention is applied to a signal processing circuit for processing an image signal sent from an image sensor in a facsimile.

Although not particularly limited, each circuit block surrounded by a chain line D in the drawing is formed on a single semiconductor chip such as a single crystal silicon substrate.

A timing generation circuit 1 is provided in the signal processing circuit D, and an image sensor 20 such as a CCD (charge coupled device) is provided by a clock signal CK output from the timing generation circuit 1 to the outside of the chip.
Is driven. The serial image signal output from the image sensor 20 is the timing generation circuit 1
From the sample and hold circuit 2 driven by the sampling signal φs synchronized with the clock signal CK.

The image signal captured by the sample and hold circuit 2 is
The peak value detection circuit 3, the 7-bit A / D, D / A conversion circuit 4, and the level detection circuit 5 are supplied.

Of these, the peak value detection circuit 3 detects the peak value of the image signal having shading distortion, performs A / D conversion on the peak value, and stores the peak value in the peak value register 6, and the peak value held in the peak value register 6. Is A / D converted to form a peak value voltage Vpk, and the 7-bit A / D, D /
It is supplied to the A conversion circuit 4.

The 7-bit A / D, D / A conversion circuit 4 performs A / D conversion on the image signal a for one line when a blank original is read,
It is supplied to the delta modulation / demodulation circuit 8.

The delta modulation / demodulation circuit 8 finds the difference between the image signal a and the initial value in the initial value register 7 and stores it in the RAM (random access memory) 10. As a result, information corresponding to the shading distortion is stored in the RAM 10.

The 7-bit A / D, D / A conversion circuit 4 reads the information in the RAM 10 at the time of image transmission to read the delta modulation / demodulation circuit 8
The shading waveform on the white voltage side, that is, the maximum value V _SH of the slice level is reproduced and output from the signal demodulated in step 1 and the initial value in the register 7.

The level detection circuit 5 has, for example, 16 comparators inside, and a shading waveform V _SH on the white potential side supplied from the 7-bit A / D and D / A conversion circuit 4 and 4
Shading waveform on the black potential side supplied from the bit D / A conversion circuit 9, that is, the minimum value Vs _{L of the} slice level
The potential difference between and is divided by the internal resistance ladder to 16
A slice level in stages is formed and supplied to each of the above comparators. As a result, each slice level is changed according to the shading waveform, and the level of the image signal a input at that time is detected.

The 4-bit D / A conversion circuit 9 is adapted to form and output a plurality of levels in accordance with the set value of the level setting register 11. Moreover, each level is formed by dividing it based on the white potential side shading waveform V _SH supplied from the 7-bit A / D, D / A conversion circuit 4. for that reason,
The minimum value Vs _L of the slice level supplied from the 4-bit D / A conversion circuit 9 to the level detection circuit 5 is dynamically changed according to the shading distortion.

Like the peak value register 6 and the initial value register 7, the level setting register 11 can be externally set via the internal bus 17.

The outputs of the comparators in the bell detection circuit 5 are output in parallel and supplied to the binary encoder 12 and the demultiplexer 13. The output of the comparator supplied to the binary encoder 12 is encoded into a 4-bit binary signal here, supplied to the transmission unit 15, modulated, and then output to an external transmission unit.

The demultiplexer 13 selectively sends one of the outputs of the comparators supplied from the level detection circuit 5 to the transmission unit 15 via the internal bus 17 according to the contents set in the binarization register 14. . That is, by changing the setting value of the binarization register 14, the binarized signal can be transmitted at an arbitrary slice level.

FIG. 2 shows the 7-bit A / D, D / in the above embodiment.
A specific circuit example of part of the A conversion circuit 4 (D / A conversion unit), the level detection circuit 5, and the 4-bit D / A conversion circuit 9 is shown.

That is, the D / A of the 7-bit A / D, D / A conversion circuit 4
The conversion unit includes a 7-bit up / down counter 41 operated by an up signal φup and a down signal φdown supplied from the timing generation circuit 1, and a decoder 4 for decoding the output of the up / down counter 41.
2 and a selector 44, which uses the output of the decoder 42 as a selection signal to select one of 128-step voltages formed by the resistance ladder 43 and supply it to a buffer amplifier 45 such as a voltage follower.

The up / down counter 41 is first loaded with the initial value set in the initial value register 7, and the actual value (difference) of the image signal stored in the RAM 10 is compared with the demodulated signal and measured from this initial value. It is designed to go up or down by the difference in value.

At both ends of the resistor ladder 43, the voltage V _BL for defining the black potential supplied from the outside, the peak voltage Vpk supplied from the peak value detection circuit 3 are applied respectively, the voltage V _BL, By dividing the potential difference of Vpk by resistance division, a voltage of 128 steps is generated. Then, the selector 44 selects one of the voltages according to the selection signal from the decoder 42 and supplies it to the buffer amplifier 45.

As a result, the voltage at which the waveform corresponding to the image signal a (or the signal waveform b corrected by the peak value B) when the blank original is first read is reproduced from the buffer amplifier 45 is the slice level voltage. It is output as the maximum value V _SH .

In the embodiment of FIG. 2, the voltage V thus formed is
_The 4-bit D / A conversion circuit 9 to which _SH is supplied is composed of a resistance ladder 91, a selector 92, and a buffer amplifier 93.

The 7-bit A / D, D /
The voltage V _SH supplied from the A conversion circuit 4 and the voltage V _BL that defines the black potential are applied, and the potential difference is divided into 16 levels corresponding to the level setting register 11 having a 4-bit configuration. Has been Selector 92
Uses the set value of the level setting register 11 as a selection signal, and supplies one voltage corresponding to the set value of the register 11 among the 16 stages of voltage formed in the resistance ladder 91 to the buffer amplifier 93.

As a result, a voltage having a waveform according to the shading waveform is output from the buffer amplifier 93, and this is supplied to the level detection circuit 5 as the minimum slice level value Vs _L.

7-bit A / D, D / A conversion circuit 4 and 4-bit A / D
The level detection circuit 5, to which the voltages V _SH and Vs _L output from the D conversion circuit 9 are supplied, includes a resistor ladder 51 and 16 comparators 52a to 52p.
It is configured as a conversion circuit.

At both ends of the resistance ladder 51, the 7-bit A / D, D /
Maximum value V of the slice level supplied from the A conversion circuit 4
_SH and the minimum slice level Vs _L supplied from the 4-bit A / D conversion circuit 9 are applied, and a voltage obtained by dividing the potential difference into 16 stages by resistance division is formed. . As a result, each divided voltage is changed according to the shading waveform like the voltages V _SH and Vs _L.

The 16 levels of voltage formed by the resistance ladder 51 are applied to the reference voltage terminals of the comparators 52a to 52p, respectively. Each comparator 52a-52
The image signal a supplied from the sample and hold circuit 2 is input to the comparison terminal of p.

As a result, the comparators 52a to 52p can detect the image signal a at 16 slice levels.

According to the above embodiment, by setting appropriate values in the peak value register 6 and the level setting value register 11,
It is possible to obtain good image quality by removing noise on the white potential side and noise on the black potential side.

That is, when the image signal when a blank original is first read has a waveform (peak value is A) as shown by the solid line a in FIG. 3 (B), the peak value register 6 stores the image signal a. A peak value B smaller than the peak value A is set.
Further, by setting the initial value _Bo corresponding to the peak value B in the initial value register 7, as shown by the broken line in FIG. 3 (B), the waveform b whose level is suppressed low is used as a reference. Then, the slice level is decided. As a result, the noise n on the white potential side due to scratches on the image sensor or dust attached to the image sensor does not get caught in the maximum value V _SH of the slice level.

On the other hand, the level setting register 11 supplies the voltage V _BL from the 4-bit D / A conversion circuit 9 to the level detection circuit 5 as it is when “0” is set therein. Therefore, in that case, the minimum value Vs _L of the slice level remains constant at the voltage V _BL as in the conventional method. Then, when an appropriate value is set in the level setting register 11, the 4-bit D / A conversion circuit 9 supplies a voltage slightly higher than V _BL and having a shading waveform to the level detection circuit 5. .

As a result, the minimum value Vs _L of the slice level has a waveform as shown by the chain line C in FIG. 3 (B), so that noise on the black potential side due to leaked light or the like at the reading section does not get caught in the slice level Vs _L. Noise is removed.

Therefore, depending on the image sensor and the facsimile machine used, that is, by reading a blank original document in advance, noise on the white potential side due to scratches on the image sensor and noise on the black potential side due to leaked light at the reading unit are generated. If the size is detected and the set values of the peak value register 6, the initial value register 7, and the level setting register 11 are determined, noise peculiar to the device is removed during actual image transmission, and a good image is obtained. You can

When transmitting a document with a color background other than white, such as a blue-colored document, if the slice level is determined using the peak value B set in the peak value register 6 from the outside, the entire image signal will have the slice level. _May be lower than the maximum value V _SH . In such a case, a good binarized image signal can be obtained by holding the peak value of the actually measured image signal in the peak value register 6 and generating a slice level.

[Effect] The upper limit on the white potential side and the lower limit on the black potential side of the analog image signal supplied from a device such as an image sensor are compressed to such an extent that noise due to scratches on the image sensor is hidden, and this compression is performed. Since the slice level is determined based on the voltage, the noise on the white potential side and the noise on the black potential side do not get caught in the slice level. There is an effect that it is possible to obtain a good image quality that is not affected by noise due to leaked light or the like in a part.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments and various modifications can be made without departing from the scope of the invention. Nor. For example, in the above embodiment, the peak value register 6 and the level setting register 11 which can be set from the outside are provided to remove both the white potential side noise and the black potential side noise. However, it is possible to omit either one of the registers 6 and 11 so that only the noise on either the white potential side or the black potential side can be removed.

[Field of Use] In the above description, the invention mainly made by the present inventor was applied to an LSI for image signal processing in a facsimile which is a field of use in the background of the invention, but the present invention is not limited thereto. However, it can be used for general devices for detecting the level of analog signals.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment in which the present invention is applied to an LSI for image signal processing in a facsimile, FIG. 2 is a circuit diagram showing an example of a circuit configuration of its main part, and FIG. FIGS. 3A and 3B respectively show the output (image signal) of the image sensor. FIG. 3A is an explanatory view showing a conventional shading distortion correction method, and FIG. 3B is related to the present invention. It is explanatory drawing which shows the correction method of shading distortion. 1 ... Timing generation circuit, 2 ... Sample and hold circuit, 2 ... Peak value detection circuit, 4 ... 7-bit A / D, D /
A conversion circuit, 5 ... Level detection circuit, 6 ... Peak value register, 7 ... Initial value register, 8 ... Delta modulation / demodulation circuit, 9 ...
4-bit D / A conversion circuit, 10 ... Memory (RAM), 1
1 ... Level setting register, 12 ... Binary encoder, 13 ... Demultiplexer, 14 ... Binarization register.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Takashi Kubo 180 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi Communication Systems Co., Ltd. Hitachi Research Laboratory (72) Inventor Yoshiharu Nagayama 1450, Kamimizuhonmachi, Kodaira-shi, Tokyo Inside Device Development Center, Hitachi, Ltd. (56) Reference JP-A-56-157576 (JP, A) JP-A-59- 57572 (JP, A) JP-A-57-185768 (JP, A)

Claims (1)

[Claims] 1. A peak value detecting means for detecting a peak value of an image signal supplied from an image sensor, a peak value holding means for holding a detected peak value or a value set from the outside, and the image signal Signal processing means for sequentially A / D converting and forming a signal relating to the amount of change in the image signal;
To detect the level of the image signal based on the storage means for storing the signal processed by the signal processing means, and the signal read from the storage means and the peak value held in the peak value holding means Maximum slice level forming means for forming the maximum slice level, minimum slice level forming means for forming the minimum slice level by dividing and selecting the maximum slice level, and output from the minimum slice level forming means. A level setting register for designating a level, voltage dividing means for dividing a potential difference between the maximum slice level and the minimum slice level to generate a plurality of reference voltages, and the reference voltage at one input terminal and the other The input terminal of is provided with level detection means for receiving the image signal and detecting the level of the image signal. Information corresponding to shading distortion is stored in the storage means by inputting an image signal for one line when a blank original document is read in advance by the image sensor, and is stored when an image signal to be processed is input. The stored information is read from the means and supplied to the maximum slice level forming means to form a maximum slice level that changes corresponding to shading distortion, and the minimum slice level forming means has the maximum slice level. A signal processing apparatus, wherein a minimum slice level that changes in accordance with shading distortion is formed by supplying a level.