JPH0658916B2 - Heterojunction bipolar transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Prior Art) A heterojunction bipolar transistor (HBT) is drawing attention as a next-generation ultra-high-speed device having both high current drive capability and excellent high-frequency characteristics. By the way, the high-speed performance of the HBT is determined by the sum of the delay times of the parasitic capacitance charging time, the minority carrier base layer running time, and the collector depletion layer running time, but each delay time is about 1/3 of the total. Is the size of. Although recent improvements in technology have made it possible to reduce parasitic capacitance and parasitic resistance and shorten the base layer travel time, the issue is to shorten the collector depletion layer travel time, which is about the same as or larger than the base layer thickness. Has become.

FIG. 4 is a band structure diagram of a first example of a conventional HBT. The HBT in this example has a structure in which a p-type base layer 44 and an n-type emitter layer 43 having a wider forbidden band than the base layer 44 are sequentially stacked on the n-type collector layer 45, and under the operating condition, A collector depletion layer 45d spreads in the collector layer 45, and an electric field generated from the potential difference 45 between the base and collector is applied to the collector depletion layer 45d. In the case of the HBT having the structure shown in FIG. 4, it is necessary to make the bias between the base and collector sufficiently large in order to make the collector depletion capacitance sufficiently large, and the electric field generated in the collector depletion layer 45d at that time becomes very strong. The electrons 8a that have finished traveling through the base layer are collector depletion layers
When entering 45d, as a result of receiving the extremely strong electric field, most of the electrons 8b move to the L valley 14 of the conduction band. However, since the electron effective mass of the L valley of the conduction band is larger than the electron effective mass of the Γ valley which is the bottom of the conduction band, the speed at which the electron 8c travels in the collector depletion layer 45d becomes slow, and the high-speed performance of the HBT is markedly reduced. It will be limited.

FIG. 5 is a band structure diagram of a second example of a conventional HBT. The HBT of this example has a collector structure of a collector layer 5i made of an intrinsic semiconductor and a thin layer 6p made of a high-concentration p-type semiconductor material.
And a high-concentration n-type layer 6 for making contact with the collector. As a result, of the potential difference 515 between the base and collector, only the potential difference 516 of the pn junction between the thin p-type layer 6p and the high-concentration n-type layer 6 is concentrated in this pn junction portion, so that the electric field applied to the collector layer 5i is Greatly eased. At this time, the electrons 8b traveling in the collector layer 5i can travel at high speed without being adversely affected by the strong electric field, and the high-speed performance of the HBT is remarkably improved.

(Problems to be solved by the invention) However, in the HBT having such a collector structure,
Since the highly doped pn junction exists in the collector portion, there is a disadvantage that the breakdown voltage is weak and the transistor operation becomes unstable. This becomes more serious when a semiconductor material having a narrow band gap is used. Such structural instability that the operation is unstable can be avoided when a single transistor is operated under a constant optimum bias condition, but in the case of configuring a circuit using these HBTs, individual Since the bias variation range applied to the HBT is wide, it is difficult to construct a high-speed logic circuit that is stable and takes advantage of the high speed of a single HBT.

In addition, the advantage of HBT in Fig. 5 is that the high concentration p
It appears only when the impurity concentration of the mold layer 6p is kept high, but when it is difficult to trap high-concentration impurities in a thin layer due to heat during the manufacturing process or use, There is a reliability problem in the structure of the HBT in Fig. 5.

An object of the present invention is to provide an ultra-high speed heterojunction bipolar transistor which has stable transistor operation performance, can be easily applied to a high speed logic circuit and the like, and has a thermally stable crystal structure.

(Means for Solving the Problem) According to the present invention, a first collector layer having a constant bandgap and having the same conductivity type as that of the intrinsic or base and a low concentration is provided in the order in which the collector layer is closer to the base layer. The heterojunction bipolar transistor is characterized by comprising a second collector layer having a high electron affinity, a high concentration, and a narrow bandgap as compared with the collector layer.

(Operation) According to the present invention as described above, according to the HBT, among the potential differences between the base and the collector, the difference Δ in the electron affinity generated at the heterojunction interface between the first collector layer and the second collector layer.
Since x is concentrated on this heterojunction interface, the potential change in the first collector layer is reduced by Δx. As a result, electrons can drift in the collector part at high speed as in the conventional HBT shown in FIG. 5, but in the collector part of the HBT shown in FIG. 5, the electric field in the electron drift region is relaxed. It is the electron affinity difference caused by the pn junction of the same semiconductor material, while in the case of the HBT of the present invention, the semiconductor material forming the first collector layer and the semiconductor material forming the second collector layer Is a crystallographic electron affinity difference between the. This heterojunction between the first collector layer and the second collector layer has not only a higher breakdown voltage than the pn junction in the collector section of the conventional HBT shown in FIG. 5 but also a thermally stable junction. Is. Therefore, using the HBT of the present invention, it is possible to construct a high-speed logic circuit having high reliability and utilizing the capability of a single HBT.

(Embodiment) FIG. 1 is a sectional view of an embodiment of the present invention. In this embodiment, the semi-insulating substrate 1 is partitioned by an insulating region 1a having a predetermined pattern formed by ion implantation of protons provided on the surface of the semi-insulating substrate 1 and the impurity concentration is 5 × 10 ¹⁸ atom / cm ³ with Si as a dopant.
A high-concentration layer 2 consisting of an n ⁺ -GaAs layer with a layer thickness of 2000 Å was formed by the MBE method.Si was used as a dopant on the high-concentration layer 2 with an impurity concentration of 3 × 10 ¹⁸ atom / cm ³ and a layer thickness of 2000 Å n. -Al _0.25 Ga
Emitter layer 3 consisting of _0.75 As layer, base layer 4 consisting of p ⁺ -GaAs with a dopant concentration of Be of 2 × 10 ¹⁹ atom / cm ³ and impurity concentration of 1000 Å, i-GaAs with impurity-free layer thickness of 2000 Å
The first collector layer 5a composed of a layer, and the impurity concentration is 5 × 10 ¹⁸ atom / cm ³ thickness dopant as Si of 700 Å n ⁺ _- InA
The second collector layer 5b composed of the s layer is sequentially formed by the MBE method, each layer of the second collector layer 5b to the emitter layer 3 is sequentially etched into a predetermined pattern, and then the high concentration layer 2, the second collector layer 5b, and the base layer 4 are formed. It has a structure in which an emitter, a collector, and base electrodes 7e, 7c, and 7b are formed on the above.

2 (a), (b) is a band structure diagram of one embodiment of the present invention, FIG. 2 (a), the emitter, the base and collector electrodes are electrically open, FIG. 2 (b) is a diagram showing that the transistor is in an operating state by applying forward and reverse biases between the emitter and the base and between the base and the collector, respectively.

In the band structure of this embodiment, the collector region is composed of a first collector layer 5a composed of an i-GaAs layer and a second collector layer 5b composed of an n ⁺ -InAs layer, and InAs has a much larger electron affinity than GaAs. Therefore, a large conduction band discontinuity 16a or 16b corresponding to the electron affinity difference Δx occurs at the interface between the first collector layer 5a and the second collector layer 5b. as a result,
The potential difference in the first collector layer 5a, which is the region where the magnitude of the electron velocity governs the delay time in the collector section, is the potential difference between the base and collector 15a or 1
It is smaller than 5b by Δx, and the electric field strength applied to the inside of the first collector layer 5a is significantly relaxed. In this embodiment, since the first collector layer and the second collector layer are made of semiconductor materials having crystallographically different electron affinities, it is necessary to form a pn junction in a semiconductor material that originally has the same electron affinity. Therefore, the band structure has a high withstand voltage and is thermally stable as compared with the case where the electron affinity difference is forcibly generated. Thus, electron affinity is different crystallographically2
By joining two semiconductor materials, it is possible to obtain a band structure in which electrons travel at high speed in the collector without the need of providing a highly reliable thin high-concentration p-type layer.

FIG. 3 is an energy band diagram of the second embodiment of the present invention, in which the In composition is changed from GaAs to In _0.4 Ga _0.6 As on the top of the first collector layer 5a made of the i-GaAs layer. _x Ga _1-x As layer
A composition gradient layer 5g made of (x = 0 → 0.4) is grown, and a second collector layer 5b made of an n ⁺ -InAs layer is further grown on the composition gradient layer 5g by the MBE method. Also in the present embodiment, as in the first embodiment, the potential difference in the first collector layer 5a is determined by the electron affinity difference Δx16 between GaAs forming the first collector layer 5a and InAs forming the second collector layer 5b. The potential difference between the base and collector is reduced by 15 minutes. The composition gradient layer 5 provided on the upper part of the first collector layer 5a has a state in which electrons easily become hot electrons in the first collector layer and are easily transferred from the Γ valley to the L valley. It is provided for the purpose of suppressing the transition from the Γ valley to the L valley by increasing the energy difference between the (bottom) and the L valley, and for relaxing the lattice strain generated between GaAs and InAs having large lattice constants. ing.

In this embodiment, the first collector layer is made of an intrinsic semiconductor material, but it is sufficient that the movable charge in the first collector layer is depleted, and it may be doped with a low concentration p-type impurity, for example. However, even if the first collector layer is doped with p-type impurities in the same manner as the base layer and is regarded as a collector layer substantially, it is not used as a part of the base layer but as the first collector layer of the present invention. It is intended to be included in the claims. In this embodiment, GaAs is used as the semiconductor material of the first collector layer and InAs is used as the semiconductor material of the second collector layer, but the material is not limited to this, and the electron affinity of the semiconductor material of the second collector layer is the first collector layer. It does not matter whether it is larger than the electron affinity of the semiconductor material of the layer or whether the lattice is a matched system or a mismatched system.

(Effects of the Invention) As described above, in the present invention, the difference in electron affinity between the region where electrons are required to travel at high speed and the high-concentration impurity region in the collector portion causes the electron affinity to differ crystallographically. Since it is generated by joining semiconductor materials, the collector structure in which electrons travel through the collector at high speed has been realized with good transistor operation stability and reliability, and by utilizing the excellent high-speed performance of a single HBT, high speed is achieved. This has the effect of facilitating the configuration of logic circuits and the like.

[Brief description of drawings]

1 and 2 are respectively a first embodiment of the present invention and a sectional view and a band structure diagram, FIG. 3 is a band structure diagram of a second embodiment of the present invention, FIG. 4 and FIG. FIG. 3 is a band structure diagram of first and second examples of conventional heterojunction bipolar transistors, respectively. In the figure, 1 ... semi-insulating substrate, 1a ... insulating region, 2 ... high-concentration layer,
3 ... Emitter layer, 4,44 ... Base layer, 45 ... Collector layer, 5a ... First collector layer, 5b ... Second collector layer, 45d
...... Collector depletion layer, 5g …… Composition gradient layer, 5i …… Intrinsic collector layer, 6p …… High concentration p-type layer, 6 …… High concentration n-type layer, 7c
...... Collector electrode, 7b ...... Base electrode, 7e ...... Emitter electrode, 8a, 8b, 8c ...... Electron, 14 ...... Conduction band L valley.

Claims (1)

[Claims] 1. A first collector layer having a constant bandgap in the order of proximity to the base layer and having a constant bandgap and having the same conductivity type as the intrinsic type and a low concentration, and an electron affinity as compared with the first collector layer. And a second collector layer having a large and high concentration and a narrow bandgap, and a heterojunction bipolar transistor.