JPH0658956B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0658956B2 JPH0658956B2 JP61215053A JP21505386A JPH0658956B2 JP H0658956 B2 JPH0658956 B2 JP H0658956B2 JP 61215053 A JP61215053 A JP 61215053A JP 21505386 A JP21505386 A JP 21505386A JP H0658956 B2 JPH0658956 B2 JP H0658956B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- semiconductor device
- forming
- layer
- mesa
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 39
- 238000000034 method Methods 0.000 title description 19
- 238000004519 manufacturing process Methods 0.000 title description 13
- 239000000758 substrate Substances 0.000 claims description 10
- 230000004888 barrier function Effects 0.000 claims description 8
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 21
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 12
- 238000005530 etching Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- 238000002955 isolation Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 239000002784 hot electron Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
- H10D48/30—Devices controlled by electric currents or voltages
- H10D48/32—Devices controlled by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H10D48/36—Unipolar devices
- H10D48/362—Unipolar transistors having ohmic electrodes on emitter-like, base-like, and collector-like regions, e.g. hot electron transistors [HET], metal base transistors [MBT], resonant tunnelling transistors [RTT], bulk barrier transistors [BBT], planar doped barrier transistors [PDBT] or charge injection transistors [CHINT]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/117—Shapes of semiconductor bodies
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
- H10D62/815—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW]
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Crystallography & Structural Chemistry (AREA)
- Bipolar Transistors (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Description
【発明の詳細な説明】 〔概要〕 本発明は、半導体装置の製造方法に於いて、基板上の半
導体層からなるメサの側面に超格子を形成することに依
り、超格子を形成するプロセスの困難性を解消したもの
である。DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to a process for forming a superlattice by forming a superlattice on a side surface of a mesa formed of a semiconductor layer on a substrate in a method for manufacturing a semiconductor device. It eliminates the difficulty.
本発明は、横方向にヘテロ接合、即ち、超格子（ｓｕｐ
ｅｒ ｌａｔｔｉｃｅ：ＳＬ）を有する半導体装置を製
造するのに好適な方法に関する。The present invention is based on a lateral heterojunction, or superlattice.
The present invention relates to a method suitable for manufacturing a semiconductor device having an er lattice (SL).
第７図は一般的な共鳴トンネリング・ホット・エレクト
ロン・トランジスタ（ｒｅｓｏｎａｎｔ−ｔｕｎｎｅｌ
ｉｎｇ ｈｏｔ ｅｌｅｃｔｒｏｎ ｔｒａｎｓｉｓｔ
ｏｒ：ＲＨＥＴ）の要部切断側面図を表している。FIG. 7 shows a general resonant tunneling hot electron transistor.
ing hot electron transist
(or: RHET) is a side view of a main part cut away.
図に於いて、１１は半絶縁性ＧａＡｓからなる基板、１
２はｎ＋型ＧａＡｓコレクタ層、１３はＡｌＧａＡｓコ
レクタ側バリヤ層、１４はｎ＋型ベース層、１５ＡはＳ
Ｌを構成するＡｌＧａＡｓ膜、１５ＢはＳＬを構成する
ＧａＡｓ膜、１６はｎ＋型エミッタ層、１７はエミッタ
電極、１８はベース電極、１９はコレクタ電極をそれぞ
れ示している。尚、バリヤ膜１５Ａ及びウエル膜１５Ｂ
で構成されたＳＬはエミッタ側バリヤ層をなしているこ
とは云うまでもない。In the figure, 11 is a substrate made of semi-insulating GaAs, 1
2 is an n + type GaAs collector layer, 13 is an AlGaAs collector side barrier layer, 14 is an n + type base layer, and 15A is S.
Reference numeral 15B is an AlGaAs film forming L, 15B is a GaAs film forming SL, 16 is an n + -type emitter layer, 17 is an emitter electrode, 18 is a base electrode, and 19 is a collector electrode. In addition, the barrier film 15A and the well film 15B
It goes without saying that the SL constituted by (1) forms a barrier layer on the emitter side.
ここでＡｌＧａＡｓ膜１５ＡはＳＬに於けるバリヤとし
て、また、ＧａＡｓ膜１５ＢはＳＬに於けるウエルとし
て動作するものであり、ＧａＡｓ膜１５ＢにはＡｌＧａ
Ａｓ膜１５Ａから電子が滲み出してきて、そこに閉じ込
められるので、モビリティが向上するなどの利点があ
る。尚、このようなＲＨＥＴでは、ＳＬの部分のみでな
く、コレクタ側バリヤ層１３とコレクタ層１２或いはベ
ース層１４その間にもヘテロ接合が存在していることは
云うまでもない。Here, the AlGaAs film 15A functions as a barrier in SL, the GaAs film 15B functions as a well in SL, and the GaAs film 15B has AlGa.
Electrons seep out from the As film 15A and are confined therein, which has advantages such as improved mobility. Needless to say, in such a RHET, a heterojunction exists not only in the SL portion but also between the collector-side barrier layer 13 and the collector layer 12 or the base layer 14.
第７図について一例を説明したように、従来のヘテロ接
合半導体装置を製造する場合、諸半導体層を縦方向に積
層するようにしているので、そのヘテロ接合も縦方向に
生成されることになる。As described above with reference to FIG. 7, when manufacturing a conventional heterojunction semiconductor device, since the semiconductor layers are stacked vertically, the heterojunction is also generated vertically. .
従って、その製造プロセスの面で種々の問題を生じてい
て、特に、素子間分離をする為に深いエッチングを行う
必要がある。Therefore, various problems occur in terms of the manufacturing process, and in particular, it is necessary to perform deep etching for element isolation.
第７図に見られるＲＨＥＴでは、コレクタ層１２：１０
００〔Å〕 コレクタ側バリヤ層１３：２０００〔Å〕 ベース層１４：１０００〔Å〕 ＡｌＧａＡｓ層１５Ａ：５０〔Å〕 ＧａＡｓ層１５Ｂ：５０〔Å〕 エミッタ層１６：４０００〔Å〕 となっていて、素子間分離には約１〔μｍ〕程度もエッ
チングする必要があり、しかも、電極導出の為に複雑な
階段状メサ・エッチングを行わなければならない。In the RHET seen in FIG. 7, the collector layer 12:10
00 [Å] Barrier layer on collector side 13: 2000 [Å] Base layer 14: 1000 [Å] AlGaAs layer 15A: 50 [Å] GaAs layer 15B: 50 [Å] Emitter layer 16: 4000 [Å] In order to separate the elements, it is necessary to etch about 1 [μm], and moreover, complicated stepwise mesa etching must be performed to lead out the electrodes.
従って、この種の半導体装置の製造歩留りは大変悪いも
のとなっている。Therefore, the manufacturing yield of this type of semiconductor device is very poor.
本発明は、ヘテロ接合を横方向に形成することに依り、
半導体装置に大きな段差が生ずることを防止し、製造プ
ロセスを容易なものとして歩留りを高め、また、安価に
製造できるようにする。The present invention relies on the lateral formation of the heterojunction,
A large step is prevented from being generated in a semiconductor device, a manufacturing process is facilitated to increase a yield, and a semiconductor device can be manufactured at low cost.
本発明による半導体装置の製造方法に於いては、半絶縁
性基板（例えば半絶縁性ＧａＡｓ基板１）上に一導電型
の第１の半導体層（例えばｎ＋型ＧａＡｓ電極コンタク
ト層２）からなるメサを形成する工程と、前記メサの側
面を含む領域にバリヤとなる半導体層（例えばＡｌＧａ
Ａｓ膜３及び５）とウエルとなる半導体層（例えばＧａ
Ａｓ膜４）とが交互に重なる超格子を形成する工程と、
前記超格子構造を含む前記半導体基板上に、前記第１の
半導体層と同導電型の第２の半導体層（例えばｎ＋型Ｇ
ａＡｓ電極コンタクト層６）を形成する工程と、前記メ
サ上に、前記第１の半導体層が露出する開口を形成する
工程と、前記開口内と前記メサ領域外の第２の半導体層
上にオーミック電極を形成する工程とが含まれてなる構
成になっている。In the method of manufacturing a semiconductor device according to the present invention, a first conductivity type first semiconductor layer (eg, n + type GaAs electrode contact layer 2) is formed on a semi-insulating substrate (eg, semi-insulating GaAs substrate 1). A step of forming a mesa, and a semiconductor layer (for example, AlGa) serving as a barrier in a region including a side surface of the mesa.
As layers 3 and 5) and a semiconductor layer (for example, Ga) serving as a well.
Forming a superlattice with alternating As films 4),
On the semiconductor substrate including the superlattice structure, a second semiconductor layer having the same conductivity type as the first semiconductor layer (for example, n + -type G
forming an aAs electrode contact layer 6), forming an opening on the mesa exposing the first semiconductor layer, and forming an ohmic contact on the second semiconductor layer in the opening and outside the mesa region. And a step of forming electrodes.
前記手段を採ることに依り、超格子を横方向に形成する
ことができ、ヘテロ接合半導体装置に大きな段差を生じ
させることなく素子間分離を行うことが可能となり、製
造プロセスが容易且つ簡単化されるので歩留りが向上
し、その結果、この種の半導体装置を安価に提供するこ
とができる。By adopting the above means, the superlattice can be formed in the lateral direction, and the element isolation can be performed without causing a large step in the heterojunction semiconductor device, which simplifies and simplifies the manufacturing process. Therefore, the yield is improved, and as a result, this type of semiconductor device can be provided at low cost.
第１図乃至第６図は本発明一実施例を解説する為の工程
要所に於ける半導体装置の要部切断側面図を表し、以
下、これ等の図を参照しつつ説明する。尚、ここでは、
共鳴トンネリング・ダイオード（ｒｅｓｏｎａｎｔ−ｔ
ｕｎｎｅｌｉｎｇ ｄｉｏｄｅ：ＲＴＤ）を製造する場
合を対象としている。1 to 6 are sectional side views of a main portion of a semiconductor device at a process step for explaining an embodiment of the present invention, which will be described below with reference to these figures. In addition, here
Resonant tunneling diode (resonant-t)
It is intended for the case of manufacturing an uniling diode (RTD).
第１図参照 (1)分子線エピタキシャル成長（ｍｏｌｅｃｕｌａｒ
ｂｅａｍ ｅｐｉｔａｘｙ：ＭＢＥ）法を適用すること
に依り、半絶縁性ＧａＡｓ基板１上にｎ＋型ＧａＡｓ電
極コンタクト層２を形成する。See Fig. 1 (1) Molecular beam epitaxial growth (molecular)
The n + type GaAs electrode contact layer 2 is formed on the semi-insulating GaAs substrate 1 by applying the beam epitaxy (MBE) method.
この電極コンタクト層２は、 厚さ：２０００〔Å〕 不純物濃度：２×１０１８〔cm-3〕 としてある。The electrode contact layer 2 has a thickness of 2000 [Å] and an impurity concentration of 2 × 10 18 [cm -3 ].
(2)通常のフォト・リソグラフィ技術を適用することに
依り、ｎ型ＧａＡｓ電極コンタクト層２のエッチングを
行ってメサを形成する。(2) The mesa is formed by etching the n-type GaAs electrode contact layer 2 by applying an ordinary photolithography technique.
このメサの大きさは、平面的に見て、例えば２〔μｍ〕
×１０〔μｍ〕程度が選択される。The size of this mesa is, for example, 2 [μm] in plan view.
About 10 [μm] is selected.
(3)ＭＢＥ法を適用することに依り、厚さ例えば５０
〔Å〕のＡｌＧａＡｓ膜３を形成する。(3) By applying the MBE method, the thickness is, for example, 50
The AlGaAs film 3 of [Å] is formed.
第２図参照 (4)ＭＢＥ法を適用することに依り、厚さが５０〔Å〕
であるＧａＡｓ膜４を形成する。See Fig. 2 (4) The thickness is 50 [Å] due to the MBE method.
Then, the GaAs film 4 is formed.
第３図参照 (5)ＭＢＥ法を適用することに依り、厚さが５０〔Å〕
であるＡｌＧａＡｓ膜５を形成する。See Fig. 3 (5) The thickness is 50 [Å] by applying the MBE method.
Then, the AlGaAs film 5 is formed.
前記のようにして形成したＡｌＧａＡｓ膜３、ＧａＡｓ
膜４、ＡｌＧａＡｓ膜５はＳＬを構成していることは勿
論であり、これ等は必要に応じて更に多層にして良い。AlGaAs film 3 and GaAs formed as described above
Needless to say, the film 4 and the AlGaAs film 5 constitute SL, and these may be further multilayered if necessary.
第４図参照 (6)ＭＢＥ法を適用することに依り、ｎ＋型ＧａＡｓ電
極コンタクト層６を形成する。See FIG. 4. (6) The n + type GaAs electrode contact layer 6 is formed by applying the MBE method.
この電極コンタクト層６は、 厚さ：１０００〔Å〕 不純物濃度：１×１０１８〔cm-3〕 としてある。The electrode contact layer 6 has a thickness of 1000 [Å] and an impurity concentration of 1 × 10 18 [cm -3 ].
第５図参照 (7)通常のフォト・リソグラフィ技術を適用することに
依り、ｎ＋型ＧａＡｓ電極コンタクト層２の上面に対向
するＳＬの部分及びｎ＋型ＧａＡｓ電極コンタクト層６
をエッチングしてリセス７を形成する。See FIG. 5 (7) By applying a normal photolithography technique, the SL portion facing the upper surface of the n + type GaAs electrode contact layer 2 and the n + type GaAs electrode contact layer 6
To form the recess 7.
(8)通常のフォト・リソグラフィ技術のレジスト・プロ
セス及びリフト・オフ法を適用することに依り、電極８
及び９を形成する。尚、記号８Ａ及び９Ａは合金化領域
を指示している。(8) The electrode 8 is formed by applying the resist process and lift-off method of the ordinary photolithography technique.
And 9 are formed. The symbols 8A and 9A indicate alloying regions.
このようにして作成されたＲＴＤでは、ｎ＋型ＧａＡｓ
電極コンタクト層２の側面に形成されているＡｌＧａＡ
ｓ膜５、ＧａＡｓ膜４、ＡｌＧａＡｓ膜３の部分がＳＬ
として作用する。In the RTD thus created, n + type GaAs
AlGaA formed on the side surface of the electrode contact layer 2
The s film 5, GaAs film 4, and AlGaAs film 3 are SL
Acts as.
第６図は本発明に於ける他の実施例を説明する為の工程
要所に於けるＲＴＤの要部切断側面図を表し、第１図乃
至第５図に於いて用いた記号と同記号は同部分を示すか
或いは同じ意味を持つものとする。FIG. 6 is a sectional side view of a main part of an RTD at a process step for explaining another embodiment of the present invention, which is the same symbol as that used in FIGS. 1 to 5. Indicate the same part or have the same meaning.
この実施例では、前記工程(3)の後、エッチング・ガス
をＣＦ４とする反応性イオン・エッチング（ｒｅａｃｔ
ｉｖｅ ｉｏｎ ｅｔｃｈｉｎｇ：ＲＩＥ）法を適用す
ることに依り、ＡｌＧａＡｓ膜３の異方性エッチングを
行ってｎ＋型ＧａＡｓ電極コンタクト層２の側面に被着
された部分のみを残して他を除去し、次いで、前記工程
(4)に依ってＧａＡｓ膜４を形成してから同様に異方性
エッチングを行い、このような工程を繰り返すことで図
示のような構造を得るものである。In this embodiment, after the step (3), the reactive ion etching (react) using CF 4 as an etching gas is performed.
iv) is used to perform anisotropic etching of the AlGaAs film 3 to remove only the portion deposited on the side surface of the n + -type GaAs electrode contact layer 2 and remove the others. Then, the step
After the GaAs film 4 is formed according to (4), anisotropic etching is similarly performed, and such a process is repeated to obtain the structure shown in the drawing.
この実施例に依って得られる半導体装置は、動作上の無
駄な部分がなく、形状が良好であるが、製造プロセスが
複雑になる。The semiconductor device obtained according to this embodiment has no wasteful part in operation and has a good shape, but the manufacturing process becomes complicated.
本発明は、半導体装置の製造方法に於いて、基板上の半
導体層からなるメサの側面に超格子を形成する構成にな
っている。According to the present invention, in a method of manufacturing a semiconductor device, a superlattice is formed on a side surface of a mesa composed of a semiconductor layer on a substrate.
前記構成を採ることに依り、超格子を横方向に形成する
ことができ、ヘテロ接合半導体装置に大きな段差を生じ
させることなく素子間分離を行うことが可能となり、製
造プロセスが容易且つ簡単化されるので歩留りが向上
し、その結果、この種の半導体装置を安価に提供するこ
とができる。By adopting the above configuration, the superlattice can be formed in the lateral direction, and the element isolation can be performed without causing a large step in the heterojunction semiconductor device, and the manufacturing process is easy and simplified. Therefore, the yield is improved, and as a result, this type of semiconductor device can be provided at low cost.
第１図乃至第５図は本発明一実施例を説明する為の工程
要所に於ける半導体装置の要部切断側面図、第６図は本
発明に於ける他の実施例を説明する為の工程要所に於け
る半導体装置の要部切断側面図、第７図はＲＨＥＴの要
部切断側面図をそれぞれ表している。 図に於いて、１は半絶縁性ＧａＡｓ基板、２はｎ＋型Ｇ
ａＡｓ電極コンタクト層、３はＡｌＧａＡｓ膜、４はＧ
ａＡｓ膜、５はＡｌＧａＡｓ膜、６はｎ＋型電極コンタ
クト層、７はリセス、８及び９は電極、８Ａ及び９Ａは
合金化領域をそれぞれ示している。FIGS. 1 to 5 are side views of a semiconductor device cut along a main part of a process for explaining an embodiment of the present invention, and FIG. 6 is for explaining another embodiment of the present invention. FIG. 7 is a side sectional view of a main part of the semiconductor device at the process key point, and FIG. 7 is a side sectional view of the main part of the RHET. In the figure, 1 is a semi-insulating GaAs substrate, 2 is n + type G
aAs electrode contact layer, 3 AlGaAs film, 4 G
a as film, 5 is an AlGaAs film, 6 is an n + type electrode contact layer, 7 is a recess, 8 and 9 are electrodes, and 8A and 9A are alloyed regions.
Claims (1)
半導体層からなるメサを形成す工程と、 前記メサの側面を含む領域に、バリヤとなる半導体層と
ウエルとなる半導体層とが交互に重なる超格子構造を形
成する工程と、 前記超格子構造を含む前記半導体基板上に、前記第１の
半導体層と同導電型の第２の半導体層を形成する工程
と、 前記メサ上に、前記第１の半導体層が露出する開口を形
成する工程と、 前記開口内の第１の半導体層と、前記メサ領域外の第２
の半導体層上にオーミック電極を形成する工程とを具備
することを特徴とする半導体装置の製造方法。1. A step of forming a mesa composed of a first semiconductor layer of one conductivity type on a semi-insulating semiconductor substrate, and a semiconductor layer serving as a barrier and a semiconductor layer serving as a well in a region including a side surface of the mesa. A step of forming a superlattice structure in which and superimpose alternately, a step of forming a second semiconductor layer of the same conductivity type as the first semiconductor layer on the semiconductor substrate including the superlattice structure, and the mesa Forming an opening on which the first semiconductor layer is exposed, a first semiconductor layer in the opening, and a second semiconductor layer outside the mesa region.
And a step of forming an ohmic electrode on the semiconductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61215053A JPH0658956B2 (en) | 1986-09-13 | 1986-09-13 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61215053A JPH0658956B2 (en) | 1986-09-13 | 1986-09-13 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6372157A JPS6372157A (en) | 1988-04-01 |
| JPH0658956B2 true JPH0658956B2 (en) | 1994-08-03 |
Family
ID=16665980
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61215053A Expired - Lifetime JPH0658956B2 (en) | 1986-09-13 | 1986-09-13 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0658956B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0669110B2 (en) * | 1985-03-04 | 1994-08-31 | 株式会社日立製作所 | Semiconductor laser device |
-
1986
- 1986-09-13 JP JP61215053A patent/JPH0658956B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6372157A (en) | 1988-04-01 |
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| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |