JPH0658976B2 - Method for manufacturing compound semiconductor device - Google Patents
Method for manufacturing compound semiconductor deviceInfo
- Publication number
- JPH0658976B2 JPH0658976B2 JP28156284A JP28156284A JPH0658976B2 JP H0658976 B2 JPH0658976 B2 JP H0658976B2 JP 28156284 A JP28156284 A JP 28156284A JP 28156284 A JP28156284 A JP 28156284A JP H0658976 B2 JPH0658976 B2 JP H0658976B2
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- Prior art keywords
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- type
- impurity
- germanium
- substrate
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/81—Bodies
- H10H20/811—Bodies having quantum effect structures or superlattices, e.g. tunnel junctions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/81—Bodies
- H10H20/822—Materials of the light-emitting regions
- H10H20/824—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP
Landscapes
- Semiconductor Lasers (AREA)
- Light Receiving Elements (AREA)
- Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
- Junction Field-Effect Transistors (AREA)
- Led Devices (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は化合物半導体装置の製造方法、更に詳しくは、
発光素子およびトランジスタなどに有用な、単一不純物
を添加してなるp-n接合を有するアルミニウムガリウム
砒素系化合物半導体装置の製造方法に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a method for manufacturing a compound semiconductor device, and more specifically,
The present invention relates to a method for manufacturing an aluminum gallium arsenide-based compound semiconductor device having a pn junction formed by adding a single impurity, which is useful for a light emitting element, a transistor, and the like.
化合物半導体の液相成長法は、例えば溶融ガリウム(Ga)
溶液に高温でガリウム砒素(GaAs)、アルミニウム(Al)お
よび適当な不純物を溶解させてアルミニウムガリウム砒
素(AlGaAs)の飽和溶液を作り、この飽和Ga溶液をGaAsま
たはAlGaAs基板上に接触させ徐冷することによりAlGaAs
結晶を成長させることからなっている。Liquid phase epitaxy of compound semiconductors includes, for example, molten gallium (Ga)
Gallium arsenide (GaAs), aluminum (Al) and appropriate impurities are dissolved in the solution at high temperature to make a saturated solution of aluminum gallium arsenide (AlGaAs), and this saturated Ga solution is brought into contact with the GaAs or AlGaAs substrate and gradually cooled. By AlGaAs
It consists of growing crystals.
この液相成長法によって、p-n接合を有する化合物半導
体を得るには、一般にp形伝導性を示すp形不純物とn
形伝導性を示すn形不純物とをそれぞれ添加した溶液か
ら形成するか、またはp形およびn形伝導性の両方を示
す両性不純物を添加した溶液から形成する方法がある。In order to obtain a compound semiconductor having a pn junction by this liquid phase growth method, generally, p-type impurities and p-type impurities exhibiting p-type conductivity are used.
There is a method of forming from a solution added with an n-type impurity exhibiting type conductivity or a solution added with an amphoteric impurity exhibiting both p-type and n-type conductivity.
従来、GaAsおよびAlxGa1-xAsにおいて、結晶成長により
p-n接合を形成する場合一般にp形不純物としてZn,Be,M
gなどを用いているが、これらの不純物は結晶成長中お
よびその後の熱処理中に拡散により移動するため、当初
のp-n接合の位置がn形側に移動することとなり、p-n接
合の不純物分布および位置の制御が困難である。このこ
とを第5図をもって従来のAlGaAsのp-n接合について説
明すると、液相エピタキシャル成長法により、n形GaAs
基板11上にn形不純物Teをドープしたn形AlxGa1-xAs層
12を結晶成長せしめ、次にp形不純物Znをドープしたp
形AlyGa1-yAs層14を前記n形層12の上にエピタキシャル
成長させている。この場合、本来不純物Znが拡散しなけ
ればp-n接合の位置16は、n形層12とp形層14の界面に
あるはずである。しかしながら、p形AlyGa1-yAs層14の
結晶成長中に不純物Znの拡散による移動がおきて、p-n
接合面が当初の接合位置16からn形AlxGa1-xAs層12中へ
と移動する。移動した接合位置15を破線で示す。そのた
め、n形層中に図に示すようにp形AlxGa1-xAs層13が形
成される。このようにp-n接合面がずれる現象は、x≠
yのヘテロ接合のとき問題で、ヘテロp−n接合を作っ
たつもりが実は、p形AlxGa1-xAs層13とn形AlxGa1-xAs
層12とのホモp−n接合となるため、発光素子としたと
きキャリアのとじ込め効果や、少数のキャリアの注入効
率などが減少し、発光効率が悪くなるとか、またトラン
ジスタの場合ではZnをドープしたp形AlGaAsをベースと
すると、n形エミッタ、コレクタ側にZnが拡散してベー
ス巾が広くなり、周波数特性が低下するという問題を生
ずる。Conventionally, due to crystal growth in GaAs and Al x Ga 1-x As
When forming a pn junction, Zn, Be, M are generally used as p-type impurities.
Although g is used, these impurities move by diffusion during crystal growth and subsequent heat treatment, so the initial position of the pn junction moves to the n-type side. Is difficult to control. This will be explained with reference to FIG. 5 for a conventional AlGaAs pn junction. The n-type GaAs is formed by liquid phase epitaxial growth.
N-type Al x Ga 1-x As layer doped with n-type impurity Te on the substrate 11
12 was crystal-grown and then p-doped with p-type impurity Zn
An Al y Ga 1-y As layer 14 is epitaxially grown on the n-type layer 12. In this case, the position 16 of the pn junction should be at the interface between the n-type layer 12 and the p-type layer 14 unless the impurity Zn originally diffuses. However, during the crystal growth of the p-type Al y Ga 1-y As layer 14, movement due to diffusion of the impurity Zn occurs and pn
The bonding surface moves from the initial bonding position 16 into the n-type Al x Ga 1-x As layer 12. The moved joining position 15 is indicated by a broken line. Therefore, the p-type Al x Ga 1-x As layer 13 is formed in the n-type layer as shown in the figure. The phenomenon in which the pn junction surface is displaced is such that x ≠
problem when y heterojunction, going to made a hetero p-n junction is actually, p-type Al x Ga 1-x As layer 13 and the n-type Al x Ga 1-x As
Since it becomes a homo pn junction with the layer 12, the effect of confining carriers when used as a light emitting element, the efficiency of injecting a small number of carriers, etc. decreases, and the light emitting efficiency deteriorates. When doped p-type AlGaAs is used as a base, Zn diffuses toward the n-type emitter and collector sides to widen the width of the base, which causes a problem of deterioration in frequency characteristics.
一方、第IV族元素である珪素(Si)はp形およびn形伝導
性を示す両性不純物であることが、GaAsで示されてお
り、同族であるゲルマニウム(Ge)についても両極性が期
待されている。特にSiは同一不純物の添加によってGaAs
中にp−n接合を形成することができ、このものは結晶
成長過程およびその後の熱処理で、上記異種不純物によ
り形成したp−n接合にみられるようなp-n接合位置の
変動がなく、発光素子などに実用化されている。On the other hand, it is shown in GaAs that silicon (Si), which is a Group IV element, is an amphoteric impurity exhibiting p-type and n-type conductivity, and ambipolarity is also expected for germanium (Ge), which is a homologous group. ing. Especially, Si is GaAs by adding the same impurities.
It is possible to form a pn junction therein, and the pn junction position does not fluctuate as seen in the pn junction formed by the above different impurities during the crystal growth process and the subsequent heat treatment. Has been put into practical use.
上記の如く、同一不純物の添加によってp-n接合が形成
できれば、p-n接合の移動もなく良好な特性が得られる
ことから、AlxGa1-xAs(0<x<1)系においても、発光素
子、受光素子およびトランジスタなどで要望されている
が、液相成長法ではAlが含まれるAlGaAsでは、不純物Si
では実用キャリア濃度でのp形伝導性が得られていな
い。不純物Geではn形伝導性が得られていなかった。そ
の理由として狭い限定された成長条件であるためおよび
あまり丹念に調べられなかったためと考えられる。As described above, if a pn junction can be formed by adding the same impurities, good characteristics can be obtained without movement of the pn junction. Therefore, even in the Al x Ga 1-x As (0 <x <1) system, , Which is required for photo detectors and transistors, but in liquid phase epitaxy, AlGaAs containing Al contains impurities such as Si.
In, the p-type conductivity at the practical carrier concentration is not obtained. With the impurity Ge, n-type conductivity was not obtained. It is considered that the reason for this is that the growth conditions are narrow and limited and that it was not carefully examined.
不純物Geは、従来液相エピタキシャル成長法では、AlxG
a1-xAs(0<x<1)ではp形伝導性のみを示し、また分子線
エピタキシャル成長ではn形伝導性のみしか示さず、そ
れ故同一の成長法ではn形およびp形伝導性を同時に制
御することはできないとされていた。Impurity Ge is Al x G in the conventional liquid phase epitaxial growth method.
a 1-x As (0 <x <1) shows only p-type conductivity, and molecular beam epitaxial growth shows only n-type conductivity. Therefore, the same growth method shows n-type and p-type conductivity. It was said that they could not be controlled at the same time.
一方、前記2種の成長法を使用してもp-n接合界面の制
御がむずかしいためp-n接合はまだ得られていない。On the other hand, even if the above-mentioned two types of growth methods are used, it is difficult to control the pn junction interface, and thus a pn junction has not yet been obtained.
しかしながら、仮りに同一不純物Geによってp-n接合を
有するAlxGa1-xAs(0<x<1)系を得れば、上記したようにp
-n接合の変動は生ぜず、p-n接合界面での不純物濃度が
少なくなり、しかもGeは拡散係数が小さいため拡散のほ
とんどない良好な化合物半導体装置を得ることができる
ことが予想される。However, if an Al x Ga 1-x As (0 <x <1) system having a pn junction is formed by the same impurity Ge, as described above, p
It is expected that a good compound semiconductor device with almost no diffusion can be obtained because the impurity concentration at the pn junction interface decreases and the diffusion coefficient of Ge does not change.
したがって、本発明は同一不純物Geを使用してなるn
形AlxGa1-xAs(0<x<1)とp形AlyGa1-y
As(0<y<1)とのp−n接合を有する化合物半導
体の製造方法を提供せんとするものである。Therefore, in the present invention, the same impurity Ge is used.
Al x Ga 1-x As (0 <x <1) and p-type Al y Ga 1-y
It is intended to provide a method for producing a compound semiconductor having a pn junction with As (0 <y <1).
本発明者らは、従来p形AlGaAsを作るのに用いられてい
たGe不純物について注目し、該不純物について詳細なド
ーピング実験を行った結果、従来のAlGaAsの液相成長法
においても、結晶成長温度、Ga溶液中へのGeの添加量を
一定にして、Alの添加量すなわち成長するAlGa1-xAsの
x値を増加させていくと、成長するAlxGa1-xAsが或るx
値以上となるとp形からn形に変わることを見出した。The present inventors have paid attention to the Ge impurity that has been conventionally used to form p-type AlGaAs, and conducted a detailed doping experiment on the impurity. As a result, even in the conventional AlGaAs liquid phase growth method, the crystal growth temperature was increased. , and a constant amount of Ge to Ga solution and gradually increasing the amount or x value of the growing AlGa 1-x As of Al, growing Al x Ga 1-x As is certain x
It was found that the p-type changes to the n-type when the value exceeds the value.
したがって、本発明の化合物半導体装置の製造方法は、
基板と、該基板上に形成された不純物としてゲルマニウ
ム(Ge)を添加したn形伝導性を示すAlxGa1-xA
s(0<x<1)層およびp形伝導性を示すAlyGa
1-yAs(0<y<1)層(ここで、xとyとは0<y
<x<1の関係にある)のp−n接合少なくとも一つと
からなる化合物半導体装置の製造方法であって、 前記両層は、ゲルマニウムを不純物として含みアルミニ
ウム(Al)および砒素(As)を含有するガリウム
(Ga)溶液と接触させることにより、基板上に結晶層
を液相エピタキシャル成長させて形成されるものであ
り、かつ液相エピタキシャル成長させるにあたり、 AlyGa1-yAs層は、所定ゲルマニウム濃度において
アルミニウム量を増加させていった場合にキャリア濃度
の極小値を境にして、形成される結晶層がp形からn形
へと移り変わる液相エピタキシャル成長特性曲線におい
て、p形が形成される側の所定アルミニウム量を含むガ
リウム溶液と接触させて形成され、 AlxGa1-xAs層は、n形が形成される側の前記所定
アルミニウム量よりも多くのアルミニウム量を含むガリ
ウム溶液と接触させて形成されることを特徴とする。Therefore, the manufacturing method of the compound semiconductor device of the present invention is
Substrate and Al x Ga 1-x A having n-type conductivity formed by adding germanium (Ge) as an impurity formed on the substrate
s (0 <x <1) layer and Al y Ga exhibiting p-type conductivity
1-y As (0 <y <1) layer (where x and y are 0 <y
<X <1) and at least one pn junction, wherein both layers contain germanium as an impurity and contain aluminum (Al) and arsenic (As). Is formed by liquid phase epitaxial growth on a substrate by bringing the Al y Ga 1-y As layer into contact with a gallium (Ga) solution, and the Al y Ga 1-y As layer has a predetermined germanium concentration. In the liquid phase epitaxial growth characteristic curve in which the crystal layer to be formed changes from the p-type to the n-type with the minimum value of the carrier concentration as the boundary when the amount of aluminum is increased, The Al x Ga 1-x As layer formed by contacting with a gallium solution containing a predetermined amount of aluminum is in front of the side where the n-type is formed. It is characterized in that it is formed by contacting with a gallium solution containing an amount of aluminum larger than the predetermined amount of aluminum.
本発明の化合物半導体装置の製造方法において、GaA
s基板上に、該基板と同一伝導性を示すゲルマニウムを
不純物として添加した第1のAlxGa1-xAs(0<x
<1)層が形成され、該第1の層とは異なる伝導性を示
すゲルマニウムを不純物として添加した第2のAlyG
a1-yAs(0<y<1)層が前記第1の層上に形成さ
れ、前記GaAs基板およびAlyGa1-yAs層に電極
が形成される方法が好ましく、例えばこの方法によっ
て、ダイオードを製造することができる。In the method of manufacturing a compound semiconductor device of the present invention, GaA
On the s substrate, the first Al x Ga 1-x As (0 <x
<1) The second Al y G in which the layer is formed and germanium having a conductivity different from that of the first layer is added as an impurity
It is preferable that an a 1-y As (0 <y <1) layer is formed on the first layer, and an electrode is formed on the GaAs substrate and the Al y Ga 1-y As layer. , A diode can be manufactured.
また、本発明の化合物半導体装置の製造方法において、
GaAs基板上に、該基板と同一伝導性を示すゲルマニ
ウムを不純物として添加した第1のAlxGa1-xAs
(0<x<1)層が形成され、該第1の層とは異なる伝
導性を示すゲルマニウムを不純物として添加した第2の
AlyGa1-yAs(0<y<1)層が前記第1の層上に
形成され、前記第1の層と同じ伝導性を示すゲルマニウ
ムを不純物として添加した第3のAlzGa1-zAs(0
<z<1)層(ここで、yとzとは0<y<z<1の関
係にある)が前記第2の層上に形成され、かつ前記Ga
As基板、AlyGa1-yAs層およびAlzGa1-zAs
層に電極が形成される方法も好ましく、例えばこの方法
によって、トランジスタを製造することができる。Further, in the method for manufacturing a compound semiconductor device of the present invention,
On the GaAs substrate, the first Al x Ga 1-x As doped with germanium having the same conductivity as the substrate as an impurity.
And a second Al y Ga 1-y As (0 <y <1) layer doped with germanium having a conductivity different from that of the first layer is formed. A third Al z Ga 1 -z As (0) layer formed on the first layer and doped with germanium having the same conductivity as the first layer is added.
A <z <1) layer (where y and z have a relationship of 0 <y <z <1) is formed on the second layer, and
As substrate, Al y Ga 1-y As layer and Al z Ga 1-z As
A method in which an electrode is formed on a layer is also preferable, and a transistor can be manufactured by this method, for example.
以下、本発明をより具体的に説明する。Hereinafter, the present invention will be described more specifically.
従来の液相エピタキシャル成長法では、p形AlxGa1-xAs
をうるとき、所定量のGaAsとAlを含有するGa溶液(溶融
液)中にGalgにつきGeを約0.01g添加していた。本発明
者らは、このGeの添加量を従来よりも少くした条件、例
えばGalgにつき0.005gとか、0.002gとしたときについ
て、AlxGa1-xAsをGaAs基板上にAl組成を種々変化させて
800℃の飽和温度で液相成長させたところ、第1図に示
すように、Geの添加量が同一でもAl組成値xを増加させ
ると、すなわちGe溶液へのAlの添加量を増加させると、
結晶成長するAlxGa1-xAsが従来知られているp形から今
まで知られていなかったn形に変ることを見出した。具
体的に説明すると、まずAl0.3Ga0.7Asが成長可能な重量
のGaAsとAlおよびGalgにつき0.002gのGeをGa中に800℃
でとかしたGa溶液を作り、このGa溶液を例えば第2図に
示すようにp形GaAs基板1上に接触させて徐冷し、Ga溶
液を除去すると、該基板1上に第1のp形Al0.3Ga0.7As
層2(キャリア濃度=1017cm-3)が成長する。つづいて
Al0.65Ga0.35Asが成長するような重量のGaAsとAlおよび
Galgにつき0.002gのGeをGa中に800℃でとかしたGa溶液
を前記第1の層2上に接触させ徐冷し、Ga溶液を除去す
ると前記第1の層2上にn形Al0.65Ga0.35As層3(キャ
リア濃度=1017cm-3)が成長し、n形Al0.65Ga0.35As−
p形Al0.3Ga0.7Asのヘテロp-n接合を形成することがで
きる。こうして作られた本発明方法によるヘテロp-n接
合は断面をSEMにより観測すると、p-n接合の位置を
示す電子ビームにより誘起される起電力信号のピーク5
はヘテロ界面6と一致しており、第5図で説明したよう
な結晶成長中にヘテロ接合界面とp-n接合との分離がお
こっていないことがわかる(第2図参照)。In the conventional liquid phase epitaxial growth method, p-type Al x Ga 1-x As
At that time, about 0.01 g of Ge per Galg was added to a Ga solution (melt solution) containing a predetermined amount of GaAs and Al. The present inventors have made various changes in the Al composition of Al x Ga 1-x As on a GaAs substrate under the condition that the added amount of Ge is smaller than that of the conventional one, for example, 0.005 g per Galg or 0.002 g. Let me
When liquid phase growth was performed at a saturation temperature of 800 ° C., as shown in FIG. 1, when the Al composition value x was increased even when the Ge addition amount was the same, that is, when the Al addition amount to the Ge solution was increased. ,
It has been found that crystal-growing Al x Ga 1-x As changes from a conventionally known p-type to an n-type that has not been known until now. To be more specific, first, GaAs having a weight capable of growing Al 0.3 Ga 0.7 As and 0.002 g of Ge per Al and Galg are added in Ga at 800 ° C.
Then, the Ga solution is melted, and the Ga solution is brought into contact with the p-type GaAs substrate 1 as shown in FIG. Al 0.3 Ga 0.7 As
Layer 2 (carrier concentration = 10 17 cm −3 ) grows. Continued
Al 0.65 Ga 0.35 As grows so much GaAs and Al and
When 0.002 g of Ge per Galg was dissolved in Ga at 800 ° C., a Ga solution was brought into contact with the first layer 2 and slowly cooled. When the Ga solution was removed, n-type Al 0.65 Ga was formed on the first layer 2. 0.35 As layer 3 (carrier concentration = 10 17 cm −3 ) grows and n-type Al 0.65 Ga 0.35 As−
A hetero pn junction of p-type Al 0.3 Ga 0.7 As can be formed. When the cross-section of the hetero pn junction produced by the method of the present invention is observed by SEM, the peak 5 of the electromotive force signal induced by the electron beam indicating the position of the pn junction is obtained.
Indicates that the heterojunction interface 6 and the pn junction do not separate during crystal growth as described with reference to FIG. 5 (see FIG. 2).
上記のp-n反転のxの値は、不純物Geの添加量の減少に
より低下する。第1図に示すように、Geの添加量が0.00
2gのとき0.005gのときよりもAlAsのモル分率は小さ
い。また、p・n反転のxの値は、Ga溶液中のGe添加量
を一定としたとき飽和温度の上昇により減少することも
わかった。The value of x in the above pn inversion decreases due to the decrease in the added amount of the impurity Ge. As shown in FIG. 1, the added amount of Ge is 0.00
The molar fraction of AlAs at 2 g is smaller than that at 0.005 g. It was also found that the value of x in pn inversion decreases with the increase of the saturation temperature when the amount of Ge added in the Ga solution is constant.
以上述べたように、液相成長法での不純物としてGeを添
加したAlxGa1-xAsの成長特性から、Ga溶液中のGe添加量
およびAl添加量、さらにGa溶液の飽和温度(ほぼ成長温
度に等しい)の条件を選定することにより、同一不純物
Geを添加してn形およびp形AlxGa1-xAsを成長させるこ
とができる。第1図の結果からわかるように、Geの添加
量をn形層とp形層で変えることによりAlxGa1-xAsのホ
モp-n接合も可能である。As described above, from the growth characteristics of Al x Ga 1-x As added with Ge as an impurity in the liquid phase growth method, the amount of Ge added and the amount of Al added in the Ga solution, and the saturation temperature of the Ga solution (almost By selecting the conditions (equal to the growth temperature), the same impurity
Ge can be added to grow n-type and p-type Al x Ga 1-x As. As can be seen from the results of FIG. 1, a homo-pn junction of Al x Ga 1-x As is possible by changing the amount of Ge added between the n-type layer and the p-type layer.
以下、本発明を実施例により説明する。 Hereinafter, the present invention will be described with reference to examples.
実施例1 本発明方法により製造されたダイオードの例を第3図に
より説明する。Example 1 An example of a diode manufactured by the method of the present invention will be described with reference to FIG.
第3図に示すように、n形GaAs基板31上に不純物として
Geを添加したn形Al0.7Ga0.3As層32(電子濃度=3×10
17cm-3)を2μm程度の厚さに形成し、さらにその上に
不純物としてGeを添加したp形Al0.2Ga0.8As層33(ホー
ル濃度=1.5×107cm-1)を厚さ2μm程度形成し、基板
31およびp形Al0.2Ga0.8As層33に電極35を形成してなる
ヘテロp-n接合界面34をもつダイオードを作製した。こ
のダイオードは、ヘテロ接合界面とp-n接合界面が、第
2図に示したものと同様によく一致した高性能のヘテロ
接合ダイオードで、発光および受光素子として使用可能
である。As shown in FIG. 3, as impurities on the n-type GaAs substrate 31
Ge-added n-type Al 0.7 Ga 0.3 As layer 32 (electron concentration = 3 × 10
17 cm -3 ) is formed to a thickness of about 2 μm, and a p-type Al 0.2 Ga 0.8 As layer 33 (hole concentration = 1.5 × 10 7 cm −1 ) with a thickness of 2 μm is formed on top of it by adding Ge as an impurity. Forming the substrate
A diode having a hetero pn junction interface 34 formed by forming an electrode 35 on the 31 and p-type Al 0.2 Ga 0.8 As layer 33 was produced. This diode is a high-performance heterojunction diode in which the heterojunction interface and the pn junction interface match well as those shown in FIG. 2, and can be used as a light emitting element and a light receiving element.
このダイオードの製法は、従来のスライドボードによる
液相エピタキシャル成長法で、液相の仕込み条件を下記
表1に記載の如くし、800℃でまず表1のGaメルトNo.1
の組成のGa溶液をn形GaAs基板31上に接触させ、0.3℃
分の速さで徐冷したのちGaメルトNo.1液を除去するこ
とによってn形Al0.7Ga0.3As層32を成長させ、つづいて
797℃で表1のGaメルトNo.2液をn形Al0.7Ga0.3As層32
上に接触させて、前記と同じ速さで徐冷したのちGaメル
トNo.2液を除去することによって、p形Al0.2Ga0.8As
層33を成長させる。このようにして得た結晶に適当なオ
ーミック電極(Au電極)35をつけることによって第3図
に示したヘテロ接合ダイオードができる。The manufacturing method of this diode is a liquid phase epitaxial growth method using a conventional slide board, and the liquid phase preparation conditions are as shown in Table 1 below.
The Ga solution having the composition of is brought into contact with the n-type GaAs substrate 31 at 0.3 ° C.
The n-type Al 0.7 Ga 0.3 As layer 32 was grown by removing the Ga melt No. 1 liquid after slowly cooling at a speed of a minute, and then.
At 797 ° C, Ga melt No. 2 liquid in Table 1 was added to n-type Al 0.7 Ga 0.3 As layer 32
After contacting with the above and gradually cooling at the same rate as above, the Ga melt No. 2 liquid was removed to obtain p-type Al 0.2 Ga 0.8 As.
Grow layer 33. By attaching a suitable ohmic electrode (Au electrode) 35 to the crystal thus obtained, the heterojunction diode shown in FIG. 3 can be obtained.
実施例2 本発明方法により製造されたトランジスタの例を第4図
により説明する。 Example 2 An example of a transistor manufactured by the method of the present invention will be described with reference to FIG.
第4図に示すように、n形GaAs基板(電子濃度=1×10
18cm-3)41上に不純物を添加しないノンドープn形GaAs
層42(電子濃度=1×1016cm-3)を厚さ2μm程度に形
成し、このノンドープn形層42上にGeを不純物として添
加したp形Al0.2Ga0.8As層43(ホール濃度〜1018cm-3)
を0.2μm厚程度形成し、このp形層43上にさらにGeを
不純物として添加したn形Al0.4Ga0.6As層44(電子濃度
〜1017cm-3)を1μm厚程度形成し、n形層44に該層44
に対するオーミックコンタクトをとりやすくするためTe
をドープしたn形GaAs層45(電子濃度〜1018cm-3)を形
成し、そして層45,43,41の各層にオーミック電極46を形
成し、n形GaAs層42をコレクター、p形Al0.2Ga0.8As層
43をベース、n形Al0.4Ga0.6As層44をエミッター、n形
GaAs層45をオーミックコンタクト用補助層としたトラン
ジスタの例である。As shown in Fig. 4, n-type GaAs substrate (electron concentration = 1 x 10
18 cm -3 ) 41 Non-doped n-type GaAs with no added impurities
A layer 42 (electron concentration = 1 × 10 16 cm −3 ) having a thickness of about 2 μm is formed, and a p-type Al 0.2 Ga 0.8 As layer 43 (hole concentration ~ 10 18 cm -3 )
Is formed to a thickness of about 0.2 μm, and an n-type Al 0.4 Ga 0.6 As layer 44 (electron concentration ˜10 17 cm −3 ) doped with Ge as an impurity is further formed on this p-type layer 43 to a thickness of about 1 μm. Layer 44 to layer 44
Te to facilitate ohmic contact with
Forming an n-type GaAs layer 45 (electron concentration ˜10 18 cm −3 ), and forming an ohmic electrode 46 on each of the layers 45, 43 and 41, the n-type GaAs layer 42 being a collector and p-type Al. 0.2 Ga 0.8 As layer
43 base, n-type Al 0.4 Ga 0.6 As layer 44 emitter, n-type
This is an example of a transistor in which the GaAs layer 45 is used as an auxiliary layer for ohmic contact.
このトランジスタは、従来のスライドボートによる液相
エピタキシャル成長法にしたがって、そして各層を形成
するための液相の仕込み条件を表1のようにして結晶を
作製することによって得られる。各工程を詳記すると、
800℃でまず表1のGaメルトNo.3液をn形GaAs基板41に
接触させ0.3℃/分の速さで徐冷し、このGaメルトNo.3
液を除去してノンドープn形GaAs層42を成長させ、つづ
いて797℃でGaメルトNo.4液をノンドープn形GaAs層42
上に接触させ前記速さで徐冷しGaメルトNo.4液を除去
してGeドープp形Al0.2Ga0.8As層43を成長させ、つづい
て798℃でGaメルトNo.5液を前記Geドープp形層43上に
接触させ前記速さで徐冷し、GaメルトNo.5液を除去し
て、Geドープn形Al0.4Ga0.6As層44を成長させ、つづい
て796℃でGeメルトNo.6液をGeドープn形層44上に接触
させ前記速さで徐冷しGaメルトNo.6液を除去してTeド
ープn形GaAs層45を成長させることによって目的とする
結晶を得る。このようにして得られた結晶に適当なオー
ミック電極(Au合金)46をつけると第4図に示すヘテロ
接合トランジスタが形成できる。This transistor can be obtained by a conventional liquid phase epitaxial growth method using a slide boat, and by preparing a crystal under the liquid phase charging conditions for forming each layer as shown in Table 1. When describing each process in detail,
At 800 ° C., first, the Ga melt No. 3 liquid shown in Table 1 was brought into contact with the n-type GaAs substrate 41 and gradually cooled at a rate of 0.3 ° C./min.
The liquid is removed to grow the non-doped n-type GaAs layer 42, and then the Ga melt No. 4 liquid is added to the non-doped n-type GaAs layer 42 at 797 ° C.
It is contacted on the surface and slowly cooled at the above speed to remove the Ga melt No. 4 liquid to grow a Ge-doped p-type Al 0.2 Ga 0.8 As layer 43, and then at 798 ° C., the Ga melt No. 5 liquid is added to the Ge melt. It is brought into contact with the doped p-type layer 43 and gradually cooled at the above speed to remove the Ga melt No. 5 liquid, and grow a Ge-doped n-type Al 0.4 Ga 0.6 As layer 44, and subsequently at 796 ° C. The No. 6 solution is brought into contact with the Ge-doped n-type layer 44 and gradually cooled at the above speed to remove the Ga melt No. 6 solution and grow the Te-doped n-type GaAs layer 45 to obtain a target crystal. . By attaching an appropriate ohmic electrode (Au alloy) 46 to the crystal thus obtained, the heterojunction transistor shown in FIG. 4 can be formed.
トランジスタではベースの厚さが薄くなるほどp-n接合
位置の移動がトランジスタの性能に影響する。そのた
め、折角ベースの厚さを薄くしても、拡散などによりp-
n接合位置が移動すると、それにより高周波特性が劣化
する。本発明方法により製造されたトランジスタでは、
こうしたp-n接合位置の移動が結晶成長中またはその後
の熱処理中におこらないため、高周波特性が設計どおり
達成できる。In a transistor, the movement of the pn junction position affects the performance of the transistor as the base becomes thinner. Therefore, even if the thickness of the corner base is thin, p-
When the n-junction position is moved, the high frequency characteristic is deteriorated. In the transistor manufactured by the method of the present invention,
Since such movement of the pn junction position does not occur during crystal growth or subsequent heat treatment, high frequency characteristics can be achieved as designed.
本発明は前述の如き構成を有することにより、基板上に
結晶層を液相エピタキシャル成長させるにあたり、1種
類の不純物であるゲルマニウムが所定量添加されかつ所
定ゲルマニウム濃度においてアルミニウム量を増加させ
ていった場合にキャリア濃度の極小値を境にして、形成
される結晶層がp形からn形へと移り変わる液相エピタ
キシャル成長特性曲線において、p形が形成される側の
所定アルミニウム量を含むガリウム溶液と接触させてp
形層が形成され、又、n形が形成される側の前記所定ア
ルミニウム量よりも多くのアルミニウム量を含むガリウ
ム溶液と接触させてn形層が形成されるため、n形のAl
xGa1-xAsとp形のAlyGa1-yAsのヘテロ接合とp-n接合界
面が一致した設計どおりのヘテロp−n接合を有する化
合物半導体装置が得られる。それ故、本発明方法を用い
て製造した種々の化合物半導体装置は以下の如き特徴を
有する。すなわち、AlGaAs/GaAs,AlGaAs/AlGaAsなど
の組合わせでヘテロp−n接合を有する半導体レーザ、
発光ダイオード、受光素子およびトランジスタとして
も、結晶成長中および成長後の高温処理でもp-n接合位
置とヘテロ接合位置が変化しないため、高効率の少数キ
ャリア注入、高効率のキャリアとじ込めができ、発光素
子の場合では発光効率の高効率化、受光素子では暗電流
の低下、トランジスタでは高増巾率および高周波化をは
かることができるという効果を奏する。According to the present invention, when the crystal layer on the substrate is liquid-phase epitaxially grown, a predetermined amount of germanium, which is one kind of impurity, is added and the amount of aluminum is increased at a predetermined germanium concentration by having the structure as described above. In the liquid phase epitaxial growth characteristic curve in which the formed crystal layer changes from the p-type to the n-type with the minimum carrier concentration as the boundary, contact is made with a gallium solution containing a predetermined amount of aluminum on the side where the p-type is formed. P
Since the n-type layer is formed, and the n-type layer is formed by contacting with a gallium solution containing more aluminum than the predetermined amount of aluminum on the side where the n-type is formed, the n-type Al is formed.
A compound semiconductor device having a designed hetero pn junction in which the hetero junction of x Ga 1-x As and the p-type Al y Ga 1-y As and the pn junction interface coincide with each other can be obtained. Therefore, various compound semiconductor devices manufactured by using the method of the present invention have the following features. That is, a semiconductor laser having a hetero pn junction in a combination of AlGaAs / GaAs, AlGaAs / AlGaAs, etc.,
As a light emitting diode, a light receiving element, and a transistor, the pn junction position and the hetero junction position do not change even during high-temperature treatment during and after crystal growth, so high-efficiency minority carrier injection and high-efficiency carrier confinement can be performed. In this case, the luminous efficiency can be improved, the dark current can be reduced in the light-receiving element, and the transistor can be increased in width and higher in frequency.
第1図は、本発明方法における液相成長によるGeドープ
AlxGa1-xAsの特性を示すグラフ、 第2図は、本発明方法により製造された化合物半導体の
p−n接合の断面とSEM観察信号の関係を示すグラ
フ、 第3図は、本発明方法により製造されたダイオードの断
面模式図、 第4図は、本発明方法により製造されたトランジスタの
断面模式図、 第5図は、従来のAlGaAsのp−n接合を示す断面模式図
である。 図中 1…p形GaAs基板 2…p形AlGaAs層 3…n形AlGaAs層 4…電極 5…起電力信号のピーク 6…ヘテロ界面FIG. 1 shows Ge doping by liquid phase growth in the method of the present invention.
2 is a graph showing the characteristics of Al x Ga 1-x As, FIG. 2 is a graph showing the relationship between the cross section of the pn junction of the compound semiconductor manufactured by the method of the present invention and the SEM observation signal, and FIG. FIG. 4 is a schematic sectional view of a diode manufactured by the method of the present invention, FIG. 4 is a schematic sectional view of a transistor manufactured by the method of the present invention, and FIG. 5 is a schematic sectional view showing a pn junction of a conventional AlGaAs. . In the figure, 1 ... p-type GaAs substrate 2 ... p-type AlGaAs layer 3 ... n-type AlGaAs layer 4 ... electrode 5 ... electromotive force signal peak 6 ... hetero interface
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H01L 29/808 31/10 H01S 3/18 (56)参考文献 特開 昭56−129319(JP,A) 特公 昭49−25630(JP,B1) 特公 昭49−25629(JP,B1)─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification number Office reference number FI technical display location H01L 29/808 31/10 H01S 3/18 (56) References JP-A-56-129319 (JP, A) Japanese Patent Sho 49-25630 (JP, B1) Japanese Patent Sho 49-25629 (JP, B1)
Claims (3)
てゲルマニウム(Ge)を添加したn形伝導性を示すA
xGa1-xAs(0<x<1)層およびp形伝導性を示
すAyGa1-yAs(0<y<1)層(ここで、xとy
とは0<y<x<1の関係にある)のp−n接合少なく
とも一つとからなる化合物半導体装置の製造方法であっ
て、 前記両層は、ゲルマニウムを不純物として含みアルミニ
ウム(A)および砒素(As)を含有するガリウム
(Ga)溶液と接触させることにより、基板上に結晶層
を液相エピタキシャル成長させて形成されるものであ
り、かつ液相エピタキシャル成長させるにあたり、 AyGa1-yAs層は、所定ゲルマニウム濃度において
アルミニウム量を増加させていった場合にキャリア濃度
の極小値を境にして、形成される結晶層がp形からn形
へと移り変わる液相エピタキシャル成長特性曲線におい
て、p形が形成される側の所定アルミニウム量を含むガ
リウム溶液と接触させて形成され、 AxGa1-xAs層は、n形が形成される側の前記所定
アルミニウム量よりも多くのアルミニウム量を含むガリ
ウム溶液と接触させて形成されることを特徴とする化合
物半導体装置の製造方法。1. A substrate and n-type conductivity A formed by adding germanium (Ge) as an impurity formed on the substrate.
x Ga 1-x As (0 <x <1) layer and A y Ga 1-y As (0 <y <1) layer showing p-type conductivity (where x and y
Is in the relationship of 0 <y <x <1) and at least one pn junction of the compound semiconductor device, wherein both layers contain germanium as an impurity and aluminum (A) and arsenic. It is formed by liquid phase epitaxial growth of a crystal layer on a substrate by bringing it into contact with a gallium (Ga) solution containing (As), and in performing liquid phase epitaxial growth, an A y Ga 1-y As layer Is a liquid phase epitaxial growth characteristic curve in which the crystal layer formed changes from the p-type to the n-type at the minimum carrier concentration when the amount of aluminum is increased at a predetermined germanium concentration. The A x Ga 1-x As layer formed by contacting with a gallium solution containing a predetermined amount of aluminum on the side where the n-type is formed is formed. 2. The method for producing a compound semiconductor device, which is formed by contacting with a gallium solution containing an amount of aluminum larger than the predetermined amount of aluminum.
示すゲルマニウムを不純物として添加した第1のAx
Ga1-xAs(0<x<1)層が形成され、該第1の層
とは異なる伝導性を示すゲルマニウムを不純物として添
加した第2のAyGa1-yAs(0<y<1)層が前記
第1の層上に形成され、前記GaAs基板およびAy
Ga1-yAs層に電極が形成されることを特徴とする特
許請求の範囲第1項記載の化合物半導体装置の製造方
法。2. A first A x on which a germanium having the same conductivity as that of a GaAs substrate is added as an impurity.
A Ga 1-x As (0 <x <1) layer is formed and a second A y Ga 1-y As (0 <y <is added with germanium as an impurity having a conductivity different from that of the first layer. 1) a layer formed on the first layer, the GaAs substrate and A y
The method of manufacturing a compound semiconductor device according to claim 1, wherein an electrode is formed on the Ga 1-y As layer.
示すゲルマニウムを不純物として添加した第1のAx
Ga1-xAs(0<x<1)層が形成され、該第1の層
とは異なる伝導性を示すゲルマニウムを不純物として添
加した第2のAyGa1-yAs(0<y<1)層が前記
第1の層上に形成され、前記第1の層と同じ伝導性を示
すゲルマニウムを不純物として添加した第3のAzG
a1-zAs(0<z<1)層(ここで、yとzとは0<
y<z<1の関係にある)が前記第2の層上に形成さ
れ、かつ前記GaAs基板、AyGa1-yAs層および
AzGa1-zAs層に電極が形成されることを特徴とす
る特許請求の範囲第1項記載の化合物半導体装置の製造
方法。3. A first A x on a GaAs substrate doped with germanium having the same conductivity as the substrate as an impurity.
A Ga 1-x As (0 <x <1) layer is formed and a second A y Ga 1-y As (0 <y <is added with germanium as an impurity having a conductivity different from that of the first layer. 1) A third A z G layer formed on the first layer and doped with germanium having the same conductivity as the first layer.
a 1-z As (0 <z <1) layer (where y and z are 0 <
y <z <1) is formed on the second layer, and electrodes are formed on the GaAs substrate, the A y Ga 1-y As layer and the A z Ga 1-z As layer. A method of manufacturing a compound semiconductor device according to claim 1, wherein:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28156284A JPH0658976B2 (en) | 1984-12-29 | 1984-12-29 | Method for manufacturing compound semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28156284A JPH0658976B2 (en) | 1984-12-29 | 1984-12-29 | Method for manufacturing compound semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61159774A JPS61159774A (en) | 1986-07-19 |
| JPH0658976B2 true JPH0658976B2 (en) | 1994-08-03 |
Family
ID=17640913
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28156284A Expired - Lifetime JPH0658976B2 (en) | 1984-12-29 | 1984-12-29 | Method for manufacturing compound semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0658976B2 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5211485B2 (en) * | 1972-06-30 | 1977-03-31 | ||
| JPS4925630A (en) * | 1972-07-03 | 1974-03-07 |
-
1984
- 1984-12-29 JP JP28156284A patent/JPH0658976B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61159774A (en) | 1986-07-19 |
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