JPH0659100B2 - Noise elimination circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a noise elimination circuit that reduces or eliminates FM peak reception noise in a satellite television receiver.

(Prior Art) Conventionally, a noise elimination circuit for reducing or eliminating the peak noise in a satellite broadcast receiver has been proposed by the applicant of the present invention on May 10, 1985, for example, and the peak noise is the intermediate of the video signal. There is one that clamps to the value (gray level) so that it does not seem to be a noise.

However, just by clamping and graying out the noise part on the screen in this way, the effect of improvement is not so great.
When the H delay line (H is a horizontal scanning period) is used to rewrite the video signal of 1H before and the peak noise, when the video of 1H before is different from the video of the noise portion, it may have an adverse effect. In addition, if the video portion 1H before the replacement is also noise, the noise elimination effect cannot be obtained.

(Problems to be Solved by the Invention) The present invention eliminates the incompleteness of eliminating or mitigating the peak noise in the conventional satellite broadcast television receiver as described above, and has a relatively simple circuit configuration and almost completely eliminates it. The present invention aims to provide a noise eliminating circuit.

(Means for Solving the Problems) In order to achieve the above object, the present invention uses a one-field delay memory to replace noise with a video signal one field before. If there is noise even one field before, the signal 1H before the current one field is replaced. Still, when there is noise, it is solved by clamping the signal level to an intermediate value (gray on the screen) as in the past.

(Operation) According to the present invention as described above, most of the noise is replaced by the signal of one field before and a noise-free image is obtained, and some of the noise is replaced by the signal of 1H or earlier,
Therefore, most of the noise is removed and the screen becomes a beautiful image with good quality. The gray screen is 1H
The probability that both the preceding field and the preceding field are noise is extremely low and rarely occurs. That is, the present invention can be applied to a satellite television receiver to make a great contribution.

(Examples) Hereinafter, the present invention will be described in detail with reference to the drawings by examples. FIG. 1 is a configuration diagram of a main part of an embodiment of the present invention, FIG. 2 is an explanatory auxiliary view of a received image, FIG. 3 is a connection diagram of a satellite television broadcast receiver embodying the present invention, and FIG. The figure is a signal waveform diagram.

First, as shown in FIG. 3, the satellite broadcast television receiver of the present invention receives a weak, for example, 12 GHz super high frequency radio wave from a broadcast satellite (not shown) by the antenna 2 supported by the support 1, and then low noise. Converter (abbreviated as LNB)
According to 3, for example, 1 GHz band (here, 850 MHz to 1450)
It is converted to a high frequency of (MHz) and is guided to the second mixer 6 which constitutes the tuner of the satellite television receiver 5 via the coaxial cable 4 having a good high frequency characteristic. The pillar 1 is for rotating the antenna 2 to directly face the satellite when receiving from a plurality of broadcasting satellites, that is, satellites having different positions. Each of the devices 1 to 4 is installed outdoors. Therefore, the satellite TV receiver 5 is installed in the IDU (Indoor Un
called it).

Now, the 2nd mixer 6 converts the frequency of the television channel in the 1 GHz band input signal into an IF (intermediate frequency) frequency (for example, 402.75 MHz or 510 MHz).
Reference numeral 7 is an IF amplifier, and 8 is an FM (frequency modulation) wide-band detection circuit having a linearity characteristic of, for example, 30 MHz or more. Reference numeral 9 is a voice demodulation circuit which performs PCM demodulation in the case of PCM and FM detection in the case of FM. Reference numeral 10 is a noise removal circuit for removing the white and black peak noises of the present invention, which is no different from the conventional IDU if it is simply considered as an output buffer amplifier. Reference numeral 11 is an output buffer (amplifier) for outputting video and audio signals in the base frequency band, and 12 is an RF modulator, which converts the outputs of the audio demodulation circuit 9 and the noise removal circuit 10 into RF signals, and converts them into a normal VHF signal. The image is input to the television receiver 13 via the coaxial cable 14, and the image is received. Generally, the FM detection circuit 8
When the C / N (carrier-to-noise ratio) up to the output of is decreased, a screen with white peak and black peak noise appears as shown in FIG. 2 (a). At this time, when the noise removing circuit 10 of the present invention operates, noise is removed as shown in FIG.
It becomes a noisy image that changes to gray as shown in.

FIG. 1 shows the details of the noise elimination circuit of the present invention together with related peripheral circuits. The dotted box 10 is the noise elimination circuit of the present invention. This operation will be described with reference to the signal waveform of FIG.

In FIG. 1, 6 to 7, and 11 are the same as those in FIG. 3, and 15 is a pedestal clamp circuit that clamps the output of the FM detection circuit 8. The clamp pulse is output from the sync separation circuit 16 and the AFC A pulse for clamping the pedestal level other than the vertical signal period is formed by the clamp pulse generation circuit 17 using the applied horizontal pulse and vertical pulse, and as a result, as shown in FIG. Clamp the pedestal signal section. Reference numeral 18 denotes a peak noise detection circuit, where the pedestal level is equal to the black level V _B , the noise portion exceeding the white level V _W is detected as shown in FIG. 4 (a), and the pulse train of FIG. 4 (c) is obtained. In addition, noise that extends further below the black level V _B is detected, and FIG.
This is a circuit for obtaining the pulse train of (d). Such a circuit is disclosed in Japanese Patent Application No. 60-88006 filed on April 24, 1985 and May 1985.
Since it is the same as the patent application filed on the 10th, detailed description is omitted.

The pulse train shown in Fig. 4 (c) and (d) above is shown in Fig. 4.
The logical sum is obtained as shown in (e) and applied to the noise gate pulse generation circuit 19, where it is converted to the TTL level.
The output of this circuit replaces noise with a signal obtained by delaying the preceding signal. The present invention is characterized in that the 1H delay line 20 and the 1-field delay line 21 are combined with the delayed signal.

That is, the odd / even determination circuit outputs the pulse for determining the odd field and the even field by the output of the sync separation circuit 16.
22. The output of the 1-field delay line 21 is switched between output with a delay of 262 times the horizontal scanning period H and output with a delay of 263 times. The 1H delay line 20 is, for example, a 682-bit CCD analog memory. If the clock is clocked at 3 times the color sub-carrier, that is, 10.738635MHz (pulse width 93.12n sec), almost 1H becomes (about
63.556 μs). Fine adjustment can be done by changing the width of 1 bit once. Also, the 1-field delay line 21 has 263 1H delay lines connected in series and has output terminals at the 263rd and 262th delay lines. The output of the odd / even determination circuit 22 indicates that the field is an odd number. You can switch which output to use depending on whether it is an even number.

Now, a signal as shown in FIG. 4 (a) indicates the field f _m (m-th (m is an arbitrary positive integer) field. This is the same as the n-th) (n is an arbitrary positive integer). Of the horizontal scanning period (which is referred to as the _n- th H _-th line, and will be applied hereafter), the output of the 1-field delay line 21 becomes the _n- th H _-th field of the f _m-1 field. On the other hand, the output of the 1H delay line 20 is intended (n-1) th of the f _m field. The output of the nose gate pulse generation circuit 19 is applied to the AND gates 23, 24 and 25 when it is shown in FIG. on the other hand,
Clamp circuit 26 and 27 is the same configuration as the pedestal clamp circuit 15, the peak noise detection circuits 28 and 29 are the same as the peak noise detection circuit 18, if Figure 4 to the nH th f _m-1 field If there is even one noise pulse at the same position as (e), the output of AND gate 24 becomes high level only in that part, for example, Q in FIG. 4 (e), and AND gates 23, 30 can be conducted. Then, the output of the inverter 31 becomes low level and the AND gate 25 is cut off. At this time, if there is no noise at point Q in FIG. 4 (e) during the (n-1) H period, the output of the AND gate 23 is at a low level, and the output of the inverter 32 is at a high level. The AND gate 30 becomes conductive, and the output of the 1H delay line 20 is obtained as the Q portion of FIG. 4 (e), in other words, the (n-1) H component having the same phase as the output of the AND gate 30. If at this time the phase of point Q
If the (n-1) H signal has noise, the output of the AND gate 23 is at a high level, the output of the inverter 32 is at a low level, and the AND gate 30 is cut off. On the other hand, AND gate
The output of 23 is a clamp pulse generation circuit 33 and a NAND gate
It is applied to 34, and the video signal is clamped to an intermediate value (gray in the video) by the clamp circuit 35. At this time, the portion of the phase of Q in FIG. 4 (b) is clamped to the intermediate level V _m . Since the output of the inverter 32 is low level, the NAND gate 34 becomes high level and the output of the gray clamp circuit 35 becomes AN.
Output buffer passing through D gate 36 and OR gate 37
It is output to 11 (see also FIG. 3) and is output as a video signal from which noise has been removed.

If there is no noise in the same phase as in FIG. 4 (e) at nH of the f _m-1 field, only the pulse part in FIG. 4 (e) is ANDed.
As a matter of course, the output of the gate 25 is applied to the OR gate 37.

As described above, unless noise exists in the same phase during the same horizontal scanning period of the immediately preceding field, the noise portion is replaced with the signal of the field and is transmitted to the output buffer 11 as the output of the OR gate 37. Since the output of the NAND gate 34 becomes a low level in the peak noise part,
Field f _m-1 of the nH th signal AND instead of nH th signal field f _m AND gates 36 is blocked
It is transmitted to the OR gate 37 via the gate 25. If there is noise in phase with the nHth noise of the field f _{m at} the nHth field f _m-1 , only that portion is AND gate 30.
Is turned on, the AND gate 25 is turned off, and the field f _m is turned on.
Only the corresponding part of the (n-1) H signal in
Is output to the OR gate 37, and if (n-1) H
If there is noise in the same phase as the signal Q in FIG. 4 (e), the AND gates 25 and 30 are cut off, and the NAND gate 34
Output becomes high level and the AND gate 36 becomes conductive,
The nH signal of the field f _m clamped in gray is output to the output buffer 11, and that portion becomes gray, as indicated by p in the screen of FIG. 2 (b). However, such a situation is extremely rare in probability.

In order to perform the above operation completely, it is important to adjust the phase of the noise and the signal delayed by 1H or 1 field, or the phase adjustment of the AND gates 23, 24 and 36. And it can be absorbed by increasing the precision of the clock phase. Ie 1
If a 1-bit delay line is provided on the output side of the H delay line 20, the 1-field delay line 21 and the gray clamp circuit 35, and they are driven by the same clock, the 1H delay output, 1-field delay output, and the phase of the received signal match. It is easy to do. The timing adjusting circuits 38 and 39 are delay circuits for adjusting the phase difference between the output of the noise gate pulse generating circuit 19 and the output of the 1H delay line 20 and the 1-field delay line 21. Also, it goes without saying that the clock signal can be easily formed from the sync separation output and the color subcarrier.

As will be apparent from the detailed description above, in the present invention, noise is reduced by one horizontal period or one field period before noise.
Noise is eliminated by replacing it with a signal that does not have noise. Even if the signal one horizontal period before or one field period before is noise, it is a gray image to reduce noise. is there.

(Effect of the invention) Since the present invention replaces the signal of one field before, in most cases, noise can be eliminated, and even if the contents of the signal are different, it is when the screen is moving. Is inconspicuous. Further, even if there is noise of the same phase one field before, the probability of removing the noise is high because it is replaced with the signal of 1H before. Furthermore, even when none of the above replacements can be performed, the replacement is performed in gray, so that white or black peak noise can be made inconspicuous.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a main part of the present invention, FIG. 2 is a video diagram for assisting the explanation of FIG. 1, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. FIG. 15,26,27 …… Pedestal clamp circuit, 19 …… Noise gate generation circuit, 20 …… 1 horizontal scanning period (1H) delay line,
21 …… 1 field delay line, 22 …… odd / even discrimination circuit, 2
8,29 …… Peak noise detection circuit.

Claims (1)

[Claims] 1. A video signal reception processing device for an FM-modulated television signal, comprising: a first peak noise detection circuit for detecting a peak noise portion included in the video signal; and a field for delaying the video signal by one field. A delay circuit, a second peak noise detection circuit for detecting a peak noise portion included in the output signal of the one-field delay circuit, one horizontal scanning period delay circuit for delaying the video signal by one line, and one horizontal scanning The third peak noise detection circuit that detects the peak noise part included in the output signal of the period delay circuit, the clamp circuit that fixes the video signal to the intermediate value between the white peak and the black peak of the video signal, and the current reception The field is the mth field, and the peak noise is the first peak noise detection circuit during the nth horizontal scanning period. In the case of being detected by, the video signal of the nth horizontal scanning period of the (m-1) th field is taken out from the 1-field delay circuit, and the peak noise is detected by the second peak noise detection circuit. If not, a first gate circuit that replaces the video signal of the n-th horizontal scanning period of the m-th field with the output of the 1-field delay circuit; Noise is detected in the n-th horizontal scanning period of the field, and the output of the 1-field delay circuit from the second peak noise detection circuit is the n-th horizontal field of the (m-1) -th field. When peak noise is detected in the video signal in the scanning period, the video signal in the (n-1) th horizontal scanning period in the m-th field is set to the one water. If the peak noise is not detected by the third peak noise detection circuit when extracted from the flat scanning period delay circuit,
A second gate circuit that replaces the video signal of the nth horizontal scanning period of the mth field with the output of the one horizontal scanning period delay circuit; and the mth field from the first peak noise detection circuit. Noise is detected in the n-th horizontal scanning period of the above, and the n-th horizontal scanning of the (m-1) -th field of the output of the first field delay circuit from the second peak noise detection circuit is performed. Peak noise is detected during the period, and the peak is detected in the video signal of the (n-1) th horizontal scanning period of the mth field of the output of the first horizontal scanning period delay circuit from the third peak noise detection circuit. And a third gate circuit for replacing the video signal of the nth horizontal scanning period of the mth field with the output of the clamp circuit when noise is detected. A noise elimination circuit characterized by the above.