JPH0664126B2 - Semiconductor integrated circuit - Google Patents

Description

The present invention relates to a semiconductor integrated circuit that has a wafer test function and outputs data from an output buffer circuit during the wafer test. The present invention relates to a semiconductor integrated circuit designed to reduce noise generated in an output buffer circuit during a wafer test.

(Prior Art) ICs for semiconductor integrated circuits for memories, semiconductor integrated circuits for logic, etc.
As is well known, receives signals and data from the outside, internally performs processing such as arithmetic and logic, and outputs the processing result to the outside. For example, in a memory IC, an input signal is an address signal or a control signal, data stored at an address designated by an address is read, and read data is output as an output signal from a data output pin. Then, in the memory IC, it is necessary to drive a large load capacitance of, for example, about 100 pF by the output buffer circuit provided in the output stage. Therefore, an output buffer circuit with a relatively large current drive capacity is used. There is a need to.
The driving power of this output buffer circuit needs to be as great as that of an IC used in a field requiring high-speed operation. That is, the time required to drive the external load capacity is treated as part of the access time.

By the way, noise is one of the problems often encountered during actual use or testing of an IC. That is, the current flowing through the output buffer circuit in the IC is instantaneously changed to generate a counter electromotive force in the power supply wiring, which is mixed with the power supply to generate noise.

FIG. 7 is a schematic diagram of an IC mounted on a wiring board.
In the figure, a region surrounded by a broken line is an IC 70, which is composed of an internal circuit 71 to which an input voltage Vin is applied, a P-channel MOS transistor and an N-channel MOS transistor,
Output buffer circuit 72 driven by the output of this internal circuit 71
It consists of and. Further, V _cc and V _ss are the power supply voltage and the ground voltage supplied to the wiring board. The both voltages V _cc and V _ss supplied to the board are respectively passed through the inductance components L1 and L2, which are the sum of the inductances existing in the wiring on the board, the wiring inside the IC, the bonding wire inside the IC, etc. Supplied to IC70. On the other hand, between the ground voltage V _ss and the output node 73 of IC70 capacitance C1 due to the external load, the capacity C2 of the IC itself between the power supply voltage V _cc and the ground voltage V _ss is connected. The capacitance C1 due to the external load driven by the output buffer circuit 72 in the IC is a large value of about 100 pF as described above,
Power supply noise occurs when the output buffer circuit 72 drives this capacitor C1. That is, for example, IC70 in FIG. 7 above.
Is a memory IC, and when its input voltage Vin is one bit of an address consisting of a plurality of bits, the address is switched and the output data Dout from the output buffer circuit 72 is changed as shown in the timing chart of FIG. Consider the case where is switched from "1" level to "0" level. At this time, for example, "0" is read. The charge stored in the capacitor C1 in advance is discharged to the ground voltage V _ss by turning on the N-channel MOS transistor in the output buffer circuit 72.
As a result, the output data Dout changes from the "1" level to the "0" level. At this time, the current I _ss flowing through the wiring of the ground voltage V _ss changes as illustrated. At this time, due to the rate of temporal change of the ground current I _ss dI _ss / dt and the inductance component L2, the wiring of the ground voltage is L2 · dI _ss.
A back electromotive force of / dt is generated. That is, inside the IC,
Immediately after the N-channel MOS transistor in the output buffer circuit 72 is turned on, the ground voltage V _ss rises. After that, as the on-current of the transistor decreases, the ground voltage V _ss becomes negative, and when the on-current no longer flows, the original 0 V is applied. Return to and stabilize.

Conversely, the output data Do from the output buffer circuit 72
At the time of "1" reading when ut switches from "0" level to "1" level, the capacitance C1 is charged by turning on the P-channel MOS transistor in the output buffer circuit 72, and the output data Dout is at "0" level. Changes from "1" level. At this time, the current I _CC flowing through the wiring of the power supply voltage V _CC changes as shown. At this time as well, a counter electromotive force of L2 · dI _cc / dt is generated in the wiring of the power supply voltage due to the rate of temporal change of the current I _CC dI _cc / dt and the inductance component L2.
The power supply voltage _Vcc fluctuates as shown.

By operating the output buffer circuit 72 in this way,
The power supply voltage V _CC or the ground voltage V _ss inside the IC fluctuates. On the other hand, the input voltage Vin is the power supply voltage V on the board.
Regardless of the fluctuation of _CC or the ground voltage V _ss , it always keeps a constant value. That is, as shown in FIG. 7, the power supply voltage V _CC and the ground voltage V _ss of the IC (not shown) that generates the input voltage Vin are separated from the IC 70 on the board and are completely separated. This is because there is no interaction between them. Therefore, the power supply voltage V _{CC is generated} inside the IC on the board.
Alternatively, if the ground voltage V _ss fluctuates, the IC 70 on the board may malfunction. For example, as shown in the waveform diagram of FIG. 9, when the input voltage Vin is at a high level potential, I
Since the ground voltage V _ss fluctuates in C, the input voltage Vin
When the potential difference (Vin−V _ss ) between the input voltage Vin and the ground voltage V _ss becomes smaller than the threshold voltage V _IL on the low level side of the input stage transistor of the IC 70, the IC 70 detects the input voltage Vin at this time as the low level potential. Therefore, in this case, incorrect data is output and the IC malfunctions.

By the way, the following two methods can be considered in order to suppress the noise generated by the operation of the output buffer circuit as described above.

(A) The ratio dI / dt of the temporal change of the ground current I _ss or the power supply current I _CC is reduced.

(B) Reduce the inductance components L1 and L2.

Furthermore, the following two methods can be considered in order to reduce the former dI / dt.

(1) The rising or falling of the signal waveform supplied to the output buffer circuit is made smooth.

(2) The element size of the transistor forming the output buffer circuit is reduced to prevent a large current from flowing.

The method (1) corresponds to delaying the time when the transistor in the output buffer circuit is turned on at the time of switching the output data Dout, and the method (2) reduces the load driving capability of the output buffer circuit. This (1), (2)
Both methods aim to suppress noise by delaying the access time.

Decreasing dI / dt in (a) above is a measure taken by the IC manufacturer, while reducing the inductance component in (b) is a measure taken by the board designer. That is, the inductance component can be reduced by designing the wiring length on the board to the minimum. For ICs that operate at high speed, delaying the access time is not preferable, but rather it is common to design the output buffer circuit so that the load capacitance can be driven as quickly as possible and take noise countermeasures by optimizing the board. .

In order to obtain an IC capable of high-speed operation, it is necessary to design a board so that some noise will be generated in the output buffer circuit, and still no malfunction will occur.

The biggest problem at this time is the wafer test (Waf) including the Die Sort Test.
er Test) is the noise that occurs. This wafer test is performed using the test system having the configuration shown in FIG. The input data Din, the power supply voltage V _CC and the ground voltage V _ss from the tester 81 are supplied to the wafer-state IC 83 set in the prober 82, and the output data Dout from the IC 83 is sent to the tester 81. By the way, from tester 81 to prober 82
The distance to can be very long, for example 1 m or more. For this reason, the inductance component existing in each wiring between the two becomes significantly larger than that on the board. For low-speed and medium-speed ICs, noise is suppressed by taking the measures in (a) above.
Even during the test, there is almost no risk of malfunction due to this noise. However, in high-speed ICs designed under the assumption that sufficient noise countermeasures are taken on the board, this wafer
The generation of noise during the test becomes a problem. That is, the high-speed IC is designed to have a large dI / dt, and the fluctuations of the power supply voltage V _CC and the ground voltage V _ss supplied to the IC also become very large. For this reason, it may not be possible to satisfactorily perform measurement with a normal test system using a current tester or prober.

(Problems to be Solved by the Invention) As described above, the conventional semiconductor integrated circuit has a problem in that, when a normal test system is used, satisfactory measurement cannot be performed due to noise generated during a wafer test.

The present invention has been made in consideration of the above circumstances, and an object thereof is to obtain a sufficient operation speed in actual use and to suppress the generation of noise during a wafer test. An object of the present invention is to provide a semiconductor integrated circuit capable of satisfactory measurement even if the system is used.

[Structure of the Invention] (Means for Solving the Problems) A semiconductor integrated circuit according to the present invention includes a mode detection means for detecting a test mode, an output buffer circuit for outputting data to the outside, and the above output buffer circuit. Drive
A pre-buffer circuit is controlled so that the driving capability for the output buffer circuit is lowered in the test mode.

Further, the semiconductor integrated circuit of the present invention includes a mode detection means for detecting the test mode, an output buffer circuit controlled so that the driving capability for an external load is lowered in the test mode, and the output buffer circuit. And a pre-buffer circuit for driving.

Further, the semiconductor integrated circuit according to the present invention includes a mode detecting means for detecting the test mode, a data output buffer circuit which is controlled so that the driving capability for an external load is lowered in the test mode, and the output buffer circuit. And a pre-buffer circuit which is controlled so as to reduce the driving capability of the output buffer circuit in the driving mode and the test mode.

(Operation) In the semiconductor integrated circuit of the present invention, in the test mode, either one or both of the drive capability of the prebuffer circuit for the output buffer circuit and the drive capability of the output buffer circuit for the external load are reduced. By performing the control, the operation speed of the output buffer circuit is delayed to suppress the generation of noise.

(Examples) Hereinafter, the present invention will be described by examples with reference to the drawings. 1 is a circuit diagram showing a configuration of an output stage of a semiconductor integrated circuit (IC) according to a first embodiment of the present invention. In the figure, 10 is an output buffer circuit for generating output data Dout. The output buffer circuit 10 has a P-channel MOS transistor 12 whose source is connected to the application point of the power supply voltage V _{CC and} whose drain is connected to the output node 11 of the data Dout.
And an N-channel MOS transistor 13 whose drain is connected to the node 11 and whose source is connected to the application point of the ground voltage V _ss . Both transistors 12,
Internal data Dout1 ′ and Dout2 ′ are provided at the 13 gates, respectively.
Is supplied to the outputs of the pre-buffer circuits 20 and 30.

One of the pre-buffer circuits 20 has the internal data Dout1 ′
To invert the P-channel MOS in the output buffer circuit 10.
CMOS inverter circuit that supplies to the gate of transistor 12
21 and the internal data Dout1 ′ are supplied, and a wafer test signal WT and its inverted signal generated in a circuit described later are provided.
In accordance with ▼, the internal data Dout1 ′ is inverted and the P channel MOS transistor 1 in the output buffer circuit 10 is inverted.
It is composed of a CMOS inverter circuit 26 including two P-channel MOS transistors 22 and 23 and N-channel MOS transistors 24 and 25, which are supplied to the gates of the two. Further, the other pre-buffer circuit 30 is configured so that the internal data Dout
N'channel M in the output buffer circuit 10 by inverting 2 '
A CMOS inverter circuit 31 supplied to the gate of the OS transistor 13 and the internal data Dout2 ′ are supplied, and a wafer test signal WT and its inverted signal generated in a circuit described later are provided.
2 P-channel MOSs which operate in accordance with ▼ to invert the internal data Dout2 'and supply the inverted data to the gates of the N-channel MOS transistors 13 in the output buffer circuit 10.
Transistors 32 and 33 and N-channel MOS transistors 34 and 3
5 and a CMOS inverter circuit 36.

In the circuit of this embodiment, the transistors 12 and 13 in the output buffer circuit 10 drive the external load capacitance (not shown) connected to the node 11 at high speed, so that their conductances are set sufficiently large. In addition, in the above one prebuffer circuit 20, the CMOS inverter circuit
The conductance of each of the transistors 21 and 26 is set so that the driving capability for the gates of the P-channel MOS transistors 12 is, for example, 1: 9. Similarly, in the other pre-buffer circuit 30, the conductance of each transistor is set so that the driving capability of the CMOS inverter circuits 31 and 36 with respect to the gate of the N-channel MOS transistor 13 is, for example, 1: 9.

In the circuit configured as described above, the wafer test signal WT is at "0" level and its inverted signal ▲ ▼ is "1" during actual use.
Be leveled. Therefore, one of the pre-buffer circuits 20
Then, the CMOS inverter circuits 21 and 26 operate together, and the internal data Dout1 'is inverted by the two CMOS inverter circuits 21 and 26 and supplied to the gate of the P-channel MOS transistor 12 in the output buffer circuit 10. Similarly, in the other prebuffer circuit 30, the CMOS inverter circuits 31 and 36 operate together, and the internal data Dout2 ′ has two CMOS inverter circuits 3
N channel M in the output buffer circuit 10 after being inverted by 1 and 36
It is supplied to the gate of the OS transistor 13. Here, when one of the internal data Dout1 ′ is set to the “1” level, the output of the prebuffer circuit 20 is driven by the two CMOS inverter circuits 21 and 26, so that it is rapidly set to the “0” level. Becomes As a result, the P-channel MOS transistor 12 in the output buffer circuit 10 is rapidly turned on, and the output data Dout of the node 11 is rapidly raised to "1" level. On the contrary, when the other internal data Dout2 ′ is set to the “0” level, the output of the prebuffer circuit 30 is 2
Since it is driven by the individual CMOS inverter circuits 31 and 36, the level rapidly becomes "1". As a result, the N-channel MOS transistor 13 in the output buffer circuit 10 is rapidly turned on, and the output data Dout of the node 11 rapidly falls to "0" level. That is, a sufficient operation speed can be obtained during actual use.

Next, the operation when performing the wafer test will be described. During this wafer test, the wafer test signal WT is "1".
The level and its inverted signal ▲ ▼ WT are set to the “0” level. At this time, in the one pre-buffer circuit 20, only the CMOS inverter circuit 21 operates, and the internal data Dout1 ′ is transferred to this C
It is inverted only by the MOS inverter circuit 21 and supplied to the gate of the P-channel MOS transistor 12 in the output buffer circuit 10. Similarly, in the other pre-buffer circuit 30, only the CMOS inverter circuit 31 operates, and the internal data Dout1 ′ is inverted only by this CMOS inverter circuit 31 and supplied to the gate of the N-channel MOS transistor 13 in the output buffer circuit 10. It

Here, in the pre-buffer circuit 20, the driving capability of the two CMOS inverter circuits 21 and 26 is set to 1: 9, and also in the pre-buffer circuit 30, the driving capability of the two CMOS inverter circuits 31 and 36 is set to 1 pair. It is set to 9. Therefore, at the time of the wafer test, the gates of the P-channel MOS transistor 12 and the N-channel MOS transistor 13 in the output buffer circuit 10 are each driven with a driving capacity of 1/10 that in actual use. Therefore, the prebuffer circuit 2
The fall or rise time of the output signals of 0 and 30 increases ten times as much as in actual use.
P channel MOS transistor 12 or N channel M in
The time change rate dI / dt of the current flowing when the OS transistor 13 is turned on is sufficiently small. As a result, it is possible to suppress the noise generated due to the fluctuation of the power supply voltage V _CC or the ground voltage V _ss inside the IC, and it is possible to satisfactorily perform the measurement by the wafer test even if the normal test system is used. it can. In this wafer test, since the operation speed is lowered and the wafer is operated, the access time in the memory IC or the like cannot be measured. However, since the test items performed in the wafer test are mainly DC characteristics measurement and detection of the presence or absence of defective memory cells, there is no problem even if the operation speed of the IC itself is lowered and the measurement is performed.

FIG. 2 is a circuit diagram showing the configuration of the output stage of a semiconductor integrated circuit (IC) according to the second embodiment of the present invention. In the IC of this embodiment, two P-channel MOS transistors 14 and 15 and N-channel MOS transistors 16 and 17 are provided in the output buffer circuit 10, and one pre-buffer circuit 20 is provided.
The CMOS inverter circuit 21 and the CMOS type NAND gate circuit
27, and the other pre-buffer circuit 30 is composed of the CMOS inverter circuit 31 and the CMOS NOR gate circuit 37.

In the output buffer circuit 10, the sources of the two P-channel MOS transistors 14 and 15 are connected to the application point of the power supply voltage V _CC , and the drains thereof are connected to the output node 11 of the data Dout. Also, two N-channel MOS transistors 16 and 1
Each source of 7 is connected to the application point of the ground voltage V _ss , and each drain is connected to the output node 11 of the data Dout.
The output of the CMOS inverter circuit 21 in one pre-buffer circuit 10 is supplied to the gate of one P-channel MOS transistor 14 in the output buffer circuit 10, and the output of the CMOS inverter circuit 21 in one pre-buffer circuit 10 is supplied to the gate of the other P-channel MOS transistor 15. The output of the NAND gate circuit 27 in the pre-buffer circuit 10 is supplied. The NAND gate circuit 27 has internal data Dout1 'and a wafer test signal ▲ ▼ generated by a circuit described later.
Is supplied. The output of the CMOS inverter circuit 31 in the other pre-buffer circuit 30 is supplied to the gate of one N-channel MOS transistor 16 in the output buffer circuit 10, and the other gate is supplied to the gate of the other P-channel MOS transistor 17. The output of the NOR gate circuit 37 in the pre-buffer circuit 30 is supplied. The NOR gate circuit 37 is supplied with internal data Dout2 'and a wafer test signal WT generated by a circuit described later.

In the circuit of this embodiment, the conductances of the two P-channel MOS transistors 14 and 15 in the output buffer circuit 10 are equal to each other and the sum of them is one P-channel MOS transistor in the answer to the embodiment of FIG. It is set to be equal to that of 12 and two N-channel MOS transistors 1 in the output buffer circuit 10 are set.
The conductances of 6 and 17 are set to be equal to each other and the sum thereof is set to be equal to that of one N-channel MOS transistor 13 in the answer of the embodiment shown in FIG.

In the circuit configured as described above, the wafer test signal WT is at "0" level and its inverted signal ▲ ▼ is "1" during actual use.
Be leveled. Therefore, one of the pre-buffer circuits 20
Then, the NAND gate circuit 27 operates as an inverter circuit that inverts the internal data Dout1 ′, and the internal data Dout1 ′ is the CMO.
It is inverted by the S inverter circuit 21 and the NAND gate circuit 27 and supplied in parallel to the gates of the two P-channel MOS transistors 14 and 15 in the output buffer circuit 10. Similarly, in the other pre-buffer circuit 30, the NOR gate circuit 37 operates as an inverter circuit that inverts the internal data Dout2 ′,
The internal data Dout2 ′ is inverted by the CMOS inverter circuit 31 and the NOR gate circuit 37 to generate two N's in the output buffer circuit 10.
The gates of the channel MOS transistors 16 and 17 are supplied in parallel. Therefore, for example, when one of the internal data Dout1 ′ is set to the “1” level, the prebuffer circuit 20
The outputs of the CMOS inverter circuit 21 and the NAND gate circuit 27 in the inside both become "0" level, and the two P-channel MOS transistors 14 and 15 in the output buffer circuit 10 are both turned on.
Therefore, the output data Dout of the node 11 rapidly rises to the "1" level. Also, the other internal data Dout2 ′ is “0”
If it is set to the level,
The outputs of the CMOS inverter circuit 31 and the NOR gate circuit 37 are both at "1" level, and the two N in the output buffer circuit 10 are
Since both channel MOS transistors 16 and 17 are turned on,
The output data Dout of the node 11 rapidly rises to "0" level. That is, a sufficient operation speed can be obtained during actual use.

At the time of the wafer test, the wafer test signal WT is set to "1" level and its inverted signal is set to "0" level.
At this time, the output of the NAND gate circuit 27 is always at "1" level,
Since the output of NOR gate circuit 37 is always at "0" level,
P-channel MOS transistor 15 in the output buffer circuit 10
The N-channel MOS transistor 17 is turned off.
Therefore, the rate of change over time of the current flowing when the P-channel MOS transistor 14 or the N-channel MOS transistor 16 in the output buffer circuit 10 is turned on during the wafer test, dI / dt, becomes sufficiently small, and Power supply voltage V
It is possible to suppress noise generated due to fluctuations in _CC or the ground voltage V _ss .

FIG. 3 is a circuit diagram showing the configuration of the output stage of a semiconductor integrated circuit (IC) according to the third embodiment of the present invention. The IC of this embodiment is constructed by combining the circuits of both the embodiments shown in FIGS. 1 and 2.

FIG. 4 is a circuit diagram showing a configuration of a modified example of the embodiment circuit shown in FIG. In the embodiment of FIG. 1, the output buffer circuit
In order to change the driving ability for the gates of the P-channel MOS transistor 12 and the N-channel MOS transistor 13 in 10, the pre-buffer circuits 20 and 30 are connected to the CMOS inverter circuit 21,
31 and each of the CMOS inverter circuits 26 and 36 whose operations are controlled by the wafer test signal WT and ▲ ▼, respectively.In this modified circuit, the prebuffer circuit 20 is shown in the figure. It is configured in.
That is, the source of the depletion type MOS transistor 41 is between the application point of the power supply voltage V _CC and the output node 40,
The drain and the source and drain of the P-channel MOS transistor 42 are connected in series. Also, output node 40
The source of N-channel MOS transistor 43, and the drain, a depletion-type MOS transistor 44 source of drain are connected in series between the application point of the ground voltage V _ss and. The wafer test signal WT, which is set to the "0" level during the wafer test, is applied to the gates of the transistors 41 and 44.
Are supplied in parallel, and the internal data Dout1 'is supplied in parallel to the gates of the transistors 42 and 43.

In the pre-buffer circuit 20 having such a configuration, the on-resistances of the transistors 41 and 44 are sufficiently reduced by setting the wafer test signal ▲ ▼ to "1" level during actual use, and the inside of the output buffer circuit 10 P channel MO
The gate of the S transistor 12 is driven with a sufficiently large drive capacity. On the other hand, the ON resistance of the transistors 41 and 44 becomes larger than that in the actual use by setting the signal ▲ ▼ to "0" level during the wafer test, and the P channel MOS transistor 12 in the output buffer circuit 10 is The gate of is driven with a smaller drive capacity than in actual use. Although not shown, the other pre-buffer circuit 30
Also, the input data is only replaced by Dout2 ′, and the configuration is similar to this.

FIG. 5 is a diagram showing an example of a circuit for generating the wafer test signals ▼ and WT used in each of the circuits of the above embodiments. In the figure, 51 is a pad set to the "1" level in the wafer test mode. The pad 51 is normally set to the "0" level of the ground potential V _ss by the high resistance 52, and when the internal chip enable signal ▲ ▼ 'is set to the "0" level, the output of the NOR gate circuit 53 becomes "0". 1 "level, the output of the inverter circuit 54 that inverts its output, that is, the wafer test signal WT is" 1 "level, and the output of the inverter circuit 55 that inverts the output of this inverter circuit 54, that is, the signal ▲ ▼ is" 0 ". "It will be a level. On the other hand, in the wafer test mode, the pad 51 is set to "1" level, the signal WT is "0" level, and the signal ▲
▼ becomes “1” level.

FIG. 6 is a diagram showing another example of a circuit for generating the wafer test signal WT, ▲ ▼ used in each of the above-described embodiments. In the figure, 61 is a pad for supplying a normal control signal into the IC. At the time of wafer test, this pad 61
Is supplied with a signal having a level sufficiently higher than a normal control signal level, that is, V _ss and V _CC . Above pad
Two P-channels between 61 and the ground voltage V _ss application point
The sources and drains of the MOS transistors 62 and 63 and one N-channel MOS transistor 64 are connected in series,
One input end of the NAND gate circuit 65 is connected to the connection point of the transistors 63 and 64.

A predetermined bias voltage Vb is applied to the gate of the transistor 63.
Is being supplied. Then, during the wafer test, the internal chip enable signal ▲ ▼ 'is set to the "0" level, and the P-channel MOS is applied to the pad 61 more than the bias voltage Vb.
When a voltage higher than the threshold voltage of two transistors is supplied, the output of the NAND gate circuit 65 is at "0" level,
The output of the inverter circuit 66 that inverts its output, that is, the wafer test signal WT is at the "1" level, and the output of the inverter circuit 67 that inverts the output of this inverter circuit 66,
That is, the signal ▲ ▼ becomes "0" level.

It is needless to say that the present invention is not limited to the above embodiments and various modifications can be made. For example, a general pre-buffer circuit is generally controlled in operation based on an output enable signal that enables its output. Therefore, when controlling the operation of the pre-buffer circuits 20 and 30 based on the output enable signal in each of the circuits of the above-described embodiments, the inverter circuits 21 and 31 are connected to the internal data Dout1 ′ or Dout2 ′ and the output enable signal, respectively. It is necessary to replace with a NAND gate circuit and a NOR gate circuit that take logic, and the inverter circuit 26,
Even with 36, it is necessary to take logic with the output enable signal.

[Effects of the Invention] As described above, according to the present invention, a sufficient operation speed can be obtained in actual use, noise generation can be suppressed during a wafer test, and the measurement can be satisfied even if a normal test system is used. It is possible to provide a semiconductor integrated circuit which can be used for

[Brief description of drawings]

1 is a circuit diagram showing a configuration of an output stage of a semiconductor integrated circuit according to a first embodiment of the present invention, and FIG. 2 is a second diagram of the present invention.
FIG. 3 is a circuit diagram showing the configuration of the output stage of the semiconductor integrated circuit according to the embodiment of the present invention, FIG. 3 is a circuit diagram showing the configuration of the output stage of the semiconductor integrated circuit according to the third embodiment of the present invention, and FIG. First
FIG. 5 is a circuit diagram showing the configuration of a modification of the embodiment circuit shown in FIG. 5, FIG. 5 is a diagram showing an example of a circuit for generating a wafer test signal used in each of the above embodiments, and FIG. 6 is each of the above embodiments. FIG. 7 is a diagram showing another example of a circuit for generating a wafer test signal used in the circuit, FIG. 7 is a schematic diagram of an IC mounted on a wiring board, and FIG. 8 is a timing chart of the IC shown in FIG. ,
FIG. 9 is a waveform diagram showing changes in the ground voltage of the IC shown in FIG. 7, and FIG. 10 is a diagram showing the configuration of a test system for performing a wafer test. 10 ... Output buffer circuit, 12, 14, 15 ... P-channel MOS transistor, 13, 16, 17 ... N-channel MOS transistor, 20,
30 ... Pre-buffer circuit, 21, 26, 31, 36 ... CMOS inverter circuit, 27 ... CMOS NAND gate circuit, 37 ... CMOS NOR
Gate circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shinro Otsuka No. 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Inside the Toshiba Research Institute Co., Ltd. (72) Inventor Kenichi Imamiya Komukai-Toshiba, Kawasaki-shi, Kanagawa No. 1 Incorporated company Toshiba Research Institute

Claims (3)

[Claims] 1. In a semiconductor integrated circuit having a test mode, a mode detection means for detecting a test mode, an output buffer circuit for outputting data to the outside, and a drive circuit for driving the output buffer circuit. And a pre-buffer circuit which is controlled so as to reduce the driving capability of the output buffer circuit. 2. A semiconductor integrated circuit having a test mode, a mode detecting means for detecting that the test mode is set, an output buffer circuit controlled so that the driving capability for an external load is lowered in the test mode, And a pre-buffer circuit for driving the output buffer circuit. 3. A semiconductor integrated circuit having a test mode, mode detection means for detecting that the test mode is present, and an output buffer circuit which is controlled so that the driving capacity for an external load is lowered in the test mode. A semiconductor integrated circuit comprising: a pre-buffer circuit that drives the output buffer circuit and is controlled so that the driving capability of the output buffer circuit is lowered in the test mode.