JPH0664280B2 - Camera exposure controller - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a camera, and more particularly, to a camera provided with a command member for storing an exposure level, in which exposure control during shooting is performed at the exposure level stored by operating the member. is there.

2. Description of the Related Art A camera having a command member for storing an exposure level and performing exposure control at the time of photographing by an exposure element stored by operating the member is conventionally known.
Since the camera configured in this way employs the average photometry method, it is very convenient when the subject to be photographed with proper exposure is not in the center of the screen.

However, in this conventional camera, when shooting continuously, the first frame is shot with the stored exposure element and the second and subsequent frames are shot with the exposure level corrected for the stored exposure element. It had the drawback that it could not be done.

Therefore, an object of the present invention is to provide a camera capable of taking an exposure by adding a correction amount to a stored exposure element by inputting a correction signal, and solving the above-mentioned conventional problems. is there.

Hereinafter, the present invention will be described based on the illustrated embodiments.

1 and 2 are respectively a front view and a plan view of a camera showing one embodiment of the present invention. This camera 10 is a so-called single-lens reflex camera,
A taking lens barrel 2 is detachably attached to the center of the front surface of the camera body 1, and a pentaprism housing 3 is provided in the center of the upper surface so as to project in a triangular roof shape. As is well known, a taking lens 4 is housed and held in the taking lens barrel 2, and an outer peripheral portion of the taking lens barrel 2 has an aperture value setting ring 5, a taking distance from a front portion to a rear portion. A setting ring 6 and a manual shutter time setting ring 7 are sequentially arranged so as to be rotatable. Also, the camera body 1
On the upper left side, which is partitioned by the pentaprism housing 3, the film winding lever 8, the film frame number display window 9, the shutter release button 11, the self-timer command operation knob 12, the memory command operation knob 13 are provided. , Spot input button 1
4, a highlight command button 15 and a shadow command button 16 are provided respectively. On the other hand, on the right half of the upper surface of the camera body 1, a film rewind knob 17, a film sensitivity setting dial 18, a film sensitivity display window 19, a shooting mode switching operation knob 21, an exposure correction operation knob 22, and a battery check. Display light-emitting windows 23 are provided respectively. A strobe mounting shoe 24 is arranged near the rear end of the upper surface of the pentaprism housing 3, and a strobe (not shown) is arranged near the upper right end of the front surface of the camera body 1. Is provided with a connector 25 for connecting via a connection cord (not shown). In FIGS. 1 and 2, reference numeral 26 is an operation button for attaching the taking lens barrel 2 to the camera body 1, and 27 is a metal fitting for attaching a strap (not shown) to the camera body 1. , 28 are viewfinder eyepiece window frames, respectively.

The memory command operation knob 13 includes the shutter release button 1
It is arranged rotatably at the base of the pedestal No. 1, and Hirao is at the intermediate position between the "MEMORY" index and the "CLEAR" index on the top surface of the camera body 1 by the self-recovery training. The index indicated on the knob 13 is made to correspond and the knob 13 is stopped. The memory command operation knob 13 is an operation member for selecting and canceling a memory shooting mode (hereinafter, simply referred to as a memory mode) in which shooting is performed over a plurality of frames at an exposure level that is once stored. Therefore, it is designed to interlock with a memory switch SW ₆ (see FIG. 7) and a clear switch SW ₇ (see FIG. ₇ ) described later. When the memory command operation knob 13 is turned to match the index of the knob 13 with the "MEMORY" index, the memory switch SW ₆ is closed and the memory photographing mode is selected. The switch SW ₇ is closed to release the memory photographing mode. When the turning force is removed from the operation knob 13, the knob 13 automatically returns to the normal position by its own habit, but the memory photographing mode and the released state are retained. This point will be described later in detail in the description of FIG. 7.

The spot input button 14 is a self-reset type push button for inputting and storing the luminance value of the subject, which is partially metered through the photographing lens 4, into the electric circuit of the camera 10, and a spot input switch SW ₈ described later. (See FIG. 7). Engaging the spot input button 14, and closing spot input switch SW ₈ is, the spot shooting mode for controlling the exposure level based on the stored portion photometric value is selected at the same time, partial metering brightness values Will be remembered. When the spot input button 14 is pressed a plurality of times, the brightness value obtained by the partial photometry is stored each time, and the plurality of photometric values are stored in the camera 1.
It is designed to be held within 0. Note that the spot photography mode is not canceled by the self-return of the spot input button 14, and the cancellation of the photography mode is performed in connection with the completion of one photographing operation.

The highlight command button 15 is the spot input button 14
Using the maximum brightness value of the partial metering values stored by the operation as a reference, a highlight reference shooting mode (hereinafter, simply referred to as highlight mode) in which exposure is performed at an exposure value lower by 21/3 Ev is selected. It is a self-return type push button for operating, and is adapted to interlock with a highlight switch SW ₉ (see FIG. 7) described later. When the highlight command button 15 is pushed an odd number of times, the highlight mode is selected, and when it is pushed an even number of times, the highlight mode is canceled. In addition, the shadow command button 1
Reference numeral 6 denotes a shadow reference shooting mode (hereinafter, simply referred to as a shadow mode) in which exposure is performed by an exposure value higher by 2 2 / 3Ev than the lowest luminance value of the partial photometric values stored by operating the spot input button 14 as a reference. A self-returning push button for selecting a switch), which is linked to a shadow switch SW ₁₀ (see FIG. 7) described later. When the shadow command button 16 is pressed an odd number of times, the shadow mode is selected, and when it is pressed an even number of times, the shadow mode is released. If the partial photometry value is not stored when the highlight command button 15 and the shadow command button 16 are pressed,
Highlight mode and shadow mode are not selected. When the shadow command button 16 is pressed in the highlight mode, the highlight mode is released and the shadow mode is selected. When the highlight command button 15 is pressed in the shadow mode, , Shadow mode is canceled and highlight mode is selected.

The shooting mode switching operation knob 21 is rotatably arranged on the base of the base of the film rewind knob 17.
"MANUAL" written on the top surface of the camera body 1,
At the positions corresponding to the respective indexes of "OFF", "AUTO", and "CHECK", click stop is applied to each position to stop temporarily. And
The shooting mode switching operation knob 21 is linked to a manual switch SW ₃ (see FIG. 7), an auto switch SW ₄ (see FIG. 7) and a battery check switch SW ₅ (see FIG. 11). Therefore, when the operation knob 21 is made to correspond to the “MANUAL” index, the manual switch SW ₃ is closed, and a shutter (not shown) is operated at the manually set manual shutter time to control the exposure. Manual exposure shooting mode (hereinafter simply referred to as manual mode)
When it corresponds to the "FF" index, the off-shooting mode (hereinafter simply referred to as "off mode") in which the shutter is operated at a shutter speed that is constant in circuit is referred to as the "AUTO" index. When the SW ₄ is closed, the shutter speed is calculated from the photometric brightness value of the subject, and the exposure is controlled by operating the shutter at the shutter speed (hereinafter, simply referred to as auto mode). , When it corresponds to the "CHECK" index,
The battery check switch SW ₅ is closed, and the battery check state in which the power supply voltage Vcc is equal to or higher than the specified voltage is lit and displayed in the battery check display light-emitting window 23 is obtained.

FIG. 3 shows an optical system of a single-lens reflex camera arranged in the camera 10 of the present invention. As is well known, in the optical system of a single-lens reflex camera, a movable reflecting mirror 31 that is tilted by 45 ° with respect to the photographing optical path is rotatably disposed in the normal state, and at this finder optical path forming position,
The subject light that has entered the camera 10 through the taking lens 4 is reflected upward at a right angle and is made incident on the finder optical system. The finder optical system includes a focus glass 35 disposed at a position optically conjugate with the photosensitive surface of the photographic film 34, and the focus glass 35.
Of the condenser lens 36, a pentaprism 37 arranged directly above the condenser lens 36, and a finder arranged so as to face the rear end face of the pentaprism 37 which is the light emitting end face. An eyepiece lens 38 is provided, and a photographing information display device 39, which is a light-transmissive liquid crystal display plate, which will be described later, is provided at the rear edge of the focus glass 35 and the condenser lens 36. Has been done. In addition, the central portion of the movable reflection mirror 31 is subjected to half mirror processing or is provided with semitransparent slits in a row to form a semitransparent portion 31a.
A total reflection mirror 32 is movably attached to the back surface of the movable reflection mirror 31 corresponding to the semi-transmissive portion 31a so as to form a predetermined angle with the rotary reflection mirror 31. The total reflection mirror 32 serves to reflect the subject light that has passed through the semi-transmissive portion 31 a of the movable reflection mirror 31 toward the photometric light receiving device 41 arranged at the bottom of the camera 10. As shown in FIG. 4, the photometric light-receiving device 41 is formed in a rectangular shape, and is formed on the photosensitive surface of the photographic film 34 or the surface of the focal plane shutter 33 arranged at the rear portion of the camera body 1 and the total reflection. The camera body 1 is tilted toward the front end of the bottom of the camera body 1 so as to look up at the mirror 32. This photometric light receiving device 41
On the surface of the N-type semiconductor substrate 42, After forming the P-type semiconductor regions 43a and 43b having a rectangular shape and a rectangular shape, the cathode electrode 44 is formed on the N-type semiconductor substrate 42,
Anode electrodes 45a, on the P-type semiconductor regions 43a, 43b,
Area 45b
a and the substrate 42 are photovoltaic elements PD for average direct photometry of subject light reflected on the photosensitive surface of the photographic film 34 or the surface of the focal plane shutter 33.
₁ (see FIG. 8) and also the region 43b and the substrate 4
Reference numeral ₂ forms a photoelectric conversion element PD ₂ (see FIG. 8) that performs spot memory photometry on the subject light reflected by the total reflection mirror 32.

FIG. 5 is a block diagram showing an outline of a configuration of an electric circuit in the camera 10 of the present invention. This electric circuit is a microcomputer (hereinafter abbreviated as CPU) 50 as a central processing unit for controlling the entire circuit, and a head amplifier circuit for photometrically measuring a subject light and outputting a photometric integrated output S2 and a brightness value signal S6. 51, and a trigger timing adjusting circuit 52 for outputting the trigger signal S1 to control the photometry start timing of the head amplifier circuit 51, and for inputting analog exposure information such as aperture value, film sensitivity value, and correction value to the circuit. A first comparison circuit that compares the analog exposure information introducing circuit 53, the photometric integrated output S2 from the head amplifier circuit 51, and the output from the analog exposure information introducing circuit 53 to output a shutter control signal 17 during direct photometry. 54
And a shutter control signal S17 for direct photometry from the first comparison circuit 54 and a shutter control signal S16 for memory mode, manual mode, or spot mode output from the CPU 50. 1 selection circuit 55, a magnet drive circuit 56 controlled by a shutter control signal output from the first selection circuit 55, a luminance value signal S6 from the head amplifier circuit 51, and an analog exposure information introduction circuit 53. From the CPU 50 and the second selection circuit 57 that selectively outputs one of the (film sensitivity value-aperture value) signal (SV-AV) based on the input selection signal S7 from the CPU 50. D-A conversion circuit 58 for D-A converting 8-bit digital information, and this D-A conversion circuit 58
From the analog signal output from the second selection circuit 57.
A second comparison circuit 59 for comparing the A / D converted analog signal S8 output from the CPU 50 as digital information and inputting the manual shutter speed and the correction value as digital exposure information into the CPU 50. Of the digital exposure information introduction circuit 60 and the photographing information display device 39 driven by receiving the output from the CPU 50.
And, the main part is composed. In addition to this,
A strobe determination circuit 62 for displaying the completion of charging of the strobe, a battery check circuit 63 for determining whether or not the power supply voltage Vcc is equal to or higher than a specified voltage, a power hold release circuit 64 for canceling self-holding of the power supply, and a strobe. A strobe over / under determination circuit 65 for determining whether the light exposure is over or under, and a strobe control circuit 66 for generating a strobe automatic light control signal are respectively provided. Further, a power supply hold circuit 67 for holding power supply to the entire circuit, a timer circuit 68 for generating various time signals, and a reference voltage circuit 69 for generating various reference voltages are respectively provided.

FIG. 6 is a block diagram showing an internal configuration of the CPU 50 which is the center of the control system in the camera 10 of the present invention. In the figure, a block generator (CLOCK) 7
Reference numeral 1 is a portion that generates a pulse that serves as a reference for the operation of the CPU 50. The control circuit (CONT) 72 is a CPU 50.
Is the central part that controls the overall operation of the. CPU
The 50 needs to transfer data into various binary numbers in order according to the determined program order. For that purpose, when, how long the gate in the CPU 50 should be opened, and It is necessary to have a portion inside the CPU 50 that determines which flip-flop should be set or reset depending on the state of the CPU 50 and the input state. CONT72 does this job. The instruction register (INR) 73 is a part that temporarily holds the contents of a random access memory (RAM) 84 described later, and the CONT 72 uses the contents of the INR 73 as a CP.
Determine the state of each part of U50. The program counter (PC) 76 is a part that stores the address to be executed in order to execute the program in order, and the program counter (PC) 76 is increased in order of execution from the smallest memory location to the largest memory location. go. The stack pointer (SP) 77 is used by the PC 7 when an interrupt instruction is generated or a jump instruction to a subroutine is generated.
6, To retain the contents of the accumulator (ACC) 79, which will be described later, and the index register (IX) 78, which will also be described later, without destroying the contents, when the user wants to return from those instructions and use them again. Is a register of. IX
Reference numeral 78 is a register for storing an instruction execution address when the instruction is executed in the index address format. The arithmetic processing circuit (ALU) 81 is a part that performs operations related to operations in the execution of instructions, performs addition and subtraction, and executes an inversion instruction that inverts the memory contents "1" or "0"). Or, a logical operation for obtaining a logical sum or a logical product of two memories is performed. The condition code register (CCR) 82 is a register for storing a code used for state detection in a flag when executing an instruction that requires judgment such as a branch instruction.
The determination function occupies an important position for the CPU 50, and in the control of the camera 10 of the present invention as well, as will be described later, the state of each input port is determined to be "1" or "0") and then executed. Often, a branch instruction is executed at a place where the flow of the program to be changed is changed or the instruction is executed without changing the flow. This is CCR8
This is done by determining the state of the flag in 2. The CCR 82 results in 2 when the instruction is executed.
Negative flag that becomes "1" when it becomes negative in the complement of, "0" when it becomes positive, becomes "1" when the result is "0", and becomes "0" when it is not "0" Zero flag, "1" when the result causes a two's complement overflow, "0" otherwise, an operation result, "1" when a carry or borrow occurs from an unsigned binary number ', It is composed of various flags such as a carry flag which becomes "0" when it does not occur. The memory buffer register (MBR) 75 is a storage address register (SA
This is a register for reading the contents of the instructed address when the memory is instructed to read at the stage where the address to be read is entered in (R) 74.

The read-on memory (ROM) 83 is for causing the CPU 50 to execute instructions while sequentially reading the contents. In addition, a random access memory (RAM) 8
Reference numeral 4 denotes a memory for temporarily storing a value in the middle of calculation processing and its result, or various input information. The display random access memory (DRAM) 85 has an area corresponding to each segment of the liquid crystal display panel forming the photographing information display device 39, which will be described later in detail with reference to FIG. When the content of a specific address of the DRAM 85 becomes "1", the segment of the liquid crystal display panel corresponding to the content is colored. As described above, the liquid crystal drive circuit (LCDD) 61 is a circuit for driving the color of the photographic information display device 39 formed of a liquid crystal display plate. Due to the 1/3 duty and 1/3 bias drive control method, 39 segment lines and 3 common lines are drawn. Input port (I
NPP) 88 is 17 input ports I0 to I16 as described later, and output port (OUTPP) 89 is 10 output ports O0 to O9 as described later.
Each is formed (see FIG. 7). In addition, OUT
The outputs of PP89 are all latch outputs.

Next, the control flow of the CPU 50 configured as above will be briefly described.

The CPU 50 repeats two cycles: a fetch cycle for loading an instruction stored in an address in the memory designated by the PC 76 and an execut cycle for executing the instruction next. Then, first, the value of the PC 76 is transferred to the SAR 74. At the same time, the PC 76 stores the content that has been stored in the PC 76 until now, plus one. If the memory is instructed to read at the stage where the address to be read is contained in the SAR 74, the contents of the address specified to the MBR 75 will be read after a while. The instruction code portion thereof is transferred to the INR 73. This is a fetch cycle. Following this, the execut cycle is entered, but this operation differs depending on the contents of INR 73. As an example, it is assumed that the INR 73 now contains an instruction (LDA instruction) for loading the memory contents into the ACC 79. The address portion of the instruction remaining in the MBR75 is transferred to the SAR74, then the memory is instructed to read, and after a while, the data obtained in the MBR75 is ACC.
Transfer to 79 to end instruction. As another example,
It shows how conditional branch instructions that frequently appear in the flowcharts described later are executed. Now, when it is desired to determine the state of a port having an input port (A port) and perform a conditional branch, the contents of the A port are read to the MBR 75 in the fetch cycle, as in the case of the above example. The A port bits are assumed to be in the most significant bits of memory. Now, assuming that the LDA instruction for storing the memory contents in the ACC 79 is contained in the INR 73, the contents of the A port are ACC as in the case of the above example.
Transferred to 79. Then, the PC 76 indicates the address to be executed next, and the instruction is executed in the MBR in the same manner.
Stored in 75. Now, assuming that an instruction (ROL instruction) for shifting the most significant bit of the ACC 79 to the carry flag of the CCR 82 is contained in the INR 73, in the next execut cycle, the carry flag indicates the state of the A port ('0' or? "1") is stored. Next, similarly, determine the state of the carry flag, and if the carry flag is '1', branch, and otherwise execute the next program execution instruction (BCS instruction). Can be achieved. In the latter example LDA, ROL and B
Although three CS commands are used, desired control can be performed by arbitrarily combining dozens of kinds of commands in this way.

In the flow chart described later, how to specifically use each block shown in FIG. 6 to execute the program is not shown at the machine language level, but the transfer instruction in the program is not shown. The addition, subtraction, etc. can be easily realized by known methods.

FIG. 7 shows an interface around the CPU 50. In this figure, reference numerals I0 to I16 indicate input ports of the CPU 50, and reference numerals O0 to O9 indicate output ports. The input port I0 is for detecting whether or not the mode is the auto mode, and is connected to one end of an auto switch SW ₄ that interlocks with the shooting mode switching operation knob 21 and also has a pull-down resistor R ₁ Is grounded through. At the other end of the auto switch SW ₄ ,
The power supply voltage Vcc is applied. Therefore, input port I
0 becomes “L” level and takes “0” when the O-switch SW ₄ is opened, and takes “H” level and takes “1” when it is closed. And when it becomes '1',
Indicates that auto mode has been detected. One end of the auto switch SW ₄ is also connected to a first input end of a NOR circuit G ₄ described later via the knot circuit G ₁ . The input ports I1 is for detecting whether the manual mode, with are connected to one end of the manual switch SW ₃ interlocked with the photographing mode switching operation knob 21, a pull-down resistor It is grounded through R ₂ . The other end of the manual switch SW _3, the power supply voltage Vcc is applied. Accordingly, the input port I1 is manual switch SW ₃ is turned 'L' level in a state of open '0', and the becomes 'H' level in the closed state takes a '1'. Then, when it becomes “1”, it indicates that the manual mode is detected.

Input port I6 is for detecting whether the memory mode, and is connected to the output terminal of the NAND circuit G _3. The output terminal of the NAND circuit G _{3 is connected to} the NAND circuit G _3.
5 is also connected to one input terminal of the NAND circuit G ₅ , the output terminal of the NAND circuit G ₅ is connected to the other input terminal of the NAND circuit G ₃ , and both circuits G ₃ and G ₅ are RS flip-flops for memory mode detection. It comprises a circuit. One input end of the NAND circuit G _{3 that} is the reset input end of the RS flip-flop circuit is connected to the output end of the NAND circuit G ₂ , and the other input end of the NAND circuit G ₅ that is the set input end is , The NOR circuit G ₄ is connected to the output terminal. The output terminal of the NOR circuit G ₄ is also connected to the other input terminal of the NAND circuit G ₂ . One input end of the NAND circuit G ₂ is connected to the memory command operation knob 13 by a memory switch SW.
It is connected to one end of ₆ and is grounded through a resistor R ₃ . The memory switch SW ₆ a self-returning type switch, the power supply voltage Vcc is applied to the other end. The second input terminal of the NOR circuit G _4, being adapted to strobe the power-on signal S14 is applied, the third
The memory timer signal T7 is applied to the input end of the. The fourth input terminal is connected to one end of a clear switch SW ₇ described later. The NOR circuit G ₄ is a gate for resetting, and the input port I 0
Is '0', that is, not in the auto mode, when the flash is attached to the camera 10, the power of the flash is turned on, the memory timer is expired, and the clear signal is manually input. There is a gate for canceling the memory mode. Also,
The NAND circuit G ₂ is a gate for resetting the RS flip-flop circuit by the output of the NOR circuit G ₄ prior to the memory mode selection signal.

Input port I2 is for detecting whether the spot mode, which is connected to the output terminal of the NAND circuit G _9, when the output terminal becomes the "H" level '1 'Indicates that it is in spot mode. The NAND circuit G ₉ constitutes an RS flip-flop circuit together with the NAND circuit G ₇ as in the case of the NAND circuits G ₃ and G ₅ . A NAND circuit G _{7 which} is a set input terminal of the RS flip-flop circuit for spot mode detection
One of the input terminals is connected to the output terminal of the NOR circuit G ₆ , and the other input terminal of the NAND circuit G _{9 serving as} the reset input terminal is connected to the output terminal of the NAND circuit G ₈ . The output end of the NOR circuit G ₆ is also connected to one input end of the NAND circuit G ₈ . It is also connected to one input end of the NOR circuit G ₆ . One input terminal of the NOR circuit G ₆ is connected to the output port O0 for spot mode release, the other input terminal, the memory command operation knob 13
It is connected to one end of a self-reset type clear switch SW ₇ interlocked with and is grounded through a resistor R ₄ . The power supply voltage Vcc is applied to the other end of the clear switch SW ₇ . The NOR circuit G ₆ is a gate for resetting, so that the spot mode is released when the clear switch SW ₇ is pressed or when a pulse signal is output to O0 by software by a program. There is. The other input terminal of the NAND circuit G ₈ is connected to one end of the spot input switch SW _8, the NAND circuit G ₈ are RS flip-flop with priority to the spot input signal at the output of the NOR circuit G ₆ It acts as a gate for resetting the circuit.

Input port I3 is for detecting the presence or absence of spot input is connected to the output terminal of the NAND circuit G _11, a '1' when the output becomes "H" level Indicates that there is spot input. NAND circuit G
₁₁ is a NAND circuit G ₁₂ together with the NAND circuits G ₃ and G
Similar to the case of ₅ , the RS flip-flop circuit is configured. One input terminal of the NAND circuit G _{11 which} is the reset input terminal of the RS flip-flop circuit for spot input detection is connected to the output terminal of the knot circuit G ₁₀ .
The other input end of the NAND circuit G ₁₂ , which is the set input end, is
It is connected to the output terminal of the knot circuit ₁₃ . The input end of the knot circuit G ₁₀ is connected to one end of a self-reset type spot input switch SW ₈ via a capacitor C ₃ and is also grounded via a resistor R ₆ . Also, NP
It is also connected to the collector of N-type transistor Q ₇₀ ,
The emitter of the transistor Q ₇₀ is grounded. Furthermore, the base of the transistor Q ₇₀ is connected to the output port O1 for spot input cancellation through the resistor R ₁₁ , and this output port O1 is also connected to the input end of the knot circuit G ₁₃ . Also, one end of the spot input switch SW ₈ has a NAND circuit G ₈ as described above.
Together are connected to the other input terminal, the resistor R ₅ is grounded through, and the power supply voltage Vcc is applied to the other end of the switch SW _8. The RS flip-flop circuit composed of the NAND circuit G ₁₁ and the NAND circuit G ₁₂ is in the spot mode state, and the spot input switch SW ₈ is closed each time the spot input switch SW ₈ is closed to input the spot photometry operation signal a plurality of times. It is for holding signals. When the spot metering operation signal is input and the calculation of the shutter speed is completed inside the CPU 50, a positive pulse signal is output to the output port O1 to set the RS flip-flop circuit and wait for the spot metering operation signal to be input again. It becomes a state.

The input port I4 is for highlight mode detection,
Is connected to the output terminal of the NAND circuit G _15, becomes "1" when the output becomes 'H' level, indicating that the highlighting mode.

The self-reset type switch SW ₉ is a command switch for highlight reference shooting, and when the switch SW ₉ is closed, the output of the RS flip-flop circuit composed of the NAND circuits G ₁₅ and G ₁₆ is output. It becomes the “H” level and the highlight mode is selected. The release of the highlight mode is performed by outputting a positive pulse to the output port O ₂ . On the other hand, the input port I5 is for detecting a shadow mode, is connected to the output end of the NAND circuit G ₁₉ , and is "1" when the output end becomes the "H" level.
Indicates that the shadow mode is set. Further, the self-reset type switch SW ₁₀ is a command switch for shadow reference photographing, and when the switch SW ₁₀ is closed, the output of the RS flip-flop circuit composed of the NAND circuits G ₁₉ and G ₂₁ becomes'. The level becomes H ', and the shadow mode is selected. This shadow mode is released by the output port O
₃ by outputting a positive pulse. A switch SW ₉ , resistors R ₇ , R ₈ , R ₁₂ , a capacitor C ₄ , an NPN transistor Q ₇₁ , a knot circuit G ₁₄ ,
A highlight mode detection circuit including G ₁₇ and NAND circuits G ₁₅ and G ₁₆ , a switch SW ₁₀ , a resistor R ₉ ,
R ₁₀ , R ₁₃ , capacitor C ₅ , NPN type transistor Q
₇₂ , knot circuit G ₁₈ , G ₂₀ and NAND circuit G ₁₉ , G ₂₁
Connection mode Shadow mode detection circuit comprising the said switch SW _8, the resistor _{R 5, R 6, R 11} , capacitors _C 3,
The spot photometry operation signal input detection circuit is composed of an NPN transistor Q ₇₀ , knot circuits G ₁₀ and G ₁₃ and NAND circuits G ₁₁ and G ₁₂ , and its detailed description is omitted here.

Next, operations of the spot photometry operation signal input detection circuit, the highlight mode detection circuit, and the shadow mode detection circuit will be described by taking the spot photometry operation signal input detection circuit as an example. Incidentally, when the spot input switch SW ₈ is closed, a short pulse signal with 'H' level to an input terminal of the NOT circuit G ₁₀ is generated through the capacitor C _3. Then,
The output of the RS flip-flop circuit consisting of NAND circuits G _11, G ₁₂ become 'H' level, serves as an input port I3 is '1', CPU 50 detects that the spot metering operation is performed, the predetermined time t Output port O
A pulsed reset signal of'H 'level is output to 1 to reset the RS flip-flop circuit. Here, if the time constants of the capacitor C ₃ and the resistor R ₁₀ are longer than the predetermined time t, even if a reset signal is output,
The RS flip-flop circuit is set again,
The CPU 50 may mistakenly recognize that the spot metering operation signal has been input again. Therefore, the transistor Q ₇₀ is connected in parallel with the resistor R ₆ and the transistor Q ₇₀ is turned on by the reset signal to forcibly fully charge the capacitor C ₃ .

The output port O4 is a port that outputs the photometric mode command signal S3. When the signal S3 is "1", the average photometric mode is selected in the head amplifier circuit 51 (see FIG. 8) described later, and "0" is selected. ', The spot metering mode is selected. The output port O5 is a port for outputting the input selection signal S7,
When the signal S7 is "1", the luminance value signal S6 is not received by the second selection circuit 57 (see FIG. 9) described later.
When it is output as the -D converted analog signal S8 and is "0", the analog operation value signal (SV-AV) of the film sensitivity value and the aperture value is output as the A / D converted analog signal S8. ing. The output port O6 is an output port for determining the sign of each bit of the D-A conversion circuit (DAC) 58, and is composed of parallel 8 bits. The input port I7 is a port for inputting A / D converted digital information, and together with the D / A conversion circuit 58, a second comparison circuit 59 forming a successive approximation type A / D conversion circuit. Is connected to the output terminal of the comparator A ₁₂ . The inverting input terminal of the comparator A ₁₂ is connected to the output terminal of the DA converting circuit 58, and the AD converted analog signal S8 is applied to the non-inverting input terminal.

The output port O7 is a common output end of the liquid crystal drive circuit 61, is formed by three lines, and is connected to the liquid crystal display plate (LCD) of the photographing information display device 39. The output port O8 is a segment output end of the liquid crystal drive circuit 61, is formed by 39 lines, and is connected to the liquid crystal display panel (LCD) of the photographing information display device 39. The input port I8 is a port for manual shutter time input, and has four input lines. Further, the input port I9 is a port for inputting the correction value, and has four input lines. Both the input ports I8 and I9 are connected to the digital exposure information introduction circuit 60. The input port I10 is an input port for detecting a release signal, and the release signal S0 is applied to it. The input port I11 is
Input port for trigger signal detection, knot circuit G
_The trigger signal S1 is applied through ₁₀₀ . Further, the input port I12 is an input port for detecting the exposure end signal, and the exposure end signal S13 is applied thereto. Furthermore, the input port I13 is an input port for detecting a strobe power-on signal, and a strobe power-on signal S14 is applied. The input port I14 is a strobe photographing over signal detection input port for detecting whether or not overexposure has occurred in strobe photographing, and the strobe photographing over signal S9 is applied thereto. The input port I15 is
The strobe photographing under signal detection input port for detecting whether the exposure is underexposed in strobe photographing is applied with the strobe photographing under signal S10. Output port O9 is in memory mode,
This is a port for outputting the shutter control signal S16 in the manual mode and the spot mode. Further, the input port I16 is a port for inputting a strobe light emission proper signal S20 for performing proper display for about 2 seconds after strobe light emission when the exposure is proper in strobe photography.

FIG. 8 shows a detailed electric circuit of the head amplifier circuit 51. The head amplifier circuit 51 is basically composed of a circuit for generating brightness information in open average photometry and brightness information in open spot photometry, an integrating circuit in direct photometry, and an analog switch. The operational amplifier A ₁ is a bipolar transistor input operational amplifier, the reference voltage V ₀ is applied to the non-inverting input terminal, and the inverting input terminal is connected to the output terminal of the operational amplifier A ₂ . The operational amplifier A ₁ can suppress the input offset voltage to within 1 mV without adjusting the offset. The output terminal of the operational amplifier A ₁ is connected to the emitter of the PNP type transistor Q ₁ , and the transistor Q ₁
Is connected to the output terminal of the operational amplifier A ₂ through the resistor R ₁₆ and also has a logarithmic compression transistor Q.
₂ collector and base. The logarithmic compression transistor Q ₂ is a multi-emitter PNP transistor, one emitter of which is the anode of the average photometric photovoltaic element PD ₁ and the other of which is the anode of the spot photometric photovoltaic element PD ₂ . , Each connected. The base and collector of the transistor Q ₂ are also connected to the non-inverting input terminal of the operational amplifier A ₃ . The cathode of the photovoltaic element PD _1, PD ₂ is connected to the inverting input terminal of the operational amplifier A _2, an anode is connected to one of the non-inverting input terminal and the other of the inverting input terminal of the operational amplifier A ₂ . The operational amplifier A ₂ is a MOS transistor input operational amplifier and has two non-inverting input terminals. Depending on whether the photometric mode command signal S3 applied to the control signal input terminal is at the “H” level or the “L” level, The valid non-inverting input terminal can be switched. That is, when the photometry mode command signal S3 is at the'H 'level, the other non-inverting input terminal becomes effective, and the photovoltaic element P
Zero bias is maintained between the anode and cathode of D ₁ ,
The potential between the base and collector of the transistor Q ₂ changes according to the amount of light received by the photovoltaic element PD ₁ . Further, when the photometry mode command signal S3 is at the'L 'level, one non-inverting input terminal becomes effective, the zero bias is maintained between the anode and the cathode of the photovoltaic element PD ₂ , and the base of the transistor Q ₂ The potential between the collectors changes according to the amount of light received by the photovoltaic element PD ₂ . A resistor R ₁₇ is connected to the bias switching signal input terminal of the operational amplifier A _2.
Bias switching signal S4 is optionally adapted to be applied through, this signal S4 is 'H' level in the direct photometry, the operational amplifier A ₂ bias current of the operational amplifier A ₂ is increased becomes capable of high-speed operation, the signal When S4 becomes the “L” level during the memory photometry, the bias current of the operational amplifier A ₂ is reduced and the power consumption is saved.

The capacitors C ₁ and C ₂ are integration capacitors at the time of direct photometry, and _one ends of the capacitors C ₁ and C ₂ are connected to the anode of the photovoltaic element PD ₁ for average photometry. In addition, the other end of the capacitor C ₁ is erected,
The other end of the capacitor C ₂ is connected to the collector of the NPN type transistor Q ₆ . Transistor Q ₆ is a transistor of the integrating capacitor switching, the emitter is grounded, the base integral capacitance switching signal S5 is adapted to be applied through the resistor R _19. The collector of the transistor Q ₆ is connected to the operational amplifier A through the resistor R _18.
It is also connected to the output terminal of ₂ . The integral capacitance switching signal S5 is a signal that is switched according to the film sensitivity,
The signal is output from the output terminal Q of the latch circuit DF ₀ (see FIG. 9). Direct metering is the metering integration output S2 of the integrating circuit.
The exposure is terminated when (the output of the operational amplifier A ₂ ) reaches a predetermined voltage level according to the film sensitivity. The judgment voltage is several mV if the film sensitivity is high.
, Which makes it more susceptible to noise such as static electricity. Therefore, in this circuit, when the high film speed, by turning off the transistors Q ₆ and the integral capacitance switching signal S5 is 'L' level, to reduce the capacitance of the integrating capacitor as a capacitance of only the capacitor C _1, the reverse The judgment level of the integrated voltage is increased. Further, when a low film speed, turning the transistor Q ₆ and the integral capacitance switching signal S5 is 'H' level, the capacitance of the integrating capacitor by the parallel capacitance of the capacitor C _1, C _2, determination of the integrated voltage Widening the dynamic range by lowering the level. The collector of the transistor Q ₆ is a resistor R
_The connection to the output terminal of the operational amplifier A ₂ through ₁₈ is to make the capacitance of the capacitor C ₂ substantially zero when the transistor Q ₆ is off.

The operational amplifier A ₃ is a buffer operational amplifier, the output end of which is connected to the inverting input end of the same amplifier A ₃ and also to the collector of a PNP transistor Q ₇ . The base of the transistor Q ₇ is connected to the non-inverting input terminal of the operational amplifier A ₃ , and the emitter is the second
Operational amplifier A ₉ forming the selection circuit 57 (see FIG. 9)
It is connected to one of the non-inverting input terminals and to one end of the constant current circuit CC ₁ . Constant current circuit CC ₁
The power supply voltage Vcc is applied to the other end of the constant current I ₀ , and a constant current I ₀ flows in the same current circuit CC ₁ . A voltage proportional to the absolute temperature of the logarithmic compression value of the photocurrent generated in the photovoltaic element PD ₁ or PD ₂ appears at the emitter of the transistor Q ₇ , and this voltage is derived as the brightness value signal S6. Has become.

The base of the transistor Q ₁ is connected to the collector of the NPN type transistor Q ₅ . Transistor Q ₅
A power supply voltage Vcc is applied to the base of the transistor through a resistor R ₁₄ , and the emitter of the transistor Q ₅ is grounded. A diode-connected NPN transistor Q is connected between the base and emitter of the transistor Q _5.
4 and the NPN transistor Q ₃ are connected to each other. The base of the transistor Q ₃ is connected to the output terminal of the knot circuit G ₁₀₁ (see FIG. 12) through the resistor R ₁₅ , and receives the trigger signal S1 from the circuit G ₁₀₁ .

Next, the operation of the head amplifier circuit 51 thus configured will be briefly described. Assuming that the trigger signal S1 was 'L' level, the transistor Q ₃ is turned off, the transistor Q ₅ is turned on, the transistor Q ₁ is turned on. Thus, the output of the operational amplifier A ₁ is now fed back to the inverting input terminal of the operational amplifier A ₁ via the transistor Q _1, Q ₂ and an operational amplifier A _2,
A negative feedback circuit is formed. Therefore, the output voltage of the operational amplifier A ₂ becomes equal to the reference voltage V ₀ . Here, the emitter of the transistor Q ₇ has a photovoltaic element PD ₁ or P
A voltage corresponding to the received light amount of D ₂ is generated. At the time of direct photometry, the trigger signal S ₁ becomes'H 'with the start of exposure.
Turning to the level, the transistor Q ₃ turns on, the transistor Q ₅ turns off, the transistor Q ₁ turns off, the negative feedback circuit whose main body is formed by the operational amplifiers A ₁ and A ₂ is cut off, and the base of the transistor Q ₂ is cut off. -The collector potential is the same as the output of the operational amplifier A ₂ . Therefore, the charges of the capacitors C ₁ and C ₂ start charging according to the photocurrent generated in the photovoltaic element PD ₁ . At this time, the transistor Q ₂
The voltage between the emitter and the base of the transistor is only the offset voltage of the operational amplifier A ₂ , and the leak current between the base and the emitter of the transistor Q ₂ and between the emitter and the collector is very small. Since the operational amplifier A ₂ is a MOS transistor input operational amplifier, the capacitor C ₁ ,
The charging current of C ₂ is almost exclusively due to the photocurrent, and the long exposure time can be created with high accuracy.
Then, the capacitors C ₁ and C ₂ continue to be charged, and the integrated output S2 of direct photometry is output to the output terminal of the operational amplifier A ₂ . When the voltage of the integrated output S2 becomes higher than the collector potential of the transistor Q ₂₀ (see FIG. 9), the output of the operational amplifier A ₈ (see FIG. 10) is inverted,
The exposure ends.

FIG. 9 shows a detailed electric circuit diagram of the analog exposure information introduction circuit 53 and the second selection circuit 57. The non-inverting input of the operational amplifier A ₄ and the reference voltage V ₀ is applied to the inverting input terminal of the operational amplifier A _4, through the correction value input variable resistor RV _0, proportional to the absolute temperature by the constant current circuit CC ₂ The current I ₁ is flowing. Between the output terminal and the inverting input terminal of the operational amplifier A _4, a variable resistor RV ₁ for film sensitivity input, a semi-fixed resistor RV ₂ for exposure level adjustment of direct photometry, a semi-fixed resistor RV ₃ for display level adjustment and A series circuit of variable resistors RV ₄ for inputting aperture information is connected. Therefore, a voltage corresponding to the analog operation value (SV-AV) of the difference between the film sensitivity value Sv and the aperture value Av appears at the output terminal of the operational amplifier A ₄ , and this operational amplifier forms the second selection circuit 57. It is adapted to be applied to the other non-inverting input terminal of A ₉ . The non-inverting input terminal of the operational amplifier A ₉ is connected to the brightness value signal S6.
Is applied from the emitter of the transistor Q ₇ (see FIG. 8). The output terminal of the operational amplifier A ₉ is connected to the inverting input terminal of the amplifier A ₉ and also the comparator A ₁₂
It is connected to the non-inverting input terminal (see FIG. 7). The input selection signal S7 is applied to the control signal input terminal of the operational amplifier A _{9 from} the output port O ₅ (see FIG. 7). When the signal S7 is at the'H level, one of the non-inverted inputs The end becomes effective, and the output end of the operational amplifier A ₉
When the luminance value signal S6 is output as the A / D-converted analog signal S8 and the signal S7 is at the “L” level, the other non-inverting input terminal is enabled and the calculated value is output to the output terminal of the operational amplifier A _9. The voltage corresponding to (SV-AV) is output as the A / D converted analog signal S8.

The operational amplifier A ₅ and the transistor group in the subsequent stage generate a judgment voltage of the integration circuit output S2 during direct photometry, or generate a signal for switching the capacitances of the integration capacitors C ₁ and C ₂ according to the film sensitivity. It is provided to do so. The non-inverting input terminal of the operational amplifier A ₅ is connected to the connection point of the resistors R ₃₀ and R ₃₁ where the reference voltage V ₀ is divided by the resistors R ₃₀ and R ₃₁ . The reference voltage V ₀ is applied to the inverting input terminal of the operational amplifier A ₅ through the resistor R ₃₂ . An NPN transistor Q ₁₀ is provided between the output terminal and the inverting input terminal of the operational amplifier A _5.
, The emitter is connected to the output terminal and the collector is connected to the non-inverting input terminal, and the base of the transistor Q ₁₀ is connected to the correction value input variable resistor RV ₀ and the constant current circuit CC _2. It is connected. The output terminal of the operational amplifier A ₅ is also connected to the emitter of the NPN transistor Q ₁₁ , and the base of the transistor Q ₁₁ is connected to the connection point of the semi-fixed resistors RV ₂ and RV ₃ . The collector of the transistor Q ₁₁ is a PNP transistor Q
It is connected to the collector of _{13 and} the base of the PNP type transistor Q ₁₂ , respectively. The power supply voltage Vcc is applied to the emitter of the transistor Q ₁₃ and the base of the transistor Q ₁₃ is PNP.
Type transistor Q ₁₄ is connected to the base of
It is also connected to the emitter of transistor Q ₁₂ . The collector of the transistor Q ₁₂ is grounded. A power supply voltage Vcc is applied to the emitter of the transistor Q ₁₄ , and the collector thereof is connected to the collector and base of the NPN transistor Q ₂₂ . The transistors Q ₁₃ and Q ₁₄ form a current mirror circuit for causing a current equal to the current flowing through the collector of the transistor Q ₁₁ to flow through the collector of the transistor Q ₂₂ . Transistor Q
₂₂ has its emitter grounded, has its base connected to the collector of an NPN transistor Q ₈₁ , and has n N transistors.
The transistors are connected to the bases of the respective transistors of the PN type transistor group Q ₈₀ . The emitter of each transistor of the transistor group Q ₈₀ is grounded, the collector is connected to the collector of the PNP type transistor Q ₁₅ , and the base of the PNP type transistor Q ₁₆ . The transistor Q ₂₂ and each of the transistors of the transistor group Q ₈₀ form a current mirror circuit, and a current n times as large as the current flowing through the collector of the transistor Q ₂₂ flows in the collector of the transistor Q _15. ing. The emitter of the transistor Q ₈₁ is grounded, and the base is connected to the output terminal Q of the latch circuit DF ₀ through the resistor R ₃₃ . When the integration capacitance switching signal S5 output from the latch circuit DF ₀ is at the “H” level,
The transistor Q ₈₁ turns on, the transistor Q ₂₂ and the transistor group Q ₈₀ turn off, and the collector current of the transistor Q ₁₅ becomes zero.

The transistor Q ₁₅ has a power supply voltage Vcc applied to its emitter, has its base connected to the bases of the PNP type transistors Q ₁₇ and Q ₁₈ , and is also connected to the emitter of the PNP type transistor Q ₁₆ . The collector of the transistor Q ₁₆ is grounded. Transistor Q
_The power supply voltage Vcc is applied to the emitter ₁₇ , the collector is connected to the collector of the PNP type transistor Q ₂₀ , and the comparator ₁₇ is connected to the non-inverting input terminal of the comparator A ₈ (see FIG. 10). Further, the transistor Q ₁₈ has a power supply voltage Vcc applied to the emitter, a collector connected to the collector of the PNP transistor Q ₁₉ , and a non-inverting input terminal of the comparator A ₇ (see FIG. 10). . Transistor Q ₁₅ and transistors Q ₁₇ and Q ₁₈
Is a current mirror circuit, and the same current as the collector current of the transistor Q ₁₅ flows through the collectors of the transistors Q ₁₇ and Q ₁₈ . Transistor Q above
₁₉ and Q ₂₀ have a power supply voltage Vcc applied to their emitters,
A reference voltage V ₀ is applied to the collector through resistors R ₃₄ and R ₃₅ . And transistors Q ₁₉ and Q ₂₀
Is connected respectively to the base to the base of the transistor Q _13, respectively with the transistor Q ₁₃ constitute a current mirror circuit. Therefore, the same current as the collector current of the transistor Q ₁₃ flows through the collectors of the transistors Q ₁₉ and Q ₂₀ . The base of the transistor Q ₁₃ is also connected to the base of a PNP type transistor Q ₂₁ , and the transistor Q ₂₁ has its emitter applied with the power supply voltage Vcc and its collector connected to the integration capacitors C ₁ and C 2. Semi-fixed resistor RV for adjusting the switching point of the capacitance of _2
Grounded through ₅ . And the transistor Q ₂₁
Is connected to the non-inverting input terminal of the comparator A ₆ . The inverting input terminal of the comparator A ₆ is connected to the connection point between the resistors R ₃₆ and R ₃₇ that divides the reference voltage V ₀ , and the output terminal is connected to the input terminal D of the latch circuit DF ₀ . The comparator A ₆ plays a role of determining whether or not to switch the integral capacitance according to the film sensitivity.
The control signal input terminal of the latch circuit DF _0, a release signal S0 from the collector of the transistor Q ₃₂ (see FIG. 11) is not adapted to be applied, the latch circuit DF ₀
Serves to hold the integral capacitance switching signal S5 output from the output terminal Q so as not to be inverted at the time of shutter release. The resistance value of the resistor R ₃₄ is the same as that of the resistor R _35.
The resistance value is set to ▲ √ ▼ times.

Next, the operation of the analog exposure information introducing circuit 53 thus configured will be briefly described. At the output terminal of the operational amplifier A ₄ , the resistors RV _{1 to} RV ₄ are used with the reference voltage V ₀ as a reference.
A voltage is generated by adding a voltage drop of a value obtained by multiplying the series resistance value of ₁ by a constant current I ₁ proportional to the absolute temperature. The voltage equivalent to the change in aperture or film speed per step is
It is about 18 mV at constant temperature. Therefore, the output of the operational amplifier A ₄ is not affected by the voltage drop due to the correction value input variable resistor RV ₀ . The base potential of the transistor Q ₁₀ is lower than the reference voltage V ₀ by the voltage drop of the resistor RV ₀ . On the other hand, the base potential of the transistor Q ₁₁ becomes higher than the reference voltage V ₀ by the voltage drop of the series resistance of the variable resistor RV ₁ for film sensitivity input and the semi-fixed resistor RV ₂ for exposure level adjustment, and the transistors Q ₁₀ and Q _{11 are connected.} The inter-base voltage of is a value corresponding to the film sensitivity and the correction value. Now
If the collector current of the transistor Q ₁₁ is Ic, when the transistor Q ₈₁ is on, the currents flowing through the resistors R ₃₄ and R ₃₅ are both (1 + n) Ic. Here, when the film sensitivity input variable resistor RV ₁ has a low value, that is, when a high-sensitivity film is used, the collector current Ic of the transistor Q ₁₁ is small, and therefore (variable resistor RV ₅
Resistance value) × (collector current Ic of transistor Q ₂₁ )
, The collector potential of the transistor Q ₂₁ becomes low, and the output of the comparator A ₆ becomes “L” level. Therefore, the transistor Q ₈₁ is turned off and the resistors R ₃₄ and R ₃₅ are turned on.
The voltage drop of the is large. Therefore, the voltage applied to the inverting input terminals of the comparators A ₇ and A ₈ rises. This means that the determination voltage level of the integrating circuit during direct photometry has increased and the determination voltage width has expanded.
Even if the range of the judgment voltage is widened, the capacitance of the integrating capacitor becomes the capacitance of only _one capacitor C ₁ at the same time, so that the correct exposure can be obtained. Which film sensitivity level is used for switching is set in advance by adjusting the semi-fixed resistor RV ₅ . By the way, 2 of comparator A ₆
If the potential difference between the two input terminals is small and the output of the comparator A ₆ becomes unstable due to noise or the like during exposure, an error will be given to the exposure. Therefore, after the shutter release operation, the release signal S0 becomes "H" level and the latch Latch the output of the circuit DF ₀ .

FIG. 10 shows the strobe over / under determination circuit 6 described above.
5 and detailed electrical circuits of the first comparison circuit 54 are shown. The strobe over / under determination circuit 65 is a part that determines whether the exposure level is over or under when the flash photography is performed by direct photometry. As described above, the decision input terminals of the comparators A ₇ and A ₈ are connected to the collectors of the transistors Q ₁₈ and Q ₁₇ (see FIG. 9) respectively, and the non-inverting input terminal thereof is connected to the operational amplifier A ₂ ( The integrated output S2 of the direct photometry is applied from the respective output ends (see FIG. 8). The output terminal of the comparator A ₇ is connected to the first input terminal of the three-input NAND circuit G ₂₂ , and the output terminal of the comparator A ₈ is the second input terminal of the NAND circuit G ₂₂ , D.
Of the flip-flop circuit DF _{1 and} the input terminal of the knot circuit G ₂₈ . The comparator A ₈ is a comparator for exposure control during direct photometry, and compares the integrated output S2 from the head amplifier circuit 51 with the output from the analog exposure information introducing circuit 53 to determine the exposure level during direct photometry. Forming a first comparison circuit 54 for determining Further, the comparator A _{7 is} also a judgment comparator for the integrated output S2,
The determination level of the comparator A ₇ is set to √√ times the determination level of the comparator A ₈ . That is, since the ratio of the resistance values of the resistors R ₃₄ and R ₃₅ is set to ▲ √ ▼ times, the potential at the inverting input terminal of the comparator A ₇ becomes
It is ▲ √ ▼ times that of the comparator A ₈ . The clock pulse CK is applied to the clock input terminal of the D-type flip-flop circuit DF ₁ , and the inverting output terminal is connected to the third input terminal of the NAND circuit G ₂₂ . The output terminals of the NAND circuit G ₂₂ are connected to the NAND circuits G ₂₃ and G _24.
The RS flip-flop circuit in the form, and is connected to one input terminal of the NAND circuit G ₂₃ is a reset input. The other input end of the NAND circuit G ₂₄ , which is the set input end of the RS flip-flop circuit, receives the strobe charge gate signal T4 from the inverting output end of the RS flip-flop circuit RSF ₄ (see FIG. 16). It has become. Then, from the output terminal of the NAND circuit G ₂₃ which is the output of the RS flip-flop circuit, if overexposed when flash photography in direct photometric 'H' level of flash photography over signal S9 is flash charging gate signal CPU only while T4 is'H 'level
It is designed to be output to the input port I14 of 50.
The output terminal of the NAND circuit G ₂₄ , which is the inverting output terminal of the RS flip-flop circuit, is the first input terminal of the 3-input AND circuit G ₉₈ .
Is connected to the input end of. On the other hand, the knot circuit G ₂₈
The shutter control signal S17 at the time of direct photometry is output from the output terminal to the first selection circuit 55 (see FIG. 15), and this signal S17 is the other signal of the NAND circuit G ₂₇ . It is also input to the input terminal. The strobe under limit signal T6 is applied to one input terminal of the NAND circuit G ₂₇ from the inverting output terminal of the RS flip-flop circuit RSF ₆ (see FIG. 16). The output terminal of the NAND circuit G _{27 is connected to} the NAND circuit G ₂₇
It is connected to the other input terminal of the NAND circuit G ₂₆ which is the reset input terminal of the RS flip-flop circuit formed by ₂₅ and G ₂₆ . Moreover, to one input terminal of the NAND circuit G ₂₅ is a set input of RS flip-flop circuit, the strobe charge gate signal T4 is adapted to be applied. From the output terminal of the NAND circuit G ₂₆ , which is the output terminal of the RS flip-flop circuit, if the exposure is underexposure when the flash is photographed by direct photometry, the flash photographing under signal S10 of'H 'level is generated and the strobe charging gate signal T4 is output. Is input to the input port I15 of the CPU 50 only during the "H" level. Further, the NAND circuit G ₂₅ which is the inverting output terminal of the RS flip-flop circuit.
The output terminal of is connected to the third input terminal of the AND circuit G ₉₈ . The second input terminal of the AND circuit G _98, the strobe charge gate signal T4 are applied, the output terminal of the AND circuit G ₉₈ is connected to the input port I16,
Only when the strobe is appropriate after strobe emission, the strobe emission appropriate signal S20 which is at the “H” level for about 2 seconds is output. The strobe charging gate signal T4 is the first
As shown in FIG. 8 (g), the strobe tuning time signal T3 is inverted to the “L” level, and at the same time, turned to the “H” level.
This is a signal that becomes “H” level for 2 seconds after this. The strobe under limiter signal T6 is shown in FIG.
As shown in (h), it is a signal that changes to the “H” level 22 ms after the trigger signal S1 is inverted to the “H” level. Further, the clock pulse CK is
As shown in Figure (a), at 32.768KHz, 'H' level, 'L'
It is a rectangular wave signal that repeats levels.

Next, the operation of the strobe over / under determination circuit 65 thus configured will be briefly described. Immediately after the shutter is released, the integrated output S2 is small, so the output of the comparator A ₈ is at the “L” level. Therefore,
At this point, the output of the inverting output terminal of the D-type flip-flop circuit DF ₁ and the output of the knot circuit G ₂₈ are at the “H” level. However, the second input terminal of the NAND circuit G ₂₂ and one input terminal of the NAND circuit G ₂₇ are at the “L” level, and the NAND circuits G ₂₂ and G ₂₇
Output is at the'H 'level. Also, FIG.
As can be seen from (g), since the strobe charge gate signal T4 is at the “L” level immediately after release, the strobe photography over signal S9 and the strobe photography under signal S10, which are the outputs of the RS flip-flop circuit, are each at the “L” level. It has been reset to. Now, it is assumed that the shooting mode of the camera 10 is the direct photometry shooting mode. When the trigger switch SW ₂ shown in FIG. 12 opens, the integrated output S2 of the head amplifier circuit 51 shown in FIG.
The potential of gradually rises. The shutter is fully open,
When the strobe trigger thyristor SCR ₁ serving as the X-contact shown in FIG. 15 is turned on, strobe flash light is emitted. When the potential of the integrated output S2 becomes higher than the potential of the non-inverting input terminal of the comparator A ₈ , the comparator A ₈
At the same time that the output of ₈ is inverted to the “H” level, the output of the inverted output terminal of the D-type flip-flop circuit DF ₁ is changed to the “L” level with a delay of one pulse of the clock pulse CK. As a result, the inverted output of the output of the comparator A ₇ is output to the output terminal of the NAND circuit G ₂₂ for one cycle of the clock pulse CK after the output of the comparator A ₈ is changed to the “H” level. Here, as described above, the determination level of the comparator A ₇ is the comparator A ₈
Since the output of the comparator A _{8 serving as} the shutter control signal S17 is turned to the “H” level through the knot circuit G ₂₈ , it is 100 μs which is one cycle of the clock pulse CK. Exposure within
If 0.5Ev or more, the output of comparator A ₇ is'H '.
The output level of the NAND circuit G ₂₂ is'L '.
When the level becomes high, the strobe photographing over signal S9, which is the output of the RS flip-flop circuit, is set to the'H 'level, and an overexposure warning is displayed as described later.

On the other hand, after strobe light emission, comparator A ₈
When the output of is still at the “L” level, that is, when the exposure level is still under, the strobe under limit signal T6 shifts to the “H” level, so that the output of the NAND circuit G ₂₇ becomes the “L” level. The flash photography under signal S1 inverted and output from the RS flip-flop circuit
0 is set to the'H 'level, and an under-exposure warning is displayed as described later. Shutter control signal S17
Since it takes about 6 ms from the occurrence of the above to the shutter rear curtain moving within the shooting image frame, the underexposure determination is also delayed until then.

In addition, the warning display of overexposure and underexposure,
The CPU 50 determines the shooting mode, and this is performed only when stroboscopic shooting is performed by direct photometry. As for the over- and under-exposure warning display, the strobe charge gate signal T4 shifts to the “L” level after 2 seconds have elapsed from the strobe light emission.
The RS flip-flop circuit composed of the NAND circuits G ₂₃ and G ₂₄ and the RS flip-flop circuit composed of the NAND circuits G ₂₅ and G ₂₆ are reset, and the strobe photographing over signal S9 and the strobe photographing under signal S10 are respectively at the “L” level. Stopped by flipping to.

If neither overexposure nor underexposure has occurred after strobe light emission, the first and third input terminals of the AND circuit G ₉₈ are at the “H” level, so the strobe charge gate signal T4 is at the “H” level. 'For 2 seconds, the level
From the output terminal of the AND circuit G ₉₈ 'H' level of the strobe light emission proper signal S20 is output. This allows the CPU
With the program of 50, the proper exposure is displayed for 2 seconds during flash photography with direct metering.

FIG. 11 shows a detailed electric circuit of the power supply hold circuit 67. The power supply hold circuit 67 is a circuit that supplies power to the magnet drive circuit 56 and the strobe control circuit 66 after shutter release, and automatically shuts off power after exposure. An operating voltage supply line L ₁ is drawn out from the positive electrode of the power supply battery E _1, a common ground line L ₀ is drawn out from the negative electrode, and the ground line L ₀ is grounded. A series circuit of a battery check switch SW ₅ and resistors R ₃₈ and R ₃₉ is connected between both lines L ₁ and L ₀ . The battery check switch SW ₅ is provided on the “CH” of the mode switching operation knob 21.
It is a self-reset type switch that is closed in conjunction with the operation corresponding to the "ECK" index. The connection point between the switch SW ₅ and the resistor R ₃₈ is one of the AND circuits G ₃₈ (see FIG. 13). It is connected to the input end. The connection point between the resistors R ₃₈ and R ₃₉ is connected to the base of the NPN transistor Q ₂₃ . The collector of the transistor Q ₂₃ is connected to the base of the transistor Q ₃₄ through a resistor R _40, the emitter is grounded. The base of the transistor Q ₂₃ is connected to the collector of the NPN-type transistor Q _24, the emitter of the transistor Q ₂₄ is grounded, and the base through a resistor R _41, and is connected to the collector of the PNP transistor Q ₂₅ . Transistor Q ₂₅ is connected to the emitter to the line L _1, PNP-type transistor Q ₂₈ of the _{base, Q 29, Q 30, Q} 31, Q 32 and are respectively connected to the base of Q _33, the transistors Q _25, Q
_The emitters of ₂₉ , Q ₃₀ , Q ₃₁ , Q ₃₂ and Q ₃₃ are connected to the line L ₁ , respectively, and form a current mirror circuit with the transistor Q ₂₈ .

In addition, the release switch S is provided between the lines L ₁ and L _0.
A series circuit of W ₁ , a capacitor C ₆ , and resistors R ₄₄ and R ₄₃ is connected. The release switch SW ₁ is a switch that opens and closes in conjunction with the movable reflection mirror 31, and is closed at the initial stage of raising the mirror 31 and opened at the final stage of lowering. The connection point between the release switch SW ₁ and the capacitor C ₆ is grounded through the resistor R ₄₂ .
The connection point between the resistors R ₄₄ and R ₄₃ is connected to the base of the NPN transistor Q ₂₆ , and
The emitter of ₂₆ is grounded, and the collector is connected to the emitter of NPN transistor Q ₂₇ . Transistor Q
_The base of ₂₇ is connected to the emitter of a transistor Q ₃₉ (see FIG. 12) through a resistor R ₉₉ , and the collector is connected to the collector of an NPN type transistor Q ₃₅ . In the transistor Q ₃₅ , the collector is also connected to the collector and the base of the transistor Q ₂₈ through the resistor R ₄₅ , the emitter is grounded, and the base is connected to the connection point between the resistors R ₄₈ and R ₄₇ through the resistor R _46. Has been done. One end of the resistor R ₄₈ is connected to the collector of the transistor Q ₂₉ , and the other end of the resistor R ₄₇ is grounded. Also, the resistance R
The connection point between ₄₈ and R _47, is also connected to the collector of the NPN-type transistor Q _36, the emitter of the transistor Q ₃₆ is grounded, and the base through a resistor R ₅₉ (see FIG. 13), the NAND circuit G It is connected to the output terminal of ₃₃ (see FIG. 13). The collector of the transistor Q ₃₀ is connected to the base of the transistor Q ₄₆ (see FIG. 12) through the resistor R ₄₉ . Also, the transistor Q ₃₁
Is connected to the input terminal of the knot circuit G ₁₀₂ (see FIG. 13) as well as being grounded through the resistor R ₅₀ . Further, the collector of the transistor Q ₃₂ is grounded through the resistor R ₅₁ and is also connected to the control signal input terminal of the latch circuit DF ₀ (see FIG. 9), and the collector voltage of the transistor Q ₃₂ is The release signal S0 is supplied. Furthermore, the collector of the transistor Q ₃₃ is connected to the collector of the PNP type transistor Q ₃₄ , and
It is connected to the base of an NPN transistor Q ₃₇ through a resistor R ₃₂ . The emitter of the transistor Q ₃₇ is grounded, and the collector is connected to one ends of the magnet drive circuit 56 and the strobe control circuit 66, respectively.
The other ends of the magnet drive circuit 56 and the strobe control circuit 66 are connected to the line L ₁ , respectively. Therefore, the transistor Q ₃₇ functions as a switching transistor that controls the power supply to the magnet drive circuit 56 and the strobe control circuit 66. Also, the transistor Q ₃₇
Is also connected to the cathode of the light emitting diode D ₀ (see FIG. 13) for battery check display and one end of the resistor R ₅₈ (see FIG. 13). The transistor Q ₃₄ has its emitter connected to the line L ₁ and its base connected to the collector of the transistor Q ₂₃ through the resistor R ₄₀ , and is forcibly turned on during the battery check operation, and the magnet drive circuit 56 and the strobe control circuit are connected. This is for the battery check to be performed in the state of maximum current consumption when power is supplied to 66.

FIG. 12 shows a detailed electric circuit of the trigger timing adjusting circuit 52. The trigger timing adjustment circuit 52 is a circuit for adjusting the photometry start timing in the head amplifier circuit 51. Trigger switch SW
Reference numeral ₂ denotes a switch that opens in association with the start of the shutter front curtain and closes in association with the completion of film winding. The switch receives a power supply voltage Vcc at one end and is closed at the other end.
It is connected to the base of a PN transistor Q ₃₉ . The transistor Q ₃₉ has a PNP-type transistor Q as its collector.
₃₈ collector and emitter resistor R ₉₉ (See Fig. 11)
Through transistor Q ₂₇ (see FIG. 11). The transistor Q ₃₈ receives the power supply voltage Vcc at its emitter, and its base is connected to the bases of the PNP type transistors Q ₄₀ and Q ₄₈ , respectively. The trigger switch SW ₂ and is connected to the trigger timing delay capacitor C ₇ in parallel, the capacitor C _7,
One end of the base of the transistor Q _{39 is connected to} the base of the PNP transistor Q ₄₁ and one end of a semi-fixed resistor RV ₆ for determining a trigger delay time together with the capacitor C ₇ . The collector of the transistor Q ₄₁ is grounded, and the emitter is a PNP transistor Q.
Connected to ₄₂ bases. The emitter of the transistor Q ₄₂ is connected to the collector of the transistor Q ₄₀ ,
The power supply voltage Vcc is applied to the emitter of the transistor Q ₄₀ . The collector of the transistor Q ₄₂ is NP
It is connected to the base of the N-type transistor Q ₄₇ and also to the collector of the NPN-type transistor Q ₄₃ . The emitter of the transistor Q ₄₃ is grounded,
The base is connected to the base and collector of the NPN transistor Q ₄₄ . The emitter of the transistor Q ₄₄ is grounded and the collector is a PNP transistor Q _49.
Connected to the collector. The emitter of the transistor Q ₄₉ is connected to the collector of the transistor Q ₄₀ ,
The base is connected to the emitter of PNP transistor Q ₄₅ . The collector of the transistor Q ₄₅ is grounded, the base receives the power supply voltage Vcc through the resistor R ₅₃ , and the NPN type transistor Q ₄₆ through the resistor R _54.
Connected to the collector. The emitter of the transistor Q ₄₆ is grounded, and the base is connected to the collector of the transistor Q ₃₀ (see FIG. 11) through the resistor R ₄₉ (see FIG. 11). The collector of the transistor Q _46, together with being connected to the other end of the time constant Trimmer resistor RV _6, is connected to the collector and base of the transistor Q ₄₈ through a resistor R _61. Transistor Q
_A power supply voltage Vcc is applied to the emitter of ₄₈ , and the transistor Q ₄₈ forms a current mirror circuit with the transistors Q ₃₈ and Q ₄₀ . The emitter of the transistor Q ₄₇ is grounded, the collector receives the power supply voltage Vcc through the resistor R ₅₅ , and the collector also receives one input terminal of the NAND circuit G ₃₂ (see FIG. 13). And a knot circuit G ₁₀₁ , respectively. The above transistors Q _{40 to} Q
₄₉ and the resistors R _{53 to} R ₅₅ and R ₆₁ constitute a differential amplifier circuit, and the base of the transistor Q ₄₁ is a non-inverting input terminal,
The base of the transistor Q ₄₆ is the inverting input terminal, and the collector of the transistor Q ₄₇ is the output terminal. The output terminal of the output transistor the NOT circuit G ₁₀₁ whose collector is connected to an input terminal of Q _47, the resistance R ₁₅ be connected to the base of the transistor Q ₃ through (FIG. 8 refer) (see FIG. 8) (see FIG. 18 (b)) for supplying a trigger signal S1 is inverted the transistor Q ₃ to 'H' level at a predetermined elapsed time after the opening of the trigger switch SW _2.

FIG. 13 shows a detailed electric circuit of the battery check circuit 63 and the power source hold releasing circuit 64.
First, the configuration of the power hold release circuit 64 will be described.
The power hold release circuit 64 is the power hold circuit 6 described above.
It is a circuit for canceling the power hold state of No. 7,
There are three ways to release the power supply hold: when the power supply voltage Vcc is equal to or lower than the specified voltage, when the shutter is closed for a predetermined time, and when the shutter is forcibly turned off during a long exposure. Therefore, the NAND circuit G _33, which is the output terminal of the power supply hold canceling circuit 64, is provided with three input terminals. The first input terminal is connected to the output terminal of the NAND circuit G _32, one input terminal of the NAND circuit G ₃₂ is the collector of the transistor Q ₄₇ (see FIG. 12), the other input terminal NOT circuit It is connected to the output terminal of the comparator A ₁₀ via G ₃₄ . When the power supply voltage Vcc is below the specified level, the output of the comparator A ₁₀ becomes the “L” level, so that the output of the NAND circuit G ₃₂ becomes the “L” level and the power supply hold is released. However, the release of the power supply hold due to the decrease of the power supply voltage Vcc causes the exposure error to increase or the trailing curtain holding magnet MG ₁ (15th) when the power supply voltage Vcc drops during the exposure and the power supply hold is released. Since the operation (see the figure) becomes unstable, the operation is performed only before the exposure operation is performed. That is, the collector voltage (trigger signal) of the transistor Q ₄₇ (see FIG. 12) and the knot circuit G ₃₄
The inversion signal of the logical product with the output of is used as a signal for releasing one power supply hold. A power hold release signal S12, which is a delay signal of the exposure end signal S13, is applied from the delay circuit DL ₀ (see FIG. 15) to the second input terminal of the NAND circuit G ₃₃ . . Further, the third input terminal of the NAND circuit G ₃₃ is connected to the output terminal Q of the RS flip-flop circuit RSF ₂ (see FIG. 16) to apply the auto limiter signal T2 which also serves as a power supply limiter signal. I am supposed to receive it. The output terminal of the NAND circuit G ₃₃ is connected to the base of the transistor Q ₃₆ (see FIG. 11) through the resistor R ₅₉ .

On the other hand, the battery check circuit 63 is a circuit for detecting whether or not the power supply voltage Vcc is equal to or higher than a specified voltage. This circuit is provided with a series circuit of resistors R ₅₆ , R ₅₇ and R _{58 to} one end of which a power supply voltage Vcc is applied, and the connection point between the resistors R ₅₆ and R ₅₇ is the non-inverting input of the comparator A _10. At the end, the connection point between the resistors R ₅₇ and R ₅₈ is the comparator A ₁₁
Are connected to the non-inverting input terminals of. The reference voltage V ₁ is applied to the inverting input terminals of both comparators A ₁₀ and A ₁₁ . The output terminal of the comparator A ₁₀ is the second input terminal of the 3-input NAND circuit G ₃₅ , the third input terminal of the 3-input NAND circuit G ₃₆ , and the knot circuit G _34.
Are respectively connected to the input ends of. The output terminal of the comparator A ₁₁ is connected to the second input terminal of the NAND circuit G ₃₆ . To the first input terminal of the NAND circuit G ₃₅ , a blinking cycle signal T8 consisting of a pulse signal of about 10 Hz is applied from the timer circuit 68 shown in FIG. Also, the third input terminal of the NAND circuit G ₃₅ and the NAND circuit G ₃₅
The first input terminal _36, is connected to the output terminal of the AND circuit G _38, one input terminal of the AND circuit G ₃₈ is connected to one end of the battery check switch SW ₅ (see FIG. 11), The other input end is connected to the collector of a transistor Q ₃₁ (see FIG. 11) via a knot circuit G ₁₀₂ . The output terminals of the NAND circuits G ₃₅ and G ₃₆ are connected to one and the other input terminals of the NAND circuit G ₃₇ , respectively, and the output terminal of the NAND circuit G ₃₇ is connected to the battery check display light emitting diode D through a resistor R _{60. 0} connected to the anode. The light emitting diode D ₀ is arranged so as to correspond to the battery check display light emitting window 23, and its cathode is connected to the collector of the transistor Q ₃₇ (see FIG. 11).

Next, the operations of the power supply hold circuit 67, the trigger timing adjustment circuit 52, the power supply hold release circuit 64 and the battery check circuit 63 shown in FIGS. 11 to 13 will be briefly described. Now, when the shutter release button 11 (see FIGS. 1 and 2) is pressed, the release switch SW ₁ interlocked with this is closed, and the transistor Q ₂₆ is turned on through the capacitor C ₆ and the resistor R ₄₄ . Since the trigger switch SW ₂ is closed at this point,
Transistor Q ₂₇ is on, transistor Q ₂₈ is on through resistor R ₄₅ , and transistors Q ₂₉ and Q ₃₅
Turns on. Once the transistor Q ₃₅ is turned on, the base current is supplied from the collector of the transistor Q ₂₉ thereafter, so that the power supply hold state is maintained. And
When the transistor Q ₂₈ turns on, the transistors Q _{29 to} Q
Since all ₃₃ are turned on, the transistor Q ₃₇ is also turned on,
Power is supplied to the magnet drive circuit 56 and the strobe control circuit 66. On the other hand, the trigger timing adjustment circuit 5
2, the base current is supplied to the transistor Q ₄₆ through the transistor Q ₃₀ . Then, when the movable reflecting mirror 31 completes the ascent and the shutter front curtain starts running and the trigger switch SW ₂ is opened, the transistor Q ₄₁ is opened.
The base potential of the capacitor gradually decreases, and the time constant of the delay circuit composed of the capacitor C ₇ and the semi-fixed resistor RV ₆ and the resistors R ₅₃ , R ₅₄
After the ratio between the delay time determined by the output transistor Q ₄₇ is turned on, the output of the NOT circuit G ₁₀₁ is inverted to 'H' level (see FIG. 18 (b)). This'H 'level signal is applied as a trigger signal S1 to the base of the transistor Q ₃ through the resistor R ₁₅ (see FIG. 8), the transistor Q ₃ turns on and the transistors Q ₅ and Q ₁ turn off, It is possible to integrate the photocurrent by direct photometry. Subsequently, the trailing-curtain holding magnet MG ₁ (see FIG. 15) is demagnetized, and when a predetermined delay time elapses after the shutter trailing curtain starts traveling, the delay circuit DL ₀ (see FIG. 15) outputs L 'level of the power supply hold release signal S12 is output, the output of the NAND circuit G ₃₃ is' becomes H' level, the transistor Q ₃₆ is turned on, is cut off the base current of the transistor Q ₃₅ is released power hold state To be done. That is, when the transistor Q ₃₅ is turned off, the transistors Q ₂₈ , Q ₃₃ , and Q ₃₇ are sequentially turned off, and the power supply to the magnet drive circuit 56 and the strobe control circuit 66 is cut off.

Further, when the power supply voltage Vcc is lower than the specified voltage, the output of the comparator A ₁₀ becomes “L” level, and the NAND circuit G 10
_Since one input terminal of ₃₂ is normally at the “H” level, the output of the NAND circuit G ₃₂ is inverted to the “L” level. For this reason,
The transistor Q ₃₆ is turned off, and the power supply hold state is released in the same manner as described above. By the way, when the power supply hold state is released due to the decrease in the power supply voltage Vcc, if the power supply voltage Vcc decreases during exposure, the exposure error becomes large if the power supply hold is cut off, or the trailing curtain holding magnet MG is used.
_Since the operation of ₁ (see FIG. 15) becomes unstable, in order to prevent this, it is not performed during exposure. That is, during exposure, the collector voltage of the transistor Q ₄₇ , which serves as a trigger signal, becomes the “L” level, and therefore this signal and the inverted signal of the output of the comparator A ₁₀ and the inverted output of the logical product are used to cancel the power supply hold. One signal is input to the first input terminal of the NAND circuit G ₃₃ . Therefore, the release of the power supply hold due to the decrease of the power supply voltage Vcc is performed until the trigger switch SW ₂ is opened. If the power supply hold is released during this time, the movable reflecting mirror 31 is mechanically raised. I try to lock it in the middle position.

Further, the power supply hold circuit 67 is configured to forcibly turn off the power supply hold when a predetermined time has elapsed in the case where the image is taken in a very dark place and exposed for a long time. This is because it is considered kinder to prevent the power supply battery E ₁ from being consumed than to shoot when the exposure time is several minutes. Therefore, being adapted to auto limiter signal T2 is input serving as a power limiter signal to the third input terminal of the NAND circuit G _33, the signal T2 is 18
As shown in FIG. 6E, after a predetermined time (120 s) has elapsed since the trigger was released, the trigger is inverted to the “L” level, and the power supply hold is cut off in the same manner as described above.

In addition, from the emitter of the transistor Q ₃₉ to the transistor Q
_A signal is supplied to the resistor ₂₇ through the resistor R _99. This is because when the release switch SW ₁ is opened when the movable reflecting mirror 31 is lowered, chattering occurs and the power supply hold circuit 67 returns to the power supply hold state. This is because the transistor Q ₂₇ is turned off when the trigger switch SW ₂ is opened to prevent the power supply hold state.

On the other hand, when the battery check is performed, the photographing mode switching operation knob 21 (see FIG. 2) is set to "CHEC".
Corresponds to the "K" index. Then, the battery check switch SW ₅ is turned on, and one input end of the NAND circuit G ₃₈ becomes the “H” level. Now, when the power supply hold circuit 67 is not in the power supply hold state, that is, when the shutter release operation is not being performed, the output of the knot circuit G ₁₀₂ is at the “H” level, and the output of the NAND circuit G ₃₈ is at the “H” level. It becomes a level. First, as the first case, when the power supply voltage Vcc is higher than the specified voltage, the comparator A
_Since the outputs of ₁₀ and A ₁₁ are both at'H 'level,
The output terminal of the NAND circuit G ₃₅ outputs flashing period signal T8, the output terminal of the NAND circuit G ₃₆ becomes 'L' level. Therefore, the'L 'level output of the NAND circuit G ₃₆ has priority,
The output terminal of the NAND circuit G ₃₇ becomes “H” level, and the battery check display light emitting diode D ₀ is turned on. Therefore, it is displayed that the power supply voltage Vcc is equal to or higher than the specified voltage. Next, as a second case, when the power supply voltage Vcc is equal to or higher than a certain specified voltage but is lower than another specified voltage, that is, as compared with the reference voltage V ₁ , a connection point between the resistors R ₅₆ and R _57. Is high, but when the potential of the connection point between the resistors R ₅₇ and R ₅₈ is low, the output of the comparator A ₁₀ is'H 'level and the output of the comparator A ₁₁ is'L' level.
While the output of the NAND circuit G ₃₆ becomes 'H' level, the output terminal of the NAND circuit G ₃₅ is output blinking cycle signal T8. Therefore, this time, the NAND circuit G ₃₇ has a blinking cycle signal T.
8 is output, and the light emitting diode D ₀ is in a state of repeating blinking at about 10 Hz. Therefore, the fact that the power supply voltage Vcc has dropped is displayed, and the replacement of the power supply battery E ₁ is urged. Furthermore, in the third case, when the power supply voltage Vcc drops below the other specified voltage and the electric circuit of the camera 10 cannot operate, the outputs of the comparators A ₁₀ and A ₁₁ are both low. 'It becomes the level, and NAND circuit G ₃₅ , G
The output of the ₃₆ becomes either 'H' level, the output of the NAND circuit G ₃₇ becomes 'L' level. Therefore, the light emitting diode D ₀ remains in the off state without being lit, and it is displayed that the power supply voltage Vcc is equal to or lower than the specified voltage.

During the shutter release operation, the shooting mode switching operation knob 21 is operated and the battery check switch SW ₅
When is closed, the output of the knot circuit G ₁₀₂ becomes the “L” level, the output of the NAND circuit G ₃₈ becomes the “L” level, and the output of the NAND circuit G ₃₇ becomes the “L” level. Therefore, the battery check display by the light emitting diode D ₀ is not made. In addition, at the time of the battery check, transistor Q ₃₄ through the transistor Q ₂₃
Is forcibly turned on, and the magnet drive circuit 56 and the strobe control circuit 66 are forcibly energized so that the battery check is performed in the state where the current consumption is maximum.

FIG. 14 shows a detailed electric circuit of the strobe determination circuit 62. The strobe determination circuit 62 determines whether or not the power source of the strobe is turned on and whether or not the charging is completed, by determining the current level of the signal S15 input through one signal line from the strobe. It is a circuit for detecting. The NPN transistor Q ₅₀ is a diode-connected transistor, the power supply voltage Vcc is applied to the emitter, and the collector and the base have the strobe mounting shoe 24 or the strobe connecting connector 25 (see FIGS. 1 and 2). ) Electrical contacts to a strobe (not shown) electrical circuit. A series circuit of resistors R ₆₇ and R ₆₅ is connected in parallel with the transistor Q ₅₀ , and the resistor R ₆₇ has a PNP transistor Q ₅₁ whose emitter is the power source and whose collector is the strobe. It is connected in parallel. The collector of this transistor Q ₅₁ is PN
It is also connected to the base of the P-type transistor Q _{52, and} the base is connected to the emitter of the transistor Q ₅₂ and the bases of the PNP-type transistors Q ₇₇ and Q ₅₆ , respectively. The collector of the transistor Q ₅₂ is grounded through a resistor R _68, the emitter of the transistor Q ₇₇ is applied the power source voltage Vcc, and the collector is grounded through a resistor R _70, R ₆₉ in series. Connection point of the resistors R _70, R ₆₉ is connected to the base of an NPN transistor Q _53, the emitter of the transistor Q ₅₃ is grounded, the power supply voltage Vcc collector through a resistor R _71, R ₇₂ in series Is being applied. The connection points between the resistors R ₇₁ and R ₇₂ are connected to the bases of PNP type transistors Q ₅₄ and Q ₅₅ , respectively, and the emitter of the transistor Q ₅₄ has a power supply voltage V
cc is applied and the collector is grounded through a resistor R ₇₉ . Also, from the collector of the transistor Q _54, the signal lines are drawn for transmitting a strobe power-on signal S14, is connected to an input port I13 of CPU 50 (see FIG. 7). The transistor Q ₅₅ is applied a power supply voltage Vcc to the emitter, collector through a resistor R _73, the base and collector of NPN type transistor Q _57, as well as the base of an NPN transistor Q _58,
Each is connected. The emitter of the transistor Q ₅₇ is grounded, the collector of the transistor Q ₅₈ is connected to the collector of the transistor Q ₅₆ , and the emitter is grounded through the resistor R ₇₄ . Transistor Q ₅₆ is
The power supply voltage Vcc is applied to the emitter, the collector is further grounded through the resistor R ₇₅ , and is connected to the base of the NPN transistor Q ₅₉ through the resistor R ₇₆ . The transistor Q ₅₉ has a collector to which a power supply voltage Vcc is applied through a resistor R ₇₇ and a collector to ground. The collector of the transistor Q ₅₉ is connected to the input terminal of the knot circuit G ₃₉ , and
The output terminal of ₃₉ is connected to one input terminal of the AND circuit G ₄₀ . The other input end of the AND circuit G ₄₀ is connected to the inversion output end of the RS flip-flop circuit RSF ₄ (see FIG. 16) via the knot circuit G ₄₁ , and receives the inversion signal of the strobe charging gate signal T4. It is like this. The output terminal of the AND circuit G ₄₀ is connected to the base of the NPN transistor Q ₆₀ through the resistor R ₇₈ , the emitter of the transistor Q ₆₀ is grounded, and the collector is the cathode of the strobe charge completion indicating light emitting diode D ₁ . It is connected to the. The light emitting diode D ₁ is incorporated in the photographing information display device 39, and the charging of the strobe is completed in the viewfinder. It emits light in a circular pattern. Light emitting diode D
₁ of the anode is connected to one end of the constant current circuit CC _3, the other end of the constant current circuit CC ₃ power supply voltage Vcc is applied.

Next, the operation of the strobe determination circuit 62 thus configured will be briefly described. First, when a power switch for a strobe (not shown) is turned on, a current of about 10 μA flows as a strobe power signal S15 toward the strobe. Then, the transistor Q ₅₂ is turned on, and subsequently, the transistors Q ₅₁ , Q ₇₇ , Q ₅₃ , and Q ₅₄ are sequentially turned on. Therefore, the collector of the transistor Q ₅₄ becomes the “H” level. In addition, transistors Q ₅₅ , Q ₅₆ ,
Q ₅₈ is also turned on, but the strobe power signal S15 is 10μA
To some extent, the base current of transistor Q ₅₆ is small and the collector potential is not high enough to supply current to the base of transistor Q ₅₉ , so transistor Q ₅₉ remains off. Therefore, the output of the knot circuit G ₃₉ becomes the “L” level, the output of the AND circuit G ₄₀ also becomes the “L” level, the transistor Q ₆₀ does not turn on, and the charge completion indicating light emitting diode D ₁ does not light. Next, when the charging of the strobe is completed, a current of about 100 μA flows toward the arm as the strobe charge signal S15. Then, the collector potential of the transistor Q ₅₆ becomes sufficiently high, transistor Q ₅₉ is turned on sufficient base current flows through the transistor Q _59. As a result, the transistor Q
The collector potential of ₅₉ decreases, and the output of the knot circuit G ₃₉ becomes “H” level. The strobe charging gate signal T4
Is a signal that is at the “H” level for about 2 seconds after the strobe is generated. Therefore, the output of the AND circuit G ₄₀ is at the “L” level for about 2 seconds after the strobe light is emitted, and the signal is at the “L” level for other periods. the output of circuit G ₄₀ becomes 'H' level, the transistor Q ₆₀ is turned on. Therefore, a current flows from the constant current circuit CC ₃ to the light emitting diode D ₁ , the diode D ₁ emits light, and the completion of charging the strobe is displayed. The reason why the strobe charge completion indication is not displayed for about 2 seconds after the strobe light is emitted is that the strobe light is turned on and off at about 100 μA after the strobe light is emitted through the same signal line as the strobe power signal and the strobe charge signal S15. Since the exposure proper signal is repeatedly sent, the light emitting diode D ₁
It is necessary to disable the operation of. The proper flash photography is displayed by blinking the liquid crystal display plate of the photography information display device 39 as described later.

FIG. 15 shows a detailed electric circuit of the selection circuit 55, the magnet drive circuit 56 and the strobe control circuit 66 of FIG. Whether the first selection circuit 55 should control the magnet drive circuit 56 with the shutter control signal S17 by direct photometry according to the photographing mode, or the CPU
It is a circuit for selecting whether or not to control by the shutter control signal S16 output from 50. The first input terminal of the NAND circuit G ₄₈ is connected to one end of the auto switch SW ₄ (see FIG. 7), and is a signal which becomes'H 'level only in the same auto mode as that input to the input port 10 of the CPU 50. Is applied. Also, the NAND circuit G
The second input end of ₄₈ is connected to the output end of a NAND circuit G ₃ (see FIG. 7) via a knot circuit G ₄₆ , and CP
The inverted signal of the signal which becomes the'H 'level is applied only in the same memory mode as that input to the input port I6 of U50. Further, the third input terminal of the NAND circuit G ₄₈ is connected to the NAND circuit G ₉ via the knot circuit G _47.
(See FIG. 7) is connected to the output terminal of the CPU 50
The inverted signal of the signal which becomes the “H” level is applied only in the same spot mode as that input to the input port I2. Therefore, only when the NAND circuit G ₄₈ is in the auto mode, neither in the memory mode nor in the spot mode, that is, when the average direct auto mode is selected, all the inputs become the “H” level and the output thereof. Becomes the'L 'level. An inverted signal of the signal applied to the first input terminal of the NAND circuit G ₄₈ is input to one input terminal of the NAND circuit G ₅₁ via the knot circuit G _49, and the other input terminal is input. The input end is connected to one end of the manual switch SW ₃ (see FIG. 7) via the knot circuit G ₅₀ , and becomes the “H” level only at the same manual time as when input to the input port 11 of the CPU 50. An inverted signal of the signal is input. Thus, the output of the NAND circuit G ₅₁ is neither in the auto mode, and no imaging mode in manual mode,
That is, the level becomes'L 'only in the off mode. The output terminal of the NAND circuit G ₄₈ is connected to one input terminal of the NAND circuit G _52, the output terminal of the NAND circuit G ₅₁ is, the NAND circuits G ₅₂
Of the NAND circuit 62 and one of the input terminals of the NAND circuit G ₆₄ through the NOT circuit G ₆₃ . The output terminal of the NAND circuit G ₅₂ is connected to the other input terminal of the AND circuit G ₇₀ and one input terminal of the NAND circuit G ₆₆ and the AND circuit G ₆₉ , respectively, and one of the NAND circuit G ₅₄ is connected. It is connected to the other input end of the NAND circuit G ₅₅ through the input end and the knot circuit G ₅₃ , respectively. The output of the NAND circuit G ₅₂ are all of the output of the NAND circuit G ₄₈ or G ₅₁ is 'L' when the level 'H' level. That is, it is determined whether the average direct auto mode or the off mode or another photographing mode, and the output of the NAND circuit G ₅₂ becomes the “H” level only in the average direct auto mode or the off mode. Therefore, as a result, in the off mode, only the longest exposure time is restricted, and shooting is performed with the same photometric method as in the average direct auto mode. The output of the NAND circuit G ₅₂ is, as a bias switching signal S4, is input to an operational amplifier A ₂ (see FIG. 8), also serves to switch the bias current of the operational amplifier A ₂ in accordance with the photographing mode as described above .

The other input end of the NAND circuit G ₅₄ has a knot circuit G _28.
Connected to the output terminal of the (10 see FIG.), Direct photometry are adapted to the shutter control signal S17 is input by, also, one input terminal of the NAND circuit G _55,
It is connected to the output port O9 of the CPU 50 (see FIG. 7), and the shutter control signal S16 in each of the memory, manual, and spot modes is input. The output terminal of the NAND circuit G ₅₄ is a 3-input NAND circuit G _57.
Of the NAND circuit G ₅₅ , and the output terminal of the NAND circuit G ₅₅ is connected to the third input terminal of the NAND circuit G ₅₇ .
The first input terminal of the NAND circuit G ₅₇ is connected to the knot circuit G _57
56 through the RS flip-flop circuit RSF ₀ (first
(See FIG. 6), the inverted signal of the high-speed limiter signal T ₀ (see FIG. 18 (c)) that holds the'H 'level for about 500 μs after the trigger is opened is input. It has become so. This high speed limiter signal T ₀ is
This is a signal for determining the shortest shutter speed. That is,
Assuming that the average direct automatic mode or off mode is selected, the output of the NAND circuit G ₅₄ is a shutter control signal S17 by the direct photometric becomes 'H' level only during 'L' level. On the other hand, the NAND circuit G
_Since the output of ₅₅ is the “H” level regardless of the level of the shutter control signal S16 in the manual mode or the like, the output of the NAND circuit G _{57 is} as follows if the output of the knot circuit G ₅₆ is the “H” level. Regulated by the output of NAND circuit G ₅₄ ,
Only when the shutter control signal S17 is at the "H" level, it becomes the "H" level. In other words, the output terminal of the NAND circuit G ₅₇ has a shutter control signal S1 by direct photometry.
7 is output. Similarly, in the memory hold, manual mode, and spot mode, the control signal S16 is output to the output terminal of the NAND circuit G ₅₇ . Here, as shown in FIG. 18 (c), the high-speed limiter signal T ₀ is held at the “H” level for about 500 μs after the trigger is opened, so that the output of the NAND circuit G ₅₇ becomes the NAND circuit G _{57. 54} , G
Regardless of the output of ₅₅ , it becomes'H 'level during this period,
The trailing curtain holding magnet MG ₁ is never demagnetized.
That is, the shortest shutter speed is 1/200 due to the signal T ₀ .
Limited to 0 seconds.

One input end of the AND circuit G ₇₀ has a transistor G
_It is connected to the collector ₅₄ (see FIG. 14) so that the strobe power-on signal S14 is inputted. The output terminal of the AND circuit G ₇₀ is connected to the NAND circuit G _70.
One input end of _{60 and} the other input end of the NAND circuit G ₅₈ are connected through a knot circuit G ₅₉ . One input end of the NAND circuit G ₅₈ is connected to the output end of the NAND circuit G ₅₇ , and the other input end of the NAND circuit G ₆₀ is R
It is connected to the output terminal Q of the S flip-flop circuit RSF ₁ (see FIG. 16) and receives the strobe tuning time signal T3. This strobe tuning time signal T3 is a signal which maintains the'H 'level for 16 ms even after the trigger is opened, as shown in FIG. 18 (f). The output terminal of the NAND circuit G ₅₈ is connected to one input terminal of the NAND circuit G _61, the output terminal of the NAND circuit G ₆₀ is connected to the other input terminal of the NAND circuit G _61. Now, in the average direct auto mode or the off mode, when the power of the strobe is not turned on or the strobe is not attached to the camera 10, the strobe power-on signal S14 is at the “L” level, and therefore, The output terminal of the NAND circuit G ₆₁ outputs the same signal as the output signal of the NAND circuit G ₅₇ . Further, when the flash from this state power is mounted is turned on, it becomes strobe power-on signal S14 is 'H' level, the output terminal of the NAND circuit G _61, so that the flash synchronization speed signal T3 is output become. Therefore, the shutter speed is 1/60 second of the constant speed. In the shooting modes other than the average direct auto mode or the off mode, the output of the AND circuit G ₇₀ becomes the “L” level, and the strobe synchronization time signal T3 does not participate in the shutter control. By the way, as long as the power of the strobe is turned on, the shutter is always fired at the strobe synchronization time so that the strobe emits light at a high shutter speed of about 1/60 second or more. At times, a method in which the strobe is not used was adopted, but this method is against the photographer's intention to shoot, and this is to correct this. That is, in the conventional camera, when the subject is a bright high-speed shutter speed, there is almost no need to fire the strobe, so the strobe is not fired from the viewpoint of saving the power consumption of the strobe. In such a case, it may be inconvenient if the photographer intends to draw an image, which is inconvenient. Therefore, the shutter speed is forcibly set to the flash synchronization time and the strobe light is emitted.

The output terminal of the NAND circuit G ₆₁ is connected to the base of the magnet control transistor Q ₆₆ of the magnet drive circuit 56 through the resistor R ₉₁ . The magnet controlling transistor Q ₆₆ is formed of an NPN type transistor, the emitter of which is grounded and the collector of which is applied with the power supply voltage Vcc through the coil of the trailing blade holding magnet MG ₁ . As described above, the application of the power supply voltage Vcc is performed only when the power supply hold circuit 67 (see FIG. 11) holds the power supply. The output terminal of the NAND circuit G ₆₁ is, CPU 50 (FIG. 7 reference) is connected to the input port I12 of the input port I12 output of the circuit G ₆₁ is as exposed ends signal S13
It is designed to be input to. Furthermore, the NAND circuit G
The output terminal of ₆₁ is connected to the second input terminal of the NAND circuit G ₃₃ (see FIG. 13) through the delay circuit DL ₀ , and the output of the circuit G ₆₁ is delayed by the delay circuit DL ₀ for a predetermined time. , are input to the NAND circuit G ₃₃ as a power supply hold release signal S12. The delay circuit DL ₀ is provided because the shutter drive circuit 56 and the strobe control circuit 66 include the power supply hold circuit 67 (first
Power is supplied through the
If the exposure end signal S1 output from the NAND circuit G ₆₁
This is to prevent the strobe control circuit 66 from operating normally if the power supply hold circuit 67 is released in step 3, so that the strobe control circuit 66 may not operate normally.

As described above, the output terminal of the NAND circuit G ₅₁ is also connected to one input terminal of the NAND circuit G ₆₂ and one input terminal of the NAND circuit G ₆₄ through the knot circuit G ₆₃ . The other input end of the NAND circuit G ₆₂ is connected to the output end Q of the RS flip-flop circuit RSF ₂ (see FIG. 16) so that the auto limiter signal T2 can be input from the same circuit RSF _2. ing. This auto limiter signal T2 is 1 after the trigger is released, as shown in FIG. 18 (e).
It is a signal that holds the'H 'level for 20 s, and is a signal that regulates the maximum exposure time in the auto mode. The other input end of the NAND circuit G ₆₄ is connected to the output end Q of the RS flip-flop circuit RSF ₃ (see FIG. 16) so that the off-limiter signal T1 is input from the same circuit RSF _3. It has become. As shown in FIG. 18 (d), the off-limiter signal T1 is a signal that holds the'H 'level for 24 ms after opening the trigger, and is a signal that determines the shutter time in the off mode. The output terminal of the NAND circuit G ₆₂ is connected to one input terminal of the AND circuit G _65, the output terminal of the NAND circuit G ₆₄ is, the AND circuit G ₆₅
Is connected to the other input terminal of. The output terminal of the AND circuit G ₆₅ is connected to the base of the NPN transistor Q ₆₃ through the resistor R ₈₀ , the emitter of the transistor Q ₆₃ is grounded, and the collector is the transistor Q _66.
Connected to the base of. Now, when the output of the NAND circuit G ₅₁ is 'L' level, that is, when the off mode, the output of the NOT circuit G ₆₃ becomes 'H' level, the AND circuit G
An inverted signal of the off-limiter signal T1 is output to the output terminal of ₆₅ . Therefore, 24 ms after the trigger is opened, the transistor Q ₆₃ turns on, the transistor Q ₆₆ turns off regardless of the output of the NAND circuit G ₆₁ , the magnet MG ₁ is demagnetized, and the shutter is closed. Also, when other than the off-mode, the output terminal of the AND circuit G ₆₅ inverted signal of the auto limiter signal T2 is outputted. Therefore, after about 2 minutes have passed since the trigger was opened, the transistor G ₆₃
Turns on, and the shutter is forcibly closed in the same manner.

Next, the strobe control circuit 66 will be described. The PNP transistor Q ₆₄ has a base connected through a resistor R ₈₅ to RS.
It is connected to the output terminal Q of the flip-flop circuit RSF ₁ (see FIG. 16) and receives the strobe tuning time signal T3. The collector of the transistor Q ₆₄ is grounded, and the emitter is connected to the base of the PNP transistor Q ₆₅ through the resistor R ₈₆ . The base of transistor Q _65, through the resistor R ₈₇ is connected to the emitter of the transistor Q _65, the power supply voltage Vcc is applied to the emitter. Also,
The collector of the transistor Q ₆₅ is being grounded through a series circuit of resistors R _88, R _89, connection point of the resistors R _88, R ₈₉ is connected to the gate of the flash trigger thyristor SCR ₁ through the capacitor C ₈ Has been done. Thyristor S
The gate of CR ₁ is grounded through resistor R ₉₀ ,
The cathode is directly grounded. Also, thyristor SC
The anode of R ₁ is connected to the electric circuit of the strobe through the electric contact of the strobe mounting shoe 24 (see FIG. 2) or the connector 25 for connection (see FIG. 1), and the thyristor SCR ₁ At the time of firing, the strobe light emission signal S19 is transmitted to the strobe. Now, it is assumed that the shutter release button 11 (see FIGS. 1 and 2) is pressed after the strobe is attached to the camera 10 and the charging is completed. Then, about 16 ms after the shutter front curtain travels and the trigger is released, the strobe synchronization time signal T3 becomes "L" level, so that the transistor Q ₆₄ is turned on, the transistor Q ₆₅ is turned on, and the thyristor is turned on. SCR
_A pulse voltage is applied to the gate of ₁ through the capacitor C ₈ , and the thyristor SCR ₁ is turned on. Then, a trigger current flows as a strobe light emission signal S19 from the strobe through the thyristor SCR ₁ , and the strobe emits light.

On the other hand, one input end of the NAND circuit G ₆₈ is connected to the collector of the transistor Q ₅₄ (see FIG. 14) to receive the strobe power-on signal S14,
The other input end is connected to the output end of the knot circuit G ₂₈ (see FIG. 10), and the shutter control signal S17 by direct photometry is input. The output terminal of the NAND circuit G ₆₈ is the AND circuit G _68.
The other input terminal of _{69 and} the other input terminal of the NAND circuit G ₆₆ are connected via a knot circuit G ₆₇ , respectively. One of the input terminals of the NAND circuit G ₆₆ and the AND circuit G ₆₉ is
They are connected to the output terminals of the NAND circuit G ₅₂ , respectively. The output terminal of the NAND circuit G ₆₆ is connected to the base of the PNP transistor Q ₆₁ through the resistor R ₈₁ , and the output terminal of the AND circuit G ₆₉ is connected through the resistor R ₈₂ to the NPN transistor Q _62.
Connected to the base of. The power supply voltage Vcc is applied to the emitter of the transistor Q ₆₁ , and the collector is connected to the collector of the transistor Q ₆₂ through a series circuit of resistors R ₈₃ and R ₈₄ . The emitter of the transistor Q ₆₂ is grounded. The connection point of the resistors R ₈₃ and R ₈₄ is connected to the electric circuit of the strobe through the electric contact of the strobe attachment shoe 24 (see FIG. 2) or the connector 25 (see FIG. 1). The strobe dimming signal S18 is transmitted to the strobe. Now, in the average direct auto mode or the off mode, since the output of the NAND circuit G ₅₂ is at the “H” level, the gates of the NAND circuit G ₆₆ and the AND circuit G ₆₉ open, and the output terminal of the AND circuit G ₆₉ . Has
The output signal of the NAND circuit G ₆₈ is, the output terminal of the NAND circuit G _66, the inverted signal of the output of the NAND circuit G ₆₈ is outputted. When the strobe is attached to the camera 10 and the strobe photographing by the direct photometry is performed, the strobe power-on signal S14 is at the “H” level, so the NAND circuit G
An inverted signal of the shutter control signal S17 at the time of direct photometry is output to the output terminal of ₆₈ . Now, assume that the shutter release button 11 (see FIGS. 1 and 2) is pressed from this state, and the shutter front curtain travels to start exposure. While the exposure level does not reach the proper, the shutter control signal S17 is 'H' level, therefore, the output of the NAND circuit G ₆₆ becomes 'L' level, the output of the AND circuit G ₆₉ 'L' level. Therefore, the transistor G ₆₁ is turned on, the transistor Q ₆₂ is turned off, and the connection point between the resistors R ₈₃ and R ₈₄ is the resistor R _83.
The power source is electrically connected to the power source through the strobe, and the strobe light control signal S18 becomes the "H" level. Strobe occurs,
When the exposure light amount reaches an appropriate level, the shutter control signal S
17 is inverted to the'L 'level, the transistor Q ₆₁ is turned off, the transistor Q ₆₂ is turned on, and the strobe dimming signal S18 becomes the'L' level. As a result, the strobe light control circuit (not shown) is activated and the strobe emission is stopped. Incidentally, neither the camera 10 is the average direct automatic mode, when there is no off mode, the output of the NAND circuit G ₅₂ becomes 'L' level, the output of the NAND circuit G ₆₆ is 'H' level, the AND circuit G ₆₉ The output becomes the “L” level, the transistors Q ₆₁ and Q ₆₂ are both turned off, and the strobe dimming signal S18 has no influence on the strobe dimming circuit.

FIG. 16 shows a detailed electric circuit of the timer circuit 68. The timer circuit 68 is a circuit for generating various timer signals for controlling the camera 10 of the present invention, and is a clock pulse C having a basic frequency of 32.768 KHz.
27 connected in cascade based on K (see FIG. 18 (a))
The T-type flip-flop circuits TF _{0 to} TF ₂₆ and the selection circuit that selects or combines the outputs of the T-type flip-flop circuits TF _{0 to} TF ₂₆ to generate a desired timer signal, and the initial setting of the timer circuit 68. And a reset circuit for. The cascaded T-type flip-flop circuits TF _{0 to} TF ₂₆ form a binary counter, and each of the T-type flip-flop circuits TF _{0 to} T F.
A pulse of 2 ^{− (n + 1)} × 32.768 KHz (where n is an integer of 0 ≦ n ≦ 26 and corresponds to the subscript of the circuit TFn ⁾ is applied to the output terminals Q _{0 to} Q ₂₆ of F ₂₆ . The signal is output. on the other hand,
The data input terminal D of the D-type flip-flop circuit DF ₂ is
It is connected to the output terminal of the NAND circuit G ₃ (see FIG. 7) and receives the same memory mode detection signal as the signal input to the input port I6 of the CPU 50. Further, the clock input terminal CK of this D-type flip-flop circuit DF ₂
A clock pulse CK having a basic frequency of 32.768 KHz is input to the. Inverting output terminal of the D-type flip-flop circuit DF ₂ is connected to one input terminal of the NAND circuit G _79, the other input terminal of the NAND circuit G _79, a memory mode that is input to the input port I6 The detection signal is input. The D-type flip-flop circuit DF ₂ and the NAND circuit G ₇₉ form a well-known synchronous differentiating circuit,
From the moment when the data input terminal of the flip-flop circuit DF ₂ becomes the “H” level, a negative pulse synchronized with the clock pulse CK is generated at the output terminal of the NAND circuit G ₇₉ . Further, the data input terminal D of the D-type flip-flop circuit DF ₃
Is connected to the collector of the transistor Q ₃₂ (see FIG. 11) to receive the release signal S0, and the clock pulse CK is applied to the clock input terminal CK.
Is being applied. Inverting output terminal of the flip-flop circuit DF ₃ is connected to one input terminal of the NAND circuit G _80, and release signal S0 is applied to the other input terminal of the NAND circuit G _80, a flip-flop circuit DF ₃ The NAND circuit G ₈₀ forms a synchronous differentiating circuit like the circuits DF ₂ and G ₇₉ . Further, the data input terminal D of the D-type flip-flop circuit DF ₄ is connected to the output terminal of the knot circuit G ₁₀₁ via the knot circuit G _{90 so} that the inverted signal of the trigger signal S1 is input. Therefore, the clock pulse CK is applied to the clock input terminal CK. Inverting input terminal of the flip-flop circuit DF ₄ is connected to one input terminal of the NAND circuit G _81, to the other input terminal of the NAND circuit G _81, as inverted signal of the trigger signal S1 is applied Therefore, the flip-flop circuit DF ₄ and the NAND circuit G ₈₁ are connected to the above circuits DF ₂ , G _79.
Similarly, a synchronous differentiating circuit is formed. The three synchronous differentiating circuits are circuits for resetting the timer circuit 68, and when the memory mode is selected and the shutter is released (actually, the power hold circuit 67 is used).
When the exposure is started (when the trigger signal becomes the “L” level), a reset pulse is generated. The timer circuit 68 needs to give an instruction as to a reference time point from which the timer operation should be started. This is because the timer circuit 68 is reset by the reset pulse. NAND circuits G ₇₉ and G ₈₉ that output reset pulses
And an output end of the G ₈₁ is 3-input AND is connected to the input terminals of the circuit G _82, an output terminal of the AND circuit G _82, T-type flip-flop circuit TF ₀ through NOT circuits G ₉₁ ~
It is connected to each reset input of TF ₂₆ . The output terminal of the AND circuit G ₈₂ has RS flip-flop circuits RSF _{0 to} RSF ₃ , RSF ₆ , RSF ₇ forming a selection circuit.
Of the OR circuit G ₈₄ , and is also connected to one of the input terminals of the OR circuit G ₈₄ .

The set input terminal of the RS flip-flop circuit RSF ₀ is connected to the inverting output terminal of the T-type flip-flop circuit TF _3. Is connected, and as shown in FIG. 18 (c), the output terminal Q holds the'H 'level for 0.5 ms even after the trigger signal S1 is inverted to the'H' level. The high-speed limiter signal T ₀ is output so as to be inverted to the'L 'level later. The NAND circuit G ₈₃ is connected to the set input terminal S of the RS flip-flop circuit RSF _3.
Of the NAND circuit G ₈₃ is connected to the output terminal Q ₃ of the T-type flip-flop circuit TF ₈ and the other input terminal of the T-type flip-flop circuit TF ₇ is connected. The output terminal Q ₇ is connected. Therefore, the output terminal Q of the RS flip-flop circuit RSF ₃ is shown in FIG.
As shown in (d), even after the trigger signal S1 is inverted to the “H” level, the off-limiter signal T1 is maintained at the “H” level for 24 ms and then inverted to the “L” level.
Is output. Further, the set input terminal S of the RS flip-flop circuit RSF ₂ is connected to the inverting output terminal of the T-type flip-flop circuit TF _21. Is connected to the output terminal Q, and as shown in FIG. 18 (e), the trigger signal S1 is maintained at the “H” level for 120 s even after the trigger signal S1 is inverted to the “H” level. L '
An auto limiter signal T2 that is inverted to the level is output. Furthermore, the set input terminal S of the RS flip-flop circuit RSF ₁ is connected to the inverting output terminal of the T-type flip-flop circuit TF _8. Is connected to the output terminal Q, as shown in FIG. 18 (f), the trigger signal S1 maintains the “H” level for 16 ms even after the trigger signal S1 is inverted to the “H” level. A strobe tuning time signal T3 that is inverted to the "L" level is output. The inverting output terminal of the RS flip-flop circuit RSF ₁ is connected to the data input terminal D of the D-type flip-flop circuit DF ₅ and also to one input terminal of the NAND circuit G ₈₉ . The clock pulse CK is applied to the clock input terminal CK of the D-type flip-flop circuit DF ₅ , and the inverting output terminal of the circuit DF ₅ is connected to the other input terminal of the NAND circuit Q ₈₉ . The output terminal of the NAND circuit G ₈₉ is R
S is connected to the flip-flop circuit RSF ₄ of the set input terminal S, a reset input R of the RS flip-flop circuit RSF ₄ is connected to the output terminal of the OR circuit G _84. The other input terminal of the OR circuit G ₈₄ is an inverting output terminal of the T-type flip-flop circuit TF _15. It is connected to the. Therefore, from the reversing force end of the RS flip-flop circuit RSF ₄ , as shown in FIG. 18 (g), the strobe tuning time signal T3 is inverted to the'L 'level, and at the same time, turned to the'H' level. The strobe charge gate signal T4 that returns to the'L 'level after about 2 seconds is output. The output terminal of the 3-input NAND circuit G ₈₅ is connected to the set input terminal S of the RS flip-flop circuit RSF ₆ , and the T-type flip-flop circuit T ₈₅ is connected to each input terminal of the NAND circuit G _85.
F _8, the output terminals of the TF ₆ and TF ₅ Q _8, Q ₆ and Q ₅ are connected. Therefore, at the inverting output terminal of the RS flip-flop circuit RSF ₆ , as shown in FIG. 18 (h), a strobe for inverting it to the “H” level 22 ms after the trigger signal S1 is inverted to the “H” level. The under limiter signal T6 is output.
Furthermore, the set input terminal S of the RS flip-flop circuit RSF ₇ is connected to the inverting output terminal of the T-type flip-flop circuit TF _26. Is connected to the output terminal Q. Therefore, FIG.
As shown in, the memory limiter signal T7 that is inverted to the "H" level is output about 70 minutes after the trigger signal S1 is inverted to the "H" level. About 1 from the output terminal Q _{11 of} the T-type flip-flop circuit TF _11.
The blinking synchronization signal T8 close to 0 Hz is output.

FIG. 17 shows a detailed electric circuit of the D-A conversion circuit 58. The D-A conversion circuit 58 constitutes a successive approximation type A-D conversion circuit together with the comparator A ₁₂ (see FIG. 7) forming the second comparison circuit 59, and the brightness value signal S6 or the film sensitivity value SV. And analog value of aperture value AV (SV-AV) are converted into a digital signal,
It has a role of causing the CPU 50 to input. The DA converting circuit 58 is a known 8-bit ladder DA converting circuit, and includes 16 analog switches AS ₀ to AS ₇ , AS ₁₀ to.
It is composed of AS ₁₇ , eight knot circuits G _{150 to} G ₁₅₇ , 16 resistors R _{149 to} R ₁₅₇ and R _{160 to} R _166, and an operational amplifier A ₂₁ . The analog switches AS _{0 to} A
S _7, AS ₁₀ to the input terminal of the analog switch AS ₀ ~AS ₇ of half of ～AS _17, the reference voltage Vr1 are applied respectively, the remaining analog switches AS ₁₀ ~ half
A reference voltage Vr2 higher than the reference voltage Vr1 is applied to the input terminals of the AS ₁₇ . Further, one of the control input terminals of the analog switches AS _{0 to} AS _{7 and} the other control input terminal of the analog switches AS _{10 to} AS ₁₇ are connected to the CPU.
The bit signals b _{0 to} b ₇ are respectively applied from the output port O6 of 50, and the other control input ends of the analog switches AS _{0 to} AS ₇ and the analog switches AS _{10 to} AS.
An inverted signal of each of the bit signals b _{0 to} b ₇ is applied to one control input terminal of ₁₇ through knot circuits G _{150 to} G ₁₅₇ . Furthermore, the output terminals of the analog switches AS _{0 to} AS ₇ and the analog switches AS ₁₀ to
A pair of output terminals of AS ₁₇ are connected to each of the output terminals of AS ₁₇ , and are connected to one ends of resistors R _{150 to} R ₁₅₇ . The other ends of the resistors R _{150 to} R ₁₅₇ have resistors R ₁₄₉ ,
It is connected to each connection point of R _{160 to} R ₁₆₆ . That is, the other end of the resistor R ₁₅₀ is connected to the connection point between the resistors R ₁₄₉ and R _160, and the resistor R ₁₅₀
The other end of ₁₅₁ has a resistance R _{152 at} the connection point between the resistances R ₁₆₀ and R _161.
The other end of the resistor R ₁₆₁ and R ₁₆₂ is connected to the other end, the other end of the resistor R ₁₅₃ is connected to the resistors R ₁₆₂ and R ₁₆₃ , the other end of the resistor R ₁₅₄ is connected to the resistors R ₁₆₃ and R ₁₆₄ . The other end of the resistor R ₁₅₅ is a connection point between the resistors R ₁₆₄ and R ₁₆₅ , the other end of the resistor R ₁₅₆ is a connection point between the resistors R ₁₆₅ and R _166, and the other end of the resistor R ₁₅₇ is a resistor. It is connected to the connection point between R ₁₆₆ and the non-inverting input terminal of the operational amplifier A ₂₁ . The reference voltage Vr to one end of the resistor R ₁₄₉
1 is applied, and the resistance value of each resistor R _{149 to} R ₁₅₇ is
It is set to be twice the resistance value of each of the resistors R _{160 to} R ₁₆₆ . The operational amplifier A ₂₁ has an inverting input terminal connected to the output terminal to form a voltage follower circuit, and the output terminal thereof is connected to the inverting input terminal of the comparator A ₁₂ (see FIG. 7).

At the output terminal of the operational amplifier A ₂₁ , which is the output terminal of the D-A conversion circuit 58 configured as described above, depending on the value of each bit signal output from the CPU 50, An output voltage V _DA of Since the D-A conversion circuit 58 is already known and is not related to the gist of the present invention, detailed description of its operation is omitted here. The operation of the successive approximation type A-D conversion circuit which is a combination of the D-A conversion circuit 58 and the comparator A ₁₂ will be described in detail later in the description of the flowchart.

19 (A) and 19 (B) respectively show the electrode structure of the liquid crystal display plate forming the photographing information display device 39,
FIG. 19 (A) shows a pattern of a segment electrode for display,
FIG. 19 (B) shows the pattern of the back electrode opposed to the segment electrodes through the liquid crystal layer.
As will be described in detail later, the photographing information display device 39 employs a driving method of 1/3 duty and 1/3 bias, and the back electrodes are the first to third back electrodes RE ₁ to RE ₁ . It is divided into RE ₃ . Also, this first
~ The segment electrodes corresponding to the third back electrodes RE _{1 to} RE ₃ are connected by one signal line with a maximum of three as one set, and are connected by the same signal line as shown in FIG. The formed segment electrodes correspond only to the different back electrodes RE _{1 to} RE ₃ . Therefore, the segment electrodes include a first segment electrode group corresponding to the first back electrode RE ₁ and a second back electrode RE ₂
Can be divided into a second segment electrode group corresponding to and a third segment electrode group corresponding to the third back surface electrode RE ₃ . As the segment electrodes included in the first segment electrode group, horizontally long rectangular point display segment electrodes (upper side of the "OVER" electrode and the "LONG" electrode) which are linearly arranged in a row in the horizontal direction at the uppermost position. , And the “±” electrodes for correction display. As the segment electrodes included in the second segment electrode group, a horizontally long rectangular bar display segment electrode sequentially arranged in a straight line in the middle in the middle, "O
There are a VER ”electrode, a“ LONG ”electrode, a“ MEMO ”electrode, and a“ SPOT ”electrode. Further, as a third segment electrode group, a shutter time electrode of“ 1 ”to“ 2000 ”, this shutter time electrode Fixed point matching index electrode formed in the lower part of the circle in a circular and triangular shape, and "-" and "+" for overexposure and underexposure display at the time of stroboscopic photography provided at corresponding positions on the left and right of this fixed point matching index electrode. Electrode, "MANUAL", "AUTO",
There are electrodes for displaying each mode of "HIGH" and "SHDW". A total of 39 signal lines connecting 1 to 3 segment electrodes are provided, and each signal line is an output terminal of a level conversion circuit (see FIG. 23) described later.
Is connected to the connection point of the OS-type field effect transistor Q _106, Q _107, segment drive signal J0~J38 is adapted to be printed. On the other hand, the first to third back electrodes R
E _{1 to} RE ₃ are common signal output circuits (24th
MOS field-effect transistor Q ₁₀₀ is the output end of FIG _{see), Q 101, Q 102,} Q 103 and Q _104, are respectively connected to the connection point of Q _105, it is applied to the common signal H0~H2 . In addition, No signal line is connected to the liquid crystal display, but this mark is not displayed on the liquid crystal, but is displayed by the strobe charging completion display light emitting diode D ₁ (see FIG. 14). It is not necessary to connect the signal line for display. Further, the segment electrodes, the signal lines and the back electrodes RE _{1 to} RE ₃ are made of transparent electrodes, and the photographing information display device 39 is formed in a light transmissive type. Further, hereinafter, the segment electrode or the display region of liquid crystal that is colored corresponding to the segment electrode is simply referred to as a segment.

FIG. 21 is a detailed electrode circuit diagram of the liquid crystal drive circuit 61. The liquid crystal drive circuit 61 is a circuit for driving the liquid crystal display plate forming the photographing information display device 39 to color. JK flip-flop circuits JKF ₀ and JKF ₁
Refers to an input terminal J output Q of the circuit JKF ₁ circuit JKF _0, the inverted output terminal of the circuit JKF ₁ is connected to an input terminal J of the circuit JKF _0, the power supply voltage Vcc to the input terminal K
And a clock pulse CK are respectively applied to the clock input terminal T to form a known synchronous ternary counter, and each circuit JKF ₀ , JKF
Output A0, A1 _1, Figure 25, respectively (b), as shown in (c). In addition, the JK flip-flop circuit JKF
₂ , the input terminal J is the JK flip-flop circuit JKF
₁ is connected to the output terminal Q and the input terminal K is connected to the knot circuit G _199.
Is connected to the output terminal Q of the circuit JKF ₁ through the above, and a clock pulse CK is applied to the clock input terminal T to form a D-type flip-flop circuit. The D-type flip-flop circuit, the output A1 of the JK flip-flop circuit JKF _1, in the circuit delaying by one period of the clock pulse CK, the output A2 is as shown in Figure 25 (d). Furthermore, the JK flip-flop circuit J
The power source voltage Vcc is applied to the input terminals J and K of the KF ₃ , and the clock input terminal T is connected to the output terminal Q of the JK flip-flop circuit JKF ₂ to form a binary counter. Is obtained by dividing the output A2 of the circuit JKF ₂ by 1/2 as shown in FIG. 25 (e).

A display RAM (DRAM) 85 is a memory that is directly accessed by the CPU 50 through an address bus and a data bus, and each memory area of the DRAM 85,
There is a one-to-one correspondence with the display segment of the photographing information display device 39. Since the photographing information display device 39 is configured to have 102 display segments, a DRAM
In 85, 102 memory areas SEG _{0 to} SEG ₁₀₁ are secured, and these memory areas SEG _{0 to} SEG ₁₀₁ are secured.
The content of _{101 is} the signal combining circuit 100 from 102 output terminals.
It is designed to be output to.

The signal synthesizing circuit 100 includes the photographing information display device 39
In order to drive with / 3 duty and 1/3 bias, D
This is a circuit for outputting 102 signals output from the output end of the RAM 85 to 39 lines by time division as output signals K0 to K38. 1/3 duty / 1
By adopting the 3-bias driving method, the number of connection lines between the photographing information display device 39 and the liquid crystal driving circuit 61 is reduced. As shown in FIG. 22, a part of the signal synthesizing circuit 100 is basically composed of four NAND circuits and one exclusive-voir circuit as one unit, and a plurality of them are provided. ing. For example, the output A2 of the JK flip-flop circuit JKF ₂ is applied to one input end of the NAND circuit G ₂₀₀ , and the other input end is connected to the memory area SE from the DRAM 85.
A signal corresponding to the contents of G ₀ is applied. The output A1 of the JK flip-flop circuit JKF ₁ is applied to _one input end of the NAND circuit G ₂₀₁ , and the signal corresponding to the contents of the memory area SEG ₁ is applied from the DRAM 85 to the other input end. ing. Further, the output A0 of the JK flip-flop circuit JKF ₀ is applied to one input terminal of the NAND circuit G ₂₀₂ , and the signal corresponding to the contents of the memory area SEG ₂ is applied from the DRAM 85 to the other input terminal. ing. Each NAND circuit G ₂₀₀ ,
_201, the output end of the _202, 3 are connected respectively to the input terminals of the input NAND circuit G _209, an output terminal of the NAND circuit G ₂₀₉ is connected to one input terminal of the Exclusive O A circuit G ₂₁₂ . The JK flip-flop circuit JKF ₃ is connected to the other input end of the exclusive circuit G _212.
Output A3 is applied, and the signal K0 is output from the output end of the exclusive pore circuit G ₂₁₂ . This signal K0 is, for example, as shown in FIG. 25 (i), the signal output from the output terminal of the DRAM 85,
The signal is time-divided into 1/3. Similarly, the NAND circuits G _{203 to} G ₂₀₅ , the 3-input NAND circuit G _210, and the exclusive circuit G ₂₁₃ allow the DRAM 85 to operate.
A signal corresponding to the contents of the memory areas SEG _{3 to} SEG ₅ of 1 is time-divided into 1/3 and output as a signal K1,
The NAND circuits G _{206 to} G ₂₀₈ , the 3-input NAND circuit G _211, and the exclusive circuit G ₂₁₄ allow the DRAM 8 to operate.
5 Memory Area _SEG 6 _{~SEG 8} signal corresponding to the contents of the is output is divided at 1/3 two by a signal K2. Thus, the signals corresponding to the contents of the 102 memory areas SEG _{0 to} SEG ₁₀₁ of the DRAM 85 are
A total of 39 signals K0 to K38 are output. The signals K0 to K38 are supplied to the segment drive signals J0 to J3 through the level conversion circuit shown in FIG.
8 is converted and applied to the display segment of the photographing information display device 39. FIG. 25 (j) shows the waveform of the signal J0 as an example of the segment drive signal. The level conversion circuit is a knot circuit G
₂₂₅ , P-channel MOS type field effect transistor Q ₁₀₆
And n-channel MOS field effect transistor Q
It is composed of ₁₀₇ . At the input end of the knot circuit G ₂₂₅ ,
The signal Kn (n = 0 to 38) is applied, and the output terminals of the knot circuit G ₂₂₅ are connected to the gates of the transistors Q ₁₀₆ and Q ₁₀₇ , respectively. Transistor Q ₁₀₆
Sources constant voltage V ₀ is applied, the transistor Q ₁₀₇
Has a constant potential of −V ₀ . The drains of the transistors Q ₁₀₆ and Q ₁₀₇ are connected to each other, and the segment drive signal Jn (n = 0 to 3) is connected from this connection point.
8) is taken out. As many as the number of such level conversion circuit segment drive signals J0 to J38,
That is, it goes without saying that 39 pieces are provided.

FIG. 24 shows a common signal output circuit in the liquid crystal drive circuit 61. This common signal output circuit includes knot circuits G ₂₁₅ and G _{222 to} G ₂₂₄ and NAND circuits G _{216 to} G.
₂₂₁ and a P-channel MOS field effect transistor Q
₁₀₀ , ₁₀₂ , ₁₀₄ , n-channel MOS type field effect transistors Q ₁₀₁ , ₁₀₃ , ₁₀₅ , and resistors R ₂₀₀ to ₂₀₂ . JK is connected to one input terminal of the NAND circuit G _216.
The output A3 of the flip-flop circuit JKF ₃ is applied to the other input terminal of the JK flip-flop circuit J
The output A0 of KF ₀ is applied. The output terminal of the NAND circuit G ₂₁₆ is connected to the gate of the P-channel MOS-type field effect transistor Q _100. Moreover, to one input terminal of the NAND circuit G _217, and the inverted signal of the output A3 is applied through the NOT circuit G _215, to the other input terminal, the output A0 is applied. The output terminal of the NAND circuit G ₂₁₇ is connected to the n-channel MOS field effect transistor Q ₁₀₁ through the knot circuit G _222.
Is connected to the gate. A constant voltage + 2V ₀ is applied to the source of the transistor Q _{100, and} the source of the transistor Q ₁₀₁ has a constant potential of −2V ₀ .
The drain of the transistor Q _100, Q ₁₀₁ is be connected to each other, this connection point is grounded through a resistor R _200. The first common signal H0 is adapted to be taken out from a connection point between the drain of the transistor Q _100, Q _101. Further, in exactly the same manner, the circuit that outputs the second common signal H1 is the NAND circuit G ₂₁₈ ,
A circuit configured by G ₂₁₉ , a knot circuit G ₂₂₃ , transistors Q ₁₀₂ and Q ₁₀₃ and a resistor R ₂₀₁ , and outputting the third common signal H2 is a NAND circuit G ₂₂₀ , G ₂₂₁ , a knot circuit G 2.
₂₂₄ , transistors Q ₁₀₄ and Q _105, and a resistor R ₂₀₂ . The first to third common signals H0 to H
The waveform of No. 2 is as shown in FIGS. 25 (f) to 25 (h).

Next, the operation of the liquid crystal drive circuit 61 will be described with reference to the time charts of FIGS. 25 (a) to (m). As an example,
Segments SEG ₀ , SEG ₁ , SEG ₂ (hereinafter, DR
The display segments corresponding to the memory areas SEG _{0 to} SEG ₁₀₁ of the AM 85 are indicated by the same reference numerals as those of the memory areas. ), The segment SE
The operation when G ₀ and SEG ₂ are colored and the segment SEG ₁ is not colored will be described. Now segment SE
Since G ₀ and SEG ₂ develop color, the content of the corresponding memory area of the DRAM 85 is “1”. On the other hand, the content of the memory area corresponding to the segment SEG ₁ is “0”. The outputs A2, A1, A0 are the memory areas SEG ₀ ,
It serves as a gate signal for sequentially outputting signals corresponding to the contents of SEG ₁ and SEG ₂ to the output terminal of the NAND circuit G ₂₀₉ (see FIGS. 25 (b), (c) and (d)). The output A of the NAND circuit G _209, the output A3 and (Figure 25 (e) refer) and Exclusive O is A and is outputted from the output of the circuit G ₂₁₂ as a signal K0 (Figure 25 (i) refer). Signal K0
Is a NAND circuit G in a section where any of the common signals H0 to H2 (see FIGS. 25 (f), (g), and (h)) is at the “H” level.
If the output ₂₀₉ 'H' level becomes 'L' level, the output of the NAND circuit G ₂₀₉ becomes 'L' if the level 'H' level. The signal K0 is the common signal H.
When any of 0 to H2 is at the “L” level, it is at the “H” level if the output of the NAND circuit G ₂₀₉ is at the “H” level, and is “L” level if the output of the NAND circuit G ₂₀₉ is at the “L” level. It becomes L'level. Thus, if the output is 'H' level of the NAND circuit G _209, a potential difference between the segment drive signal J0 and the common signal H0~H2 described later by a 3V _0, the liquid crystal corresponding to the segment is colored. Also, if the output is 'L' level of the NAND circuit G _209, by the potential difference between the segment drive signal J0 and the common signal H0~H2 is V _0, the liquid crystal corresponding to the segment is not colored. Now segment SEG ₀ , SE
The content of the memory area of the DRAM 85 corresponding to G ₂ is “1”, and the DRAM 85 corresponding to the segment SEG ₁
Since the content of the memory area is 0, the waveform of the signal K0 is as shown in FIG. 25 (i). Therefore, the segment drive signal J0 after the level conversion is as shown in FIG. 25 (j). Therefore, the potential difference H0 to J0 between the common signal H0 and the segment drive signal J0 is as shown in FIG. 25 (k), and the segment SEG ₀ develops color at 1/3 duty. Further, the potential differences H1 to J0 between the common signal H1 and the segment drive signal J0 are shown in FIG.
As shown in (l), it always becomes V ₀ , and segment SEG ₁
Does not develop color. Further, the potential differences H2 to J0 between the common signal H2 and the segment drive signal J0 are as shown in FIG. 25 (m), and the segment SEG ₂ develops color at 1/3 duty. Other segments SEG _{3 to} SE
The color development of G ₁₀₁ is controlled in the same manner.
Needless to say, even if the segments are colored with 1/3 duty as described above, they appear to be continuously colored by the human eye. In addition, the memory area S
The subscripts of EG _{0 to} SEG ₁₀₁ are added for the purpose of explanation, and have no direct relation to the addresses of the memory areas SEG _{0 to} SEG ₁₀₁ .

Here, the correspondence relationship between the display segment and the address of the memory area of the DRAM 85 will be briefly described. As a general rule, the point display data is the DRAM 85 as it is.
Specify the address of the memory area of. For example, it is assumed that the leftmost segment (high-speed seconds) of the point display segment column corresponds to address 0 of the memory area of the DRAM 85. Every time one segment is moved to the right, the address of the memory area corresponding to that segment is 1
The address will increase. Now, assuming that the point display data is "4", by storing "1" at the address 4 of the memory area of the DRAM 85, the fifth segment from the leftmost end of the point display segment string is displayed in color. Become. The designation of this address can be set arbitrarily, and in the camera 10 of the present invention, as can be seen from the program described later, the leftmost segment corresponding to the higher order of the "OVER" segment in the point display segment sequence is set. At the address C41 of the memory area,
The rightmost segment corresponding to the upper part of the "ONG" segment is specified at the address C40 (= C41 + 35). In the program described later, the point display data and the bar display data are calculated using the same arithmetic expression. And
If you display the address as it is, it will be duplicated. In the case of bar display, this is the DR added by adding the constant in the display data.
This can be solved by shifting the address designation of the memory area of AM85, but the addition of the constant was not specified in the program.

FIG. 26 is a graph showing a counting method at shutter speed in the case of performing memory photographing. Actually, CP
This is performed by software inside the U50, and will be described in detail later, but here, a brief overview thereof will be given first. The memory mode counts the actual exposure time taken by direct photometry and controls the exposure based on this, but since the exposure amount is stored,
When the aperture or film sensitivity is changed during the memory mode shooting, it is necessary to change the stored value so that the exposure amount becomes constant accordingly. In this case, in the camera 10 of the present invention, the aperture value and the film sensitivity value are logarithmic compression information with an accuracy of the least significant bit (LSB) of 1/12 Ev, so the actual exposure time is also the aperture value. , It is necessary to convert the film speed value into the same series of numerical values. As a method for this, (1) after counting the actual exposure time with pulses of the same cycle, the LSB 1 / 12E
(2) The pulse period of the clock that is the reference for counting is changed with time, and the count value itself becomes a value equivalent to the time value of LSB 1/12 Ev (hereinafter referred to as the Tv value). There are two possible methods. The latter method is used in the camera 10 of the present invention. Strictly converting the actual exposure time into the Tv value, the control of the clock frequency becomes very complicated. Therefore, in the camera 10 of the present invention, the clock cycle is controlled to double each time the exposure time doubles. FIG. 26 shows
The relationship between the ideal curve A for converting the actual exposure time into the Tv value and the conversion curve B by the method adopted by the camera 10 of the present invention is shown. According to the method adopted by the camera 10 of the present invention, The error from the ideal curve A is only about 0.08 Ev at maximum including the quantization error, and it is possible to exhibit sufficient accuracy as a camera.

The digital exposure information introduction circuit 6 shown in FIG.
0 is the manual shutter speed and the correction value CV is CP
Although a circuit for inputting a digital amount as it is into U50, since it can be easily configured by using already known circuit means, detailed description and illustration are omitted here.
Similarly, detailed description and illustration of the reference voltage circuit 69 are omitted here.

The camera 10 of the present invention is configured as described above.

Next, before entering the description of the operation of the camera 10, the shooting mode of the camera 10 of the present invention will be briefly described. First, the shooting modes of the camera 10 are roughly classified into three basic shooting modes: an auto mode, a manual mode, and an off mode. The auto mode is a so-called automatic exposure shooting mode in which the brightness of the subject is measured to automatically determine the shutter speed, and is selected by associating the shooting mode switching operation knob 21 with the "AUTO" index. . This auto mode is further divided into an average direct auto mode, a spot auto mode, and a strobe auto mode. The average direct auto mode is a shooting mode that automatically closes the shutter when the subject light reflected from the film surface and the shutter curtain surface during exposure is averaged and the proper exposure is reached. The index of the memory command operation knob 13 is set to "M
It is possible to select the memory mode by associating with the “EMORY” index. When this memory mode is selected, the shutter speed at the time of shooting the first frame after selection is set to the camera 10
After that, as long as the memory mode is not cleared by associating the index of the memory command operation knob 13 with the "CLEAR" index, shooting is performed with the same exposure level for any number of frames. The spot auto mode is a shooting mode in which a plurality of subject parts are spot-metered before shooting, and the shutter is automatically operated to obtain the proper exposure using the average value of the brightness values of the respective subject parts. Yes, the spot input button 14 in the auto mode
The spot auto mode is selected by pressing, and at the same time, the spot photometric value is input and stored. In addition, as the spot photometric value, the photometric value of the object portion projected on a spot photometric index (not shown) provided in the finder so as to optically correspond to the above-described partial photometric photovoltaic element PD ₂ Is entered. In the spot auto mode, by pressing the highlight command button 15 or the shadow command button 16, it is possible to further select the highlight mode or the shadow mode. In the highlight mode, the shutter speed is determined and exposure control is performed so that the exposure is reduced by 21/3 Ev from the spot photometric value of the maximum brightness of the plurality of spot photometric values. Be done. In the shadow mode, the shutter speed is determined so that the exposure is higher by 2 2/3 Ev than the spot photometric value of the minimum luminance among the plurality of spot photometric values as a reference, and photographing is performed. further,
The strobe auto mode is a shooting mode selected when the strobe is attached to the strobe mounting shoe 24 in the auto mode or the strobe is connected to the connector 25 and the power of the strobe is turned on. Yes, the shutter is operated at 1/60 second, which is the flash synchronization time, and the flash is automatically adjusted with proper exposure.

The manual mode is a shooting mode in which the shutter is operated at the shutter time set by the manual shutter time setting ring 7, and is selected by making the shooting mode switching operation knob 21 correspond to the "MANUAL" index. To be done. This manual mode is divided into a normal manual mode, a spot manual mode, and a strobe manual mode. However, the three modes are the same in that the shutter is operated at the time of the manual shutter speed, only the display state of the photographing information display device 39 is different. The memory mode cannot be selected in the manual mode, and the highlight mode and the shadow mode can be selected in the spot manual mode.

The off mode is a shooting mode selected by associating the shooting mode switching operation knob 21 with the “OFF” index, and the subject is metered by average direct metering.
When the shutter time is shorter than 1/40 second, the shutter is closed at that shutter time, and when the shutter time is longer than 1/40 second, the shutter is forcibly closed at 1/40 second.

Next, the operation of the camera 10 and the program flow in the CPU 50 will be outlined with reference to the flowchart in FIG. First, when the power of the camera 10 is turned on, the CPU 50 and the interface are reset to the initial state, and then a branch to a predetermined program is performed according to the photographing mode of the camera 10. First, when the camera 10 is in the direct auto mode, the determination as to whether or not it is in the auto mode is YES (hereinafter, the branch direction of YES is indicated by Y in the flowchart), and whether the strobe power is on or not. No (hereinafter, the branching direction of the no is indicated by N on the flowchart) and the determination as to whether or not the spot mode is no is made.
Enter the program for direct auto mode. In addition, it is assumed that the memory mode is not currently selected. In this program, it is first determined whether or not the mode has been switched. If the mode has been switched, the display in the finder, the interface and the internal register of the CPU 50 are reset. Next, an average brightness value (hereinafter, brightness value is referred to as Bv value) by open metering, a calculated value of (film sensitivity value-aperture value) (hereinafter referred to as Sv-Av value), and a correction value (hereinafter, referred to as Sv-Av value). Cv value) is sequentially input, and thereafter, it is determined whether or not the memory is held. Memory hold refers to the state in which the actual exposure time by direct photometry has already been stored, and the state of a memory set that is in the same memory mode but in which the actual exposure time is not stored but only the memory mode is selected. To be distinguished. In the memory hold state, the average Bv value or the like used for the calculation of the Tv value is changed to the already held value, and then the Tv value is calculated. When the calculation of the Tv value is completed, the Tv value is displayed as a bar (see FIG. 45). Then, it is determined whether or not the shutter has been released. If the shutter has not been released, the process returns to the beginning of the flowchart through-and the loop is repeated until the shutter is released. Therefore, the latest proper shutter time (Tv value) is always displayed as a bar on the photographing information display device 39. When the shutter is released, it waits until the exposure starts in a loop by determining whether the trigger is open.When the trigger is open, if the memory mode is not set, the shutter is released when the integrated output by direct photometry reaches a predetermined level. Closes and the exposure ends.
If the memory mode is not set and the memory is not held, the actual exposure time is counted at the same time. Further, in the memory mode and the memory hold, the shutter speed is controlled based on the Tv value already stored. After the exposure is finished, the process returns to the beginning of the flowchart through-and the display for the next shooting is repeated.

If the camera 10 is in the spot auto mode, the determination as to whether or not it is the auto mode is YES, the determination as to whether or not the strobe power is ON is NO, and whether or not the spot mode is selected. Exit each judgment with yes,
Enter the program for spot auto mode. In this program, it is first judged whether or not there is a spot input, but since there was always a spot input when the spot mode was selected, first enter the program with spot input in spot auto mode, then It is determined whether or not the mode has just been switched. If the mode has been switched, the display in the finder, the interface and the internal register of the CPU 50 are reset. Next, the spot Bv value by open metering, Sv-A
After the v value is sequentially input and the Tv value is calculated, the Tv value is stored and displayed in points (see FIG. 48). Then, it is judged whether the mode is the highlight mode or the shadow mode. If it is not these modes, Cv
After inputting the value and adding the correction, after calculating the simple average of the Tv value, this is displayed as a bar (5th step).
(See Figure 0). Here, in the point display of the Tv value, the Cv value is not added, and in the bar display, the fact that the subject brightness is displayed is the point display in principle. This is because the Tv value conversion display of the appropriate level is displayed on the other hand, and on the other hand, since the bar display is the display of the actual exposure time level, this is displayed with the correction taken into consideration. After the average value is displayed on the bar, it is determined whether or not the release is performed. If the release is not performed, the program returns to the mode determination program through-and the determination as to whether or not there is a spot input is made again. In the second loop after spot input, the spot input state is canceled in the first loop, so
This time, enter the program without spot input. Here, first, the Sv-Av value is input, and the Tv value is calculated based on the plurality of stored spot Bv values,
The point display of each Tv value is changed. That is, since the storage by the spot input operation is only the storage of the exposure amount, the input point is changed so that the exposure amount is constant. Next, it is judged whether the mode is the highlight mode or the shadow mode. If not, the Cv value is input, and then a simple average of the Tv values is calculated with the correction taken into consideration. Display the value in a bar (5th
(See Figure 0). Subsequently, the spot Bv value currently being measured is input, and this Bv value is converted into a Tv value that gives an appropriate exposure, and is displayed as points. This point display is performed by blinking display and is distinguished from the Tv value based on the already input Bv value. Next, it is judged whether or not the memory is held, and if it is the memory hold, it is judged whether or not it is the release. If not, whether or not it is the highlight mode and whether or not the shadow mode is set. Enter the decision. If it is neither the highlight mode nor the shadow mode, the process goes to the determination as to whether or not the release is set.

Next, the case where the spot auto mode is the highlight mode or the shadow mode will be described. Now
If the spot input operation is performed and the point display of the Tv value is finished, then in the highlight mode or the shadow mode, the bar display is not changed, and the program is branched again to the mode determination program by the shutter release determination. . Then, when the spot input is judged again,
This time, enter the program without spot input, shift the point display so that the exposure amount is constant,
Then, the highlight mode or the shadow mode is discriminated. Since it is in highlight mode or shadow mode now, the bar display is not shifted,
After the point display of the current photometric value is performed, if the memory is not held, it is next determined whether or not the highlight mode is set. If it is the highlight mode, the Tv value that exceeds the maximum brightness value of the plurality of brightness values stored by the spot input operation by 21/3 Ev is displayed in a bar (see FIG. 52). At the time of this bar display, the tip of the bar display once corresponds to the maximum brightness value so that the photographer can clearly know which photometric point is the 21/3 Ev over trap. It extends to the value (see Fig. 51), after which the 21/3 Ev over stops at that point (see Fig. 52). On the other hand, if in the shadow mode, the Tv value that is 2 2/3 Ev under the lowest luminance value among the plurality of luminance values stored by the spot input operation is displayed in a bar (see FIG. 56).
Even in this case, the tip of the bar display once returns to the Tv value corresponding to the lowest luminance value (see FIG. 55), and thereafter, 2 @ 2/3 Ev under stops from that point (see FIG. 56).

Then, in the spot auto mode, when the shutter is released, it waits until the exposure starts by looping to determine whether the trigger has opened, and when the trigger opens, the bar set in the timer counter is set. The exposure time is measured based on the exposure time information corresponding to the display information. And
When the timer counter value reaches a predetermined value, the shutter is closed and the exposure is completed. After this, the program returns to the mode determination program again via the-. Next, the case where the direct auto mode and the memory mode are set will be described. Now, it is assumed that the memory is not held. Then, the determination as to whether or not it is the auto mode is YES, and the determination as to whether or not the strobe power is ON is NO,
If the determination of direct auto and memory hold is NO, the determination of whether or not it is the spot mode is NO, and the program of the direct auto mode is entered. Then, the Tv value bar display is performed in exactly the same manner as in the normal direct auto mode before release (see FIG. 57). When the shutter is released, after waiting until the trigger is opened, the memory hold determination is returned to NO, so that the actual exposure time in the direct auto mode is counted and at the same time, the apex value is changed. After this, when the exposure is completed, the program branches again to the mode determination program. Here, if the memory mode is not released, the memory hold state is automatically set. In the memory hold state, the bar display and the "MEMO" display blink at a low speed (58th display).
See figure). As a result, it is possible to positively indicate to the photographer that the photographing mode is the memory mode, and to reduce the risk of photographing in the wrong mode. Then, the determination of the direct auto mode and the memory hold state is answered in the affirmative, and the step of inputting the Sv-Av value and the Cv value is entered without inputting a new average Bv value. Here, since it is the exposure amount storage of the memory hold that a new average Bv value is not input, the Bv value has already been input and stored, and the Sv-Av value and C
This is because only the v value information needs to be input. When the input of the Cv value is completed, it is determined whether or not the memory is held. Since the memory is held now, the Sv-Av value and Cv at the time of the memory hold by direct photometry are determined.
When there is a change in the current Sv-Av value and Cv value from the value, the bar display is changed accordingly. This is because the memory hold stores the exposure amount, not the exposure time. Next, when the shutter is released, since the memory is held, the exposure control based on the memory photographing information is performed by the timer counter in which the value corresponding to the bar display information is set. In other words, shooting is performed at the same level as the exposure amount during direct photometry shooting before memory hold. Since the bar display shifts according to the Cv value, the exposure amount can be corrected, and it cannot be said that the exposure amount is memorized in the strict sense. There is a possibility that it may be mistaken that the camera 10 does not change because of a failure, so correction is possible even in the memory mode.

Next, memory shooting in the spot auto mode will be described. In this case, the spot input operation becomes invalid,
The program branches directly to the flow without spot input in spot auto mode. Also, the highlight standard T
The v value bar display and the shadow-based Tv value bar display are not performed. The flow of the other programs is almost the same as that described in the spot auto mode. In the memory hold state in the spot mode, the "MEMO" display, the input point display, and the bar display blink at a low speed, and the point display of the current photometric value blinks at a faster normal speed. The exposure control is performed based on the bar display data.

Next, flash photography in the auto mode will be described. When the power of the flash is turned on in the auto mode, the exposure is automatically controlled by direct metering. First, the program leaves the determination as to whether or not it is the auto mode with YES and the determination as to whether or not the strobe power is on with YES, and enters the flow for the strobe auto mode. Then, first, it is judged whether or not it is immediately after the mode switching, and if it is immediately after the switching, after initializing the display in the finder, the average Bv value, Sv-Av value, C
Each v value is input. Next, this average Bv value, S
The Tv value is subjected to an apex operation from the v-Av value and the Cv value. Here, the display in the viewfinder at the time of shooting with a flash is a display of "60" at the flash synchronization time and a display of a fixed point index (see FIG. 68). That is, the point display of the deviation with respect to the exposure level of 1/60 second at shutter speed is performed. Next, it is determined whether the flash photography is overexposed or underexposed, and overexposed, underexposed or proper is displayed. This display is performed only for 2 seconds after the strobe light is emitted, and the "+" mark blinks when the exposure is overexposed and the "-" mark blinks when the exposure is underexposed (see FIGS. 70 and 71). If neither is the case, the fixed-point index “▲” is made to blink due to proper exposure (see FIG. 73). It should be noted that the fixed-point index “▲” is simply continuously displayed during normal operation other than 2 seconds after strobe light emission. next,
It is determined whether or not the shutter is released. If the shutter is not released, the program returns to the mode determination program. If the shutter is released, a loop is made to determine whether the trigger is opened and the exposure is started. Then, when the trigger is opened, the integration by direct photometry is started, and the strobe light is emitted when the shutter is fully opened. The exposure control and strobe control by the direct photometry are performed by hardware as described above.

In the mode discriminating program, if it is not the automatic mode, it is next determined whether or not it is the manual mode. If it is not the manual mode, it is the off mode. Branch to. In the off mode, all the display in the finder is erased to prevent power consumption, and the program returns to the mode determination program through the-. When the shutter is released, the exposure control by direct photometry is performed within the range where the longest exposure time is limited as described above. This exposure control is performed by hardware, not by the program of the CPU 50.

Next, when the manual mode is selected, it is subsequently determined whether or not the power of the strobe is turned on. Now, when the power of the strobe is not turned on, it is next determined whether or not it is the spot mode. If it is not the spot mode, the program branches to the flow of the normal manual mode. Here, first, it is determined whether or not the mode has been switched immediately.
Initialization of variables and initialization of display are performed. Then, the manual data corresponding to the manually set second is input to display the manual shutter time. FIG. 61 shows a state in which the shutter speed is set to 1/60 second. Next, the average Bv value, S
The v-Av value and the Cv value are sequentially input, and the deviation amount (hereinafter referred to as deviation) from the standard exposure level is calculated from the manual data, the average Bv value, the Sv-Av value and the Cv value, and this is displayed in a bar. (See FIG. 61). Then, it is determined whether or not the shutter is released,
If it is not released, the program returns to the mode determination program again. If it is released, the trigger open determination loop waits until the exposure starts. Then, when the trigger opening is opened, the exposure time is counted based on the manual data set in the timer counter, and when the value of the timer counter reaches a predetermined value, the exposure is terminated and the program branches again to the mode determination program.

When the spot mode is selected in the spot mode determination, it is the spot manual mode, and the flow branches to the spot manual mode flow. Here, first, it is determined whether or not the spot input operation is performed. However, in the first program flow after selecting the spot mode, the spot input is always performed at the same time. Is determined. Immediately after switching the mode, the variables are reset, the display is reset, and the interface is reset. Next, the manual data corresponding to the manually set time is input and the manual shutter time is displayed (see the display of "125" in FIG. 63). Then, the spot Bv value and Sv-Av value are sequentially input, and the manual data, Bv value, and Sv-
The deviation from the Av value and the standard exposure level is calculated and stored, and this is displayed in points (see FIG. 63). Next, it is determined whether the mode is the highlight mode or the shadow mode. In either mode, it is directly determined whether or not the release mode is set. If it is not in any mode, the Cv value is input, the deviation of the simple average value of the stored spot input values from the standard exposure level is calculated, and this is displayed as a bar (see FIG. 63). Next, it is determined whether or not the shutter is released. If not released, the program returns to the mode determination program. And
When the spot input is determined again, unless the spot mode is released during this period, the flow branches to the spot input-less flow. Here, first, the manual data is input and the manual shutter speed is displayed. Next, after inputting the Sv-Av value, Sv-
The point display is changed so that the exposure amount becomes constant according to the change amount of the Av value. Then, it is determined whether the mode is the highlight mode or the shadow mode. If neither, the Cv value is input, and then the Sv-Av
The bar display is changed so that the exposure amount becomes constant according to the change amount of the value and the Cv value. Here, in the point display,
The Cv value is not added, and the Cv value is added to the bar display. As with the description of the auto mode, the point display is basically the subject brightness display, but in reality, the deviation from the standard exposure level is displayed based on the subject brightness at the time of spot input. is doing. On the other hand, since the bar display is an index of the actual exposure level, the Cv value is added. Next, after inputting the spot Bv value, this Bv value and Sv-Av
The deviation of the standard exposure level from the value is displayed as a point. Since this display is a display of the current photometric point, it is a blinking display in order to distinguish it from the already input point (see FIG. 63). Now, assuming that neither the highlight mode nor the shadow mode is set, it is next determined whether or not the release is performed. If not, the process returns to the mode determination program. Figure 64 shows
FIG. 65 shows a state in which the deviation of the simple average value of the input points is displayed in a bar, and FIG. 65 shows a state in which the correction is input.

Next, the case where the highlight mode or the shadow mode is selected in the spot manual mode will be described. When the spot mode is selected but the spot input operation is not performed, the highlight mode or the shadow mode is determined after the spot input point display is changed as described above.
If it is now in highlight mode, the bar display for the simple average of spot input values is not changed, and as described above, after the blinking display of the current photometry point, it is determined whether or not it is in highlight mode. To do. Since it is now in the highlight mode, 21/3 Ev minus the crocodile bar display from the minimum brightness value of the multi-point input points is displayed (see FIG. 66). In this case, like the display in auto mode, the tip of the bar display is once extended to the minimum brightness value to inform the photographer of which spot input point is the 21 / 3Ev minus trap, and then multipoint input is performed. Change the bar display to 21/3 Ev minus side from the minimum brightness value of the point. Next, it is determined whether or not the release has been performed. If not released, the process branches again to the mode determination program.

Next, the case where the shadow mode is selected will be described. The procedure up to the blinking display of the current metering point is the same as in the highlight mode, so the program after that will be described. Since it is now in the shadow mode, a plus bar is displayed by 21/3 Ev above the minimum luminance value of the multipoint input points (see FIG. 67). in this case,
The tip of the bar display once retreats to the minimum brightness value, and then the bar display extends by 21/3 Ev plus alligator from the minimum brightness value. Next, it is determined whether or not the release is performed, and if it is not released, the program returns to the mode determination program again.

In the spot mode, when the shutter is released, it is determined whether the trigger is opened next. If the trigger is opened, the exposure time is measured based on the manual data set in the timer counter and the timer counter is set to The exposure ends when the value is reached. After the exposure is completed, the program returns to the mode discrimination program.

Next, the case where the power of the strobe is turned on in the manual mode will be described. Now, when the power of the strobe is turned on and the strobe manual photographing is performed, it is first determined whether or not the mode has been switched, and if the mode has been switched, the display is reset. The display of "MENU" and the display of the fixed point index shown in FIG. 73 correspond to this. Next, after the manual data is input, the shutter speed is displayed. FIG. 73 shows a state in which 1/30 second is set as the manual shutter time. Subsequently, the average Bv value, the Sv-Av value, and the Cv value are input in this order, the deviation from the standard exposure level is calculated from these values, and this is displayed in points (see FIG. 73). Next, it is determined whether or not the release is performed, and if it is not released, the process branches to the mode determination program. In the auto mode or the off mode, in flash photography, the shutter speed is all the flash synchronization time, but in manual photography, the shutter is controlled at the manually set shutter time.

Next, the operation of the camera 10 of the present invention will be described with reference to FIGS.
Referring to the detailed flowchart of the figure, the CPU 50
It will be described together with the flow of the program in. First, the second
Turn on the power as shown in FIG. This is equivalent to storing a battery having an electromotive force and a capacity higher than the specified voltage in the battery storage chamber of the camera 10. Next, the display is cleared. This corresponds to setting all the contents of the DRAM 85 to "0". It also resets the interface. Here, a positive pulse is output to the output ports O _{0 to} O ₃ , the spot mode detection flip-flop circuits (G ₇ , G ₉ ), the spot input detection flip-flop circuits (G ₁₁ , G ₁₂ ), and the highlight. The flip-flop circuits for mode detection (G ₁₅ , G ₁₅ ) and the shadow mode detection flip-flops (G ₁₉ , G ₂₀ ) are reset. Thus, the input port _I 2 ~I ₅ becomes '0'. Next, the variables are reset. Here, first, the contents of the flag M10 (M1
Set 0) to '1'. This flag M10 is a memory hold detection flag, and (M10) = 0 indicates a memory hold state. Next, the shooting mode detection flag M13
The off mode constant C22 is stored in. The shooting mode detection flag M13 is set with a constant corresponding to each shooting mode, and is used in pair with the same shooting mode detection flag M12 to determine whether or not the shooting mode has been changed immediately. Then, "0" is stored in the detection flag M17 immediately after the highlight input. The flag M17 immediately after the highlight input is a flag for determining whether or not it is immediately after the highlight input. Next, "0" is stored in the detection flag M18 immediately after the shadow input. The post-shadow input detection flag M18 is a detection flag indicating whether or not the shadow has just been input. As described above, in highlight-based shooting or shadow-based shooting, immediately after the mode is selected, the bar display tip extends to the maximum brightness value or minimum brightness value of the input point, and then the predetermined exposure level is reached. The bar display is set. Therefore, once highlight mode or shadow mode is selected, when shifting the bar display with respect to the spot input point input after that, it is only necessary to change the bar display to the predetermined exposure level and to obtain the maximum brightness. The operation of resetting the bar display to the value or the minimum brightness value is not performed. Therefore, it is necessary to determine whether or not it is immediately after the highlight input and the shadow input. The detection flag M17 immediately after the highlight input and the detection flag M18 immediately after the shadow input are flags for this detection. Then, "1" is stored in the blinking display flag M22. The blinking display flag M22 is a flag for performing the blinking display, and by reversing the sign of the flag M22, the display is performed or erased so that the blinking display is performed. .

In this way, when the initialization is performed after the power is turned on, it is subsequently determined whether or not the input port I0 is "1" and whether or not the automatic mode is set. Now, assuming that I0 = 1, that is, if the auto mode is selected, it is next determined whether or not the input port I13 is "1". The input port I13 has I13 = 1 when the power of the strobe is turned on, but it is assumed that the power of the strobe is not turned on and I13 = 0. Then, it is next detected whether or not the memory mode detection input port I6 is "1". This input port I6 is I6 = 1 when in the memory mode.
Becomes No memory mode is currently selected, and I6
= 0. Next, the content of the memory hold detection flag M10 is set to "1". This is performed to reset the contents of the flag M10 because the memory hold state is not in progress. Then, the display of "MEMO" is cleared. This is performed by setting the content of the memory area of the DRAM 85 corresponding to the "MEMO" segment to "0". Next, the non-memory constant C26 is stored in the memory mode detection flag M11. This non-memory constant C26 is a constant C20-24, C3 described later.
It is a constant having a value different from 0 and C31. Next, it is determined whether the content (M11) of the flag M11 is the same as the average direct auto mode constant C21. As mentioned above, there are two types of memory modes: average direct auto memory, which controls exposure by direct photometry in auto mode, and strobe auto memory, which controls exposure by spot photometry in auto mode. In the average direct auto mode, the memory mode detection flag M11 stores the average direct auto mode constant C21. In the spot auto memory mode, the memory mode detection flag M11 stores the spot auto mode constant. C20 is stored. Since neither is present, it is next determined whether or not the spot mode detection input port I2 is "1". In the spot mode, I2 = 1, but if it is not in the spot mode, the shooting mode becomes the average direct auto mode, and the program goes through-to the flow for the average direct auto mode shown in FIG. Branch off. Here, first, the average direct auto mode constant C21 is stored in the shooting mode detection flag M12. Next, the content (M13) of the shooting mode detection flag M13 is the off mode constant C22.
Or not. Since a constant C22 is set in the flag M13 when the variable is reset immediately after the power is turned on, if the flow of the program is the first time immediately after the power is turned on, the variable is reset next. . If (M13) = C22 is not satisfied, then it is determined whether or not the contents (M12) and (M13) of the shooting mode detection flags M12 and M13 are equal to each other, and (M13) = (M12). ) Is not
Immediately after the change from the other shooting mode to the average direct auto mode, the variables are reset next. When (M13) = (M12), since the program flow is the first and subsequent times after switching to the average direct auto mode, it is not necessary to reset variables and display, and these resets are not performed. Now, suppose that it was the first program flow after changing to the average direct auto mode. At this time, the bar display start point is initially set as a variable reset. This is performed by storing the address of the memory area of the DRAM 85 corresponding to the rightmost end of the bar display segment shown in FIG. 19A in the bar display start address storage area M14. In the bar display immediately after changing the mode, the segment display starts from the rightmost segment, and the photographer is actively informed that shooting in the new mode has started.Therefore, it is necessary to specify the start point for this. Because there is. Next, the display is reset. Here, the "AUTO" segment and "LONG" shown in FIG. 45,
"1" is stored in the memory area of the DRAM 85 corresponding to each segment of "1" to "2000" and "OVER", and all the memory areas of the other DRAMs 85 are set to "0".

Next, the content (M12) of the shooting mode detection flag M12 is transferred to the shooting mode detection flag M13, and the shooting mode is stored. Therefore, in the flow of the program from the second time onward, (M13) = (M12) is always satisfied, and the variables are not reset and the display is not reset. Next, it is determined whether or not the content (M10) of the memory hold detection flag M10 is "0". Now
Since it is not in the memory hold state, the content (M10) of the flag M10 is "1". Therefore, (M10)
The content of = 0 is skipped with no (N), and then the average B input from the input port I7 is input to the average Bv value storage area M0.
The v value BV1 is stored.

Here, how the average Bv value of the analog signal output from the head amplifier circuit 51 is converted into a digital value will be described. First, the CPU 50 sets the output port O4 to "1" to specify that the average Bv value is input. Next, set output port O5 to "1" and set B
Specifies that the input is a v-value. By the way, A-D
The relationship between the contents of the converted analog signal S8 and the signals S3 and S7 output from the output ports O4 and O5 is that when the signals S3 and S7 are "1" and "1", the signal S8 has an average Bv value of "1". Spot Bv value when ',' 0 ',
When the value is "0" or "1", the Sv-Av value is set, and when the value is "0" or "0", the signal input is prohibited. Since the signals S3 and S7 are now "1" and "1", the A / D-converted analog signal S8 has an average Bv value. Before the A-D conversion is started, all the inputs of the D-A conversion circuit 58 shown in FIG. 17 are "0". Comparison with A-D conversion start, to only the most significant bit _{b 7} '1' First, then, the voltage V _AG of the output voltage V _DA and the A-D converter analog signal S8 of the DA converter 58 To do. Now, if V _AG ≧ V _DA , the output of the comparator A ₁₂ becomes “1”. CPU50
With the next A-D conversion signal input port I7 is left to '1' if the most significant bit b ₇ '1', A
Set "1" to the most significant bit of the register that stores the D conversion result. If V _AG <V _DA , the most significant bit b _{7 is set} to “0” and the most significant bit of the register that stores the AD conversion result is set to “0”. By repeating the above operations until _b 7 ~b _0, finally A-
A digital value corresponding to the average Bv value is stored in the register that stores the D conversion result. Next, the digital value corresponding to this average Bv value is temporarily stored in the accumulator (AC
C) Stored at address M0 via 79. Note that the spot Bv value and Sv-Av value A-D, which will be described later,
The conversion is done in exactly the same way.

Returning to FIG. 29 again, when the average Bv value is stored in the average Bv value storage area M0, next, (M10) = 0 again.
Since it is not in the memory hold state, the Sv-Av value SV- is stored in the Sv-Av value storage area M1.
Store the AV. Then, the determination of (M10) = 0 is performed again, and since the memory hold state is not established, the Cv value CV from the input port I9 is stored in the Cv value storage area M2. Then, it is determined whether or not (M2) = 0, and when there is no correction input, (M2) = 0, so the display of the '±' segment is erased, and when there is correction input, (M2) = Since it is not 0, the '±' segment is displayed. Next, it is again judged whether or not the memory is held by the judgment of (M10) = 0. Since the memory is not held now, the calculation of the Tv value is started.
First, after adding the average Bv value (M0) and the Sv-Av value (M1), the added value is reduced to ¼. This is the Bv value,
This is because the Sv-Av value is stored with the resolution of LSB 1/12 Ev, while the display is performed in the unit of 1/3 Ev. Next, the Cv value (M2) is added. Cv value is L
Since it is input with a resolution of SB1 / 3Ev, no correction is necessary. Next, after adding the constant C2 to perform level correction, the calculated result value is displayed in the bar display data storage area M3.
Store at. Next, while there are 34 bar display segments and the displayable range is only 111/3 Ev, the calculation result value stored in the area M3 is about 0-2.
Since it becomes 0 Ev, it is necessary to judge whether or not it is within the displayable range. Therefore, next, the calculation result value (M3)
Is converted into display data, a data conversion subroutine f {(M3)} is executed.

The subroutine f {(M3)} is a function program for converting the value (M3) into display data, and is specifically shown by the flow chart shown in FIG.
Next, this flowchart will be described.

The constant C41 is the DR corresponding to the "OVER" segment.
It is a constant indicating the address of the memory area of AM85. (M
3) When C41, the Tv values stored in the bar display data storage area M3 are all in the over area.
The content of area M3 is set to C41. Now, (M3) ≦ C
If not 41, the content (M3) of the area M3 is then compared with the constant C40. The constant C40 is a constant indicating the address of the memory area of the DRAM 85 corresponding to the "LONG" segment. When (M3) ≧ C40, area M
Since the Tv values stored in 3 are all in the under area, the content (M3) of area M3 is set to C40. if,
If C41 <(M3) <C40, it means that the Tv value is within the area where the bar can be displayed, and the subroutine f {(M3)} is finished as it is. After this, subroutine f
{(M3)} returns to the original program.

Returning again to the program of the average direct auto mode in FIG. 29, and when the subroutine f {(M3)} is completed, a delay instruction (interval instruction) of a predetermined time next
After executing, the process starts to judge whether the release signal input port I10 is "1". Here, the role of the interval command is particularly important in memory photography, so
I will explain it in the explanation. The input port I10 indicates that it has been released with "1", but if it has not been released, then bar display is performed based on the bar display data (M3). This bar display is performed by the bar display subroutine shown in FIG. Since there are various kinds of bar display methods depending on each photographing mode, the program of the bar display subroutine will be described after the entire program has been described, and only the bar display mode will be described until then. Now, when C41 <(M3) <C40, the 45th
The display as shown in the figure is made. In this case, in the first program flow immediately after the mode change, the bar display sequentially develops colors from the rightmost segment, and in FIG. 45, corresponds to the "15" segment indicating the shutter speed 1/15 second. Stop at the position you want. In the second and subsequent program flows immediately after the mode change, the bar display starts from the tip of the previous bar display and stops at a predetermined display position. If (M3) = C41, as shown in FIG. 46, the bar display extends to the leftmost end, and "OVER" is displayed.
The R "segment is displayed blinking. (M3) = C4
When it is 0, as shown in FIG. 47, no bar is displayed and only the "LONG" segment is displayed in blinking.

Next, assuming that the shutter is released in the program flow of the average direct auto mode, I10 = 1
The result of the determination is YES, and subsequently, it is determined whether or not the memory mode detection input port I6 is "1". The input end port I6 indicates a memory mode with "1", but since it is assumed that the memory mode is not selected at this time, the determination is negative and the exposure end signal input port I12 is subsequently determined. The input port I12 is a port to which the exposure end signal S13 is input, and is "1" until the trailing curtain holding magnet MG1 is demagnetized. Therefore, the program flow loops with the determination of I12 = 1 until the end of exposure. When the input port I12 turns to "0" and the exposure ends, the judgment I
Exit 12 = 1 with no. Then, the interval instruction for delay is executed. This interval instruction
For example, after storing a numerical value in a register, a subtraction instruction is executed by "1" and the execution is ended when the subtraction instruction reaches a predetermined value. It is necessary to perform photometry after the recoil reflection mirror 31 descends and the photometric optical system becomes stable. Tens of meters for the photometering optical system to stabilize,
Since s is required, an interval instruction is required. When this interval instruction is completed, next, output port O0
Output a positive pulse to each of O1. This is to automatically switch to the average shooting mode when shooting in the spot auto mode or the spot manual mode is completed. Next, the program returns to the mode discrimination program shown in FIG. Next, the flow of the program in the spot auto mode will be described. If the camera 10 is in the auto mode and the spot input button 14 (see FIG. 2) is pressed, the spot input switch SW ₈
(See FIG. 7) is closed, and the spot mode detection input end port I2 and the spot input detection input port I3 of the CPU 50 become "1", respectively. Therefore, in the auto mode, the spot auto mode is selected and the spot is input. Since the spot auto mode is the same as the average direct auto mode, it is the second mode.
In the mode discriminating program of FIG. 8, the average direct auto mode reaches the judgment of I2 = 1, which is branched through, and exits this judgment with YES this time, and then the content of the photographing mode detection flag M13 (M13) Whether or not it is equal to the spot manual mode constant C24 is determined. This determination is necessary because the following cases occur due to the configuration of the electric circuit of the camera 10. The manual mode includes a normal manual mode and a spot manual mode. In the spot manual mode,
Spot mode detecting input port I2 has become a '1', when changed to the auto mode by closing the auto switch SW ₄ from this state, to be changed directly spot automatic mode from the spot manual mode Become. Generally, when shooting in the spot mode, the frequency of shooting is relatively low compared to the overall shooting frequency, and it is appropriate to use the average direct auto mode or the normal manual mode unless a spot operation is performed. Therefore, in the camera 10 of the present invention, the average direct auto mode is switched when the manual mode is switched to the auto mode, and the normal manual mode is switched when the auto mode is switched to the manual mode. Immediately after the change from the spot manual mode to the automatic mode, the shooting mode detection flag M13 is set to the spot manual mode constant C24 at the beginning of a spot automatic mode program (see FIG. 35) described later.
Since it is set to, output ports O0, O
1 to send a pulse of '1', it resets the spot mode detection flip-flop circuit _(G 7, G _9), and a flip-flop circuit for spot input detection (G _11, G _12), an input port I2, I3 Is set to '0'. If it is not immediately after the change from the spot manual mode to the auto mold, then (M10) = 0 is determined. Now, since the memory hold state is not in effect, the content (M10) of the memory mold detection flag M10 is "1", and this determination is NO. Then I3 = 1
Is determined. Since the spot input detection input port I3 is now "1", that is, there is a spot input, the program passes through-
In the spot auto mode shown in the figure, the process branches to the flowchart with spot input. Here, first, Bv
The spot Bv value BV2 is stored in the value storage area M0. Spot A as a digital value after A-D conversion
The method for storing the v value BV2 in the area M0 is the average Bv.
This is as described in the description of storing the value BV1. Next, it is determined whether or not the value (M0) of the spot Bv value is smaller than a certain set value C1, and if (M0) ≧ C1, the constant C1 is transferred to the area M0. In general,
There is a limit to the subject brightness that can be measured by the photometry circuit, and weak light is particularly problematic. This is because as the brightness of the subject decreases, the photocurrent decreases, and errors due to leakage current and noise and errors due to loss of linearity of the logarithmic compression diode increase. Therefore, the spot Bv value (M0) becomes a small value although it is originally a large value indicating a low brightness, and when the exposure control is performed based on this value, a large error may occur. Therefore, when the spot Bv value (M0) is equal to or more than a certain photometric limit value C1, the spot Bv value (M0
0) is fixed to the limit value. Next, the spot auto mode constant C20 is stored in the shooting mode detection flag M12 to store the shooting mode.
Then, as in the case of the average direct auto mode, it is determined whether the power has just been turned on or the mode has been switched (M1
3) = C22 and (M13) = (M12), and if applicable, reset variables, reset display, reset interface. The contents of the shooting mode detection flag M13 (M
It goes without saying that the determination as to whether 13) is equal to the spot manual mode constant C24 may be performed here. Regarding the above-mentioned variable, that is, the reset of the internal register, the content of the overlap detection flag M5 is first set to "1" here. In spot mode, the calculation result of the current metering point is displayed in high-speed flashing, so if the display of the current metering point and the spot input point overlap, the display of the current metering point will take priority. Blinks. Overlap detection flag M
Reference numeral 5 is a detection flag for this purpose. This will be described later in detail. Next, the content of the highlight input detection flag M6 is set to "1". Further, the content of the shadow input detection flag M7 is set to "1". Both detection flags M
6, M7 is '1', indicating that neither highlight nor shadow mode is in effect. Then, the address of the bar display start segment is stored in the bar display start address storage area M14. As described above, the start segment of the bar display immediately after the mode change is the rightmost segment. Further, the contents of the spot input data number storage area M15 are set to "0". The area M15 is for counting and storing the number of spot input data. Next, the display is initialized. Here, as shown in FIG. 48, "SPOT", "LONG",
"OVER", "AUTO" and "1" to "200"
Each segment of 0 "is displayed. Since these displays are indispensable in the spot auto mode, they are displayed immediately after the mode is changed.
Initialize the interface. Here, the output port O2, O3 and outputs a pulse of '1', the highlight mode detecting flip-flop circuit (G _15, G ₁₆₎
And a shadow mode detection flip-flop circuit (G
₁₉ and G ₂₁ ) are reset. Also, output port O9
Is output to set the shutter control signal S16 to the energization waiting state.

Next, the spot auto mode constant C20 stored in the shooting mode detection flag M12 is transferred to the shooting mode detection flag M13. This will prevent the initial setting from being performed from the next program flow. continue,
The contents of the spot input data number storage area M15 are incremented by one. Next, the spot Bv value BV2 stored in the Bv value storage area M0 is transferred to the MBN address of the register. Here, N of the MBN address is the area M1.
An address corresponding to the contents of 5 is meant. Next, in the Sv-Av value storage area M1, the Sv-Av value (SV
Store AV). Then, the spot Bv value (M
0) and the Sv-Av value (M1) are added, and the result is ¼, and then the constant C2 is added and stored in the MTN address of the register. Here, N of MTN address is area M
An address corresponding to the contents of 15 is meant.
Further, the meaning of the above arithmetic expression is as described in the explanation of the average direct auto mode. Next, MTN
The subroutine f {(MT
N)} (see FIG. 43) is executed to convert the calculation result into display data and store it again at the MTN address. Next, the Tv value (MTN) of the spot input point is displayed as a point (see FIG. 48). At this stage, the bar display and the flashing display of the current photometry point have not been made yet. Then, a positive pulse is output to the output port O1.
In the spot mode, two flip-flop circuits, a spot mode detection flip-flop circuit (G ₇ , G ₉ ) and a spot input detection flip-flop circuit (G ₁₁ , G ₁₂ ) work, but when the sequence for spot input is completed. It is necessary to reset the spot input detection flip-flop circuits (G ₁₁ , G ₁₂ ) and wait for the spot input state again. This is the reason why a positive pulse is output to the output port O1. Next, it is determined whether the content (M6) of the highlight input detection flag M6 is "-1" and the content (M6) of the shadow input detection flag M7.
It is determined whether or not 7) is'-1 '. if,
If (M6) =-1 or (M7) =-1, the highlight mode or the shadow mode is set, and therefore, bar display is not performed by averaging the spot input data. Now, neither in the highlight mode nor in the shadow mode, (M6) ≠ -1 and (M7) ≠ -1
If so, then the program for displaying the bar by adding and averaging the spot input data is entered. Here, first, the spot Bv value (MBn) obtained by the spot input operation
Average value of (n = 1 to N) Is stored in the bar display data storage area M3. Next, the Cv value CV is stored in the Cv value storage area M2. Then, whether or not the correction operation is performed,
The determination is made by determining whether the correction value (M2) is '0'. If there is correction, the “±” segment is displayed (see FIG. 50), and if there is no correction, The display of the "±" segment is erased (see Fig. 48).
Then, the average value (M3) of the spot Bv values and Sv
-Av value (M1) and 4 times the Cv value 4 (M2)
And a constant C3 are stored in the shutter time storage area M8. Here, the reason why the Cv value (M2) is quadrupled and added together is to equalize the LSB weights. That is, Bv value (M3), Sv-Av value (M1)
LSB is 1/12 Ev, and LSB of Cv value (M2) is
Since it is 1/3 Ev, the Cv value (M2) is quadrupled to B
This is because the weights of the v value (M3) and the Sv-Av value (M1) are matched. Therefore, the contents of area M8 (M8)
Indicates shutter speed information for exposure control. After release, a value corresponding to the content (M8) is set in the timer counter to perform exposure control. This will be described later in detail. Next, after adding the Sv-Av value (M1) and the average value of the spot Bv values (M3) to 1/4, the Cv value (M2) and the constant C2 are added to store the bar display data. Store in area M3. Then, using the content (M3) of the area M3 as a variable, the subroutine f
After executing {(M3)} to convert the content (M3) into a Tv value for bar display, a subroutine for bar display is executed to display the Tv value (M3) in a bar (48th display).
See figure). Here, if the spot input is the first input, the bar display starts from the display of the rightmost segment,
If it is the second or later input, the segment is moved from the segment at the tip of the previous bar display to the segment at the desired position. If the Tv value (M3) after the bar display data conversion is equal to the constant C41, as shown in FIG.
At the same time the bar display extends to the leftmost segment,
The "OVER" segment is displayed blinking. When the Tv value (M3) after the bar display data conversion is equal to the constant C40, the bar display disappears and the "LONG" segment blinks. The details of the bar display will be described later.

If the bar display ends or if the determination at (M6) =-1 or (M7) =-1 is answered with YES, then whether or not the shutter is released is determined by the determination at I10 = 1. Judgment is made. Since the input port I10 is "0" when the release is not made, the determination I
Exit 10 = 1 with no, and return to the mode discrimination program of FIG. 28 again through-. Further, when the shutter is released, the program for exposure control in FIG. This program will be described later.

Next, even if the spot auto mode is the same, when no spot input is made, that is, when I2 = 1, I3 =
The flow of the program when 0 is described. In this case, in the mode discriminating program of FIG. 28,
The determination of I2 = 1 is answered by yes, the determination of I3 = 1 is answered by no, and the program branches to the program shown in FIG. 31 through-. Here, first, the Sv-Av value storage area M1
The Sv-Av value (SV-AV) is stored in. next,
The Sv-Av value (SV-AV) is stored in the Cv value storage area M1. Next, the Cv value C is stored in the Cv value storage area M2.
V is input. Needless to say, the spot Bv value is not input because the spot is not currently input. Then, (M2) = 0 is judged, and if there is a correction, the "±" segment is displayed (see FIG. 50).
If there is no correction, the “±” segment is deleted (4th
(See Figure 8). . Next, the spot input data for display (M
Tn) (n = 1 to N) are all erased. This is because the point display of the spot input data indicates that the subject brightness (spot Bv
Value) and the Sv-Av value at each time point, which is a point display of the Tv value. Therefore, according to the change of the Sv-Av value,
This is because it is necessary to change the point display. The spot Bv value by each spot input is stored in the individual register M.
As described above, the data is stored in Bn (n = 1 to N). Next, the Tv value for the spot Bv value stored in the register MBn (n = 1 to N) is set to 1/4 {(M1) +
(MBn)} + C ₂ (n = 1 to N) to calculate each MB
The value is stored in each register MTn corresponding to the spot Bv value stored at the address n. And each register MT
Subroutine f {(MT
n)} is executed to convert each Tv value (MTn) (n = 1 to N) into display data. Next, the Tv value (MTn) (n = 1 to N) after the display data conversion is displayed in points. Next, it is determined whether the content (M6) of the highlight input detection flag M6 is "-1" and whether the content (M7) of the shadow input detection flag M7 is "-1". Do. If (M6) =-1 or (M7) =-1, it means the highlight mode or the shadow mode. Therefore, the bar display by the averaging of the spot input data described below is not performed and will be described later. Jump to the step of inputting the spot Bv value (M0 ← BV2). If neither the highlight mode nor the shadow mode is set, the program for bar display based on the arithmetic mean of the spot input data is entered next. First, the spot-input spot Bv value (MBn) (n = 1 to 1
N) arithmetic mean value Is stored in the bar display data storage area M3. Next, the average value of the spot Bv values (M3),
The Sv-Av value (M1), the quadruple Cv value 4 (M2) and the constant C3 are added and stored in the shutter time storage area M8. The content (M8) of this area M8 becomes exposure control data, as described above. Note that, hereinafter, regarding the meaning of the arithmetic expression, detailed description of the already described one will be omitted. Next, 1/4 {(M1) + (M3)} + (M2) +
The Tv value is obtained from C2 and stored in the bar display data storage area M3. Then, subroutine f
After the contents (M3) of the area M3 are converted into display data by executing {(M3)}, a bar display subroutine is executed to display a bar.

Next, the program for blinking the current photometry point is entered.
Here, the calculation of the display data of the current metering point and the display mode of the current metering point when the blinking display of the current metering point overlaps with the spot input point, that is, the processing of prioritizing the blinking display, and a certain blinking cycle The process of blinking and displaying the current photometric point is performed. First, the display data calculation of the current photometric point will be described. First, B
The spot Bv value BV2 is stored in the v value storage area M0. Next, 1/4 {(M0) + (M1)} + C2 gives T
After calculating the v value, it is stored in the point display data storage area M4. Then, the subroutine f {(M
4)} is executed to change the contents (M4) of the area M4 into display data and then stored again in the area M4. When the display of the current metering point currently displayed by the point is updated, the old point display needs to be deleted. That is, it is necessary to set the content of the address of the memory area of the DRAM 85 corresponding to the point display to "0". However, if the display of the current metering point and the display of the spot input point were overlapped, but the current metering point was updated and the display position changed, the old current metering point remains displayed as the spot input point. I have to Next is a program for this processing. First, it is determined whether or not the content (M5) of the overlap detection flag M5 is '1', and (M5) ≠ 1.
If there is an overlap with, it is determined whether or not the display data (M4) of the current photometric point to be displayed and the display data (M5) of the current photometric point currently displayed are equal. If the data (M4) and (M
If 5) is not equal, it is determined whether or not the display data (M5) of the current photometric point currently displayed and one of the plurality of spot input point data (MTn) (n = 1 to N) are not equal. If they are equal, the data (M5) is displayed as points, and if they are not equal, the data (M5) is updated in order to update to a new display.
Clear the display of 5). Further, if the result of the determination of (M5) = 1 is YES, it means that the display is the first current photometric point, and therefore it is not necessary to update. Then, the display data (M4) of the new current photometric point is transferred to the address M5. Next, by determining I10 = 1, it is determined whether or not the shutter is released. I10 =
When the value is 1, the program branches to the exposure control program shown in FIG. When I10 ≠ 1, since the release has not been made, the program for blinking the current photometry point is entered next. First, the display blinking cycle constant C50 is stored in the display blinking cycle storage area M23. Then, the process proceeds to a subroutine WAIT3 for blinking display shown in FIG. This subroutine WAI
At T3, first, a flag M2 for blinking display
The program for delay is executed by jumping to the subroutine WAIT2 shown in FIG. 40 for inverting 2 and counting the blinking cycle. The blinking cycle of the display is determined by this subroutine WAIT2 and the program execution time in the spot auto mode. First, the subroutine WAI
At T2, the contents of the display blinking cycle storage area M23 are decremented by one and stored again in the area M23. Next, it is determined whether or not the content (M23) of the area M23 is "0". When (M23) ≠ 0, the content (M23) is again determined.
Decrement 23). Then, if (M23) = 0, the determination is negative, the sign of the blinking display flag M22 is inverted, and the process returns. A predetermined delay time is obtained by executing this subroutine WAIT2. After the execution of this subroutine WAIT2, in the subroutine WAIT3, it is determined whether or not the flag M22 is "1". If YES, the display data (M5) of the current photometry point is displayed, and if NO, the data (M5 ) Is cleared. In the next program flow, since the flag M22 is reversed in the subroutine WAIT2, the displayed point is erased or the erased point is displayed. In this way, the display state is inverted every time the program flows, and the current photometry point is displayed in blinking. When the data (M5) is displayed or cleared, the processing of the subroutine WAIT3 ends and the process returns. Here, the display of the data (M5) means the DRAM 8
5 is to store "1" in the address (M5) of the memory area, and the clearing of the data (M5) is the DRAM8.
It is to store '0' in the address (M5) of the memory area of No. 5.

Next, the program of FIG.
The processing program for the highlight mode and shadow mode shown in FIG. 2 is entered. First, by the determination of (M10) = 0, it is determined whether or not the memory hold state. No memory hold now (((M1
Since 0) = 1), the determination is answered in the negative, and then it is determined whether or not there is a highlight input by the determination of I4 = 1. Now, since there is no highlight input and I4 = 0, it is next determined whether or not it is a shadow input by the determination of I5 = 1. Now, since there is no shadow input and I5 = 0, the highlight input detection flag M6 and the shadow input detection flag M7 are subsequently detected. In highlight or shadow mode, if the highlight input or shadow input is input an even number of times, that mode is canceled, and when the mode is switched from highlight to shadow or shadow to highlight, it is selected last. It is possible to switch to the specified mode. The highlight input detection flag M6 and the shadow input detection flag M7 are
This is a flag required for this. Now, neither in highlight mode nor in shadow mode, (M6) = 1,
Since (M7) = 1, it is next determined whether or not the shutter is released by the determination of I10 = 1. If the release has not been made, the process returns to the mode discrimination program of FIG. If it is released, the program branches to the exposure control program shown in FIG. 29 through-.

Next, the exposure control program in FIG. 29 will be described. First, the content (M8) of the shutter time storage area M8 is set in the timer counter. Since the Tv value (M8) has an accuracy of LSB1 / 12Ev, it is necessary to perform the following approximate conversion on the Tv value (M8) and set it in the timer counter. Now, when the Tv value, which is the contents of the area M8, is expressed in a decimal number, it can be expressed as Tv = 12 (12X + Y + 1 / 12Z) (1) (where X, Y and Z are integers). Therefore, the exposure time T is T = (1 / f) 2 ^{(Tv / 12)} = (1 / f) 2 ^{12X + Y + 1 / 12Z} (2) (where f is the frequency of the clock pulse CK) This is approximately expressed as T = (1 / f) (1 + Z / 12) · 2 ^{12X + Y} (3). Therefore, when setting the Tv value (M8) in the timer counter, first set the Tv value (M8) to 1/12 and
Below the decimal point (here, 4 bits) is calculated. Next, the least significant bit of the timer counter is set to "1", and then the four bits below the decimal point are loaded while shifting the least significant bit from the least significant bit of the timer counter by one bit. Therefore, "1" is always loaded in the 5th bit from the least significant bit, and 4 bits below the decimal point are loaded in the lower 4 bits. Next, the 5 bits are further shifted to the upper side by 12X + Y-4 bits. As a result, the Tv value (M8) is loaded so as to satisfy the above expression (3), and the setting of the timer counter is completed. Next, by determining I11 = 0, it waits until the trigger opens, and when the trigger opens, the input port I11 becomes "1". Next, the timer counter is subtracted at a cycle of 1 / f.
Time the exposure time. Then, when the content of the timer counter becomes "0", the exposure must be ended, so "0" is output to the output port O9 to end the exposure. Then, after executing the interval instruction,
Through, the program returns to the mode classification program of FIG. 28 again. The shutter control signal S1 is used to execute the interval command.
It takes several tens of ms for 6 to be output and the movable reflecting mirror 31 to move down after the rear curtain holding magnet MG ₁ is demagnetized and to be able to perform photometry again. This is done to create this time.

Next, the flow of the program when the highlight mode is selected in the spot auto mode will be described. Now, in the spot auto mode, if I3 = 0 instead of spot input, in this case, in the mode discriminating program of FIG. 28, I3
If the judgment of = 1 is answered in the negative, the program branches to the program for no spot input in the spot auto mode of FIG. 31 through-. Hereinafter, description of programs common to the normal spot auto mode will be omitted.
Now, it is assumed that the flow of the program has progressed and the display of the spot input point has been changed. That is, the 31st
In the flow of the figure, data (MTn) (n = 1 to N)
It is assumed that the point display step of is completed. Next, by (M6) =-1 and (M7) =-1, it is determined whether or not there is a highlight input and whether or not there is a shadow input, but at this stage it is still (M6). =
Since 1, (M7) = 1, the normal spot auto mode program is executed and bar display of the bar display data (M3) is performed. When the flow of the program further progresses, the program of FIG. 32 is entered through-. Here, first, it is determined whether or not the memory is held by the determination of (M10) = 0. However, since it is not in the memory hold state, the determination is no, and then the highlight mode detection input port 14 Perform level detection. Now that highlight input is in progress and I4 = 1,
The determination I4 = 1 is exited with YES, and then “1” is stored in the detection flag M17 immediately after the highlight input. This flag M17 is a flag for detecting whether or not the program is executed for the first time after the highlight mode is selected. next. In order to reset the flip-flop circuit (G ₁₅ , G ₁₆ ) for detecting the highlight input, the output port O
Output a positive pulse to 2. Then, the contents of the highlight input detection flag M6 are inverted. Now (M6) =
When it is -1, the highlight mode is set, and when (M6) = 1, the highlight mode is released. That is, when the highlight input detection flip-flop circuit (G ₁₅ , G ₁₆ ) is set an even number of times, (M6) = 1, and the highlight mode is canceled, and when it is set an odd number of times, (M6) = − 1. Next to
Highlight mode is selected. Now, (M6) =-1
It is assumed that the highlight mode has been selected with. Next, "H
The "IGH" segment is displayed (see FIG. 51).
Then, the spot Bv value MBn (n
MIN (MBn) (n = 1 to 1)
N) is obtained and stored in the shutter time storage area M8. Next, it is determined whether or not the content (M17) of the detection flag M17 immediately after highlight input is "1",
When (M17) = 1, that is, when the program flow is the first time after switching to the highlight mode, the bar display first reaches the spot input point corresponding to the minimum value MIN (MBn), as described above. Need to stretch (5th
(See Figure 1). Next, a program for this processing will be described. First, the Tv value is calculated by 1/4 {(M1) + (M8)} + C5, and the bar display data storage area M3 is calculated.
Store at. Here, (M1) is the Sv-Av value, (M1
8) is the minimum spot Bv value input by spot, C
5 is a constant. Next, after converting the Tv value (M3) into display data by executing the subroutine f {(M3)},
The Tv value (M3) is displayed on a bar. Then, the interval instruction is executed. This interval command waits until the bar display of the above-mentioned Tv value (M3) indicating the maximum brightness value (M8) is performed and then the bar display at the shutter speed of 21/3 Ev over this value (M3) is executed. It plays the role of creating a deadline. If this interval command is not executed, the bar display will reach the maximum brightness value and then immediately 2/3
This is because it is difficult to confirm the display by shifting to the display of Ev over, so that it is prevented. If (M
When 17) =-1, the bar display of the maximum luminance value is not performed, and the operation described below is executed. Then, a bar display of 21/3 Ev over is performed from the point display of the spot input data corresponding to the maximum brightness value. First, 1/4
{(M1) + (M8)} + (M2) + C5 + 7
The v value is calculated and stored in the area M3. Here, the added number '7' corresponds to 21/3 Ev. A correction value (M2) is also added to this calculation. Then, by executing the subroutine f {(M3)}, the data (M3) is converted into display data, and then the area M3 is again displayed.
And display the data (M3) in a bar (5th
(See Figure 2). Next, (M1) +4 (M2) + (M8) + C
The exposure time in the highlight mode is calculated by 6,
This is stored in the shutter time storage area M8. Here, (M1) is the Sv-Av value, (M2) is the Cv value, and (M
8) is the maximum brightness Bv value, and C6 is a constant. The above is
In distinguishing the highlight mode detection flag M6,
As for the case where (M6) = − 1,
When (M6) = 1, the display of the "HIGH" segment is erased. Then, the flag M17 is set to the effect that the detection flag M17 immediately after the highlight input is set to "0", the mode is shifted to the highlight mode, and the first program flow is completed. Next, the shadow input detection flag M7 is set to "1" and the flag M7 is reset.
Thereafter, it is determined whether or not the shutter is released by the determination of I10 = 1, and the program is branched to a predetermined flowchart through-or-as in the case of the normal spot auto mode.

Next, a case where the shadow mode is selected in the spot auto mode will be described. Detailed description of the same program flow as in the normal spot auto mode and highlight mode will be omitted. In the flowchart of FIG. 32, in the shadow mode,
The judgments of (M10) = 0 and I4 = 1 are skipped, and the judgment of I5 = 1 is started. With shadow input,
Since I5 = 1, "1" is stored in the detection flag M18 immediately after the shadow input. This flag M18
Is a flag for detecting whether or not it is the first program flow after changing to the shadow mode.
Indicates that it is the first time. Next, a positive pulse is output to the output port O3 to reset the shadow mode detecting flip-flop circuits (G ₁₉ , G ₂₁ ). As a result, I5 = 0. Then, the sign of the shadow input detection flag M7 is inverted. This is because the shadow mode is cleared when the shadow mode is continuously selected an even number of times, as in the highlight mode. In resetting the variables in FIG. 30, (M
Since 7) = 1, in the first program flow, (M7) =-1, and the next determination of (M7) = 1 is no. Therefore, first, the "SHDW" segment is displayed (see FIG. 55). continue,
Minimum brightness value MAX (MBn) (n =
1 to N). Here, the larger the data (MBn), the smaller the brightness value. Therefore, the data (MBn)
The maximum value of is equivalent to the minimum brightness value. The obtained minimum brightness value MAX (MBn) is the shutter-second storage area (M
Stored in 8). Next, it is determined by (M18) = 1 whether or not it is the first program flow after changing the shadow mode. Since (M18) = 1 in the first program flow, it follows that , Minimum brightness value MA
The bar display data corresponding to X (MBn) is calculated. This is obtained by 1/4 {(M1) + (M8)} + C5 and stored in the bar display data storage area M3. Here, (M1) is an Sv-Av value, (M8) is a minimum luminance value MAX (MBn), (M2) is a Cv value, and C5 is a constant. Next, the subroutine f {(M3)} is executed to convert the data (M3) into bar display data, and then the bar display corresponding to the minimum brightness value MAX (MBn) is performed (see FIG. 55). . Next, the interval instruction is executed, and the purpose of this instruction is the same as that described in the description of the highlight mode. In this way, after switching the shadow mode, in the first program flow,
The bar display is once returned to the position corresponding to the spot point display corresponding to the lowest brightness value. This display is not necessary in the flow of the program from the second time onward, so in this case, the determination of (M18) = 1 is left without a branch to the next program directly. Next, from the lowest brightness value, 22 /
The program for displaying 3Ev underbar is executed. Here, first, 2 2 / 3E from the lowest brightness value
Calculation of Tv value corresponding to vunder is 1/4 {(M1) +
(M8)} + (M2) + C5-8, and the result is stored in the bar display data storage area M3.
Here, (M1) is an Sv-Av value, (M8) is a minimum luminance value MAX (MBn), (M2) is a Cv value, and C5 is a constant. The subtracted '8' corresponds to 2 2/3 Ev. Next, after the data (M3) is converted into bar display data by executing the subroutine f {(M3)}, the bar display of the data (M3) is performed (see FIG. 56). Then, the exposure time information in the shadow mode is obtained by (M1) + (M8) +4 (M2) + C6 and stored in the shutter time storage area M8. On the other hand, the above (M
7) In the judgment of 1, the shadow input detection flag M
When 7 is '1', the shadow mode is released, so the display of the “SHDW” segment is erased and the bar display corresponding to the above minimum brightness value and 2 2/3 Ev from this are displayed.
The under bar is not displayed. Then, "0" is stored in the detection flag M18 immediately after the shadow input. As a result, in the shadow mode program from the next time onward, the content (M18) of the flag M18 is determined and the bar display corresponding to the lowest brightness value is not performed. Further, the highlight mode detection flag M6 is reset to "1", then it is judged whether or not the shutter is released by the judgment of I10 = 1, and the process is branched to each program through-or-.

In the highlight and shadow modes, I4 = 0 and I5 = 0 in the second and subsequent program flows. At this time, the determinations of I4 = 1 and I5 = 1 are respectively rejected with no, and subsequently, (M6) = − 1, (M
7) The judgment of = -1 is performed. When (M6) =-1, the highlight mode is selected, so the program in the highlight mode is executed.
When (M7) =-1, the shadow mode is selected, so the shadow mode program is executed. If neither is the case, the process directly goes to the determination of I10 = 1. Then, by the determination of I10 = 1, it is determined whether or not the shutter release is performed, and the program is branched to-or-through each program.

Next, the memory mode will be described. As described above, the memory mode includes the direct auto memory mode and the spot auto memory mode. First, the direct auto memory mode will be described. Now, in the flow of the program for mode discrimination in FIG. 28, after the determination that the strobe power is turned on with I13 = 1 in the auto mode, the memory mode detection input port I6
The level is determined. Since the input port I6 becomes Selecting memory mode by closing the memory switch SW ₆ and I6 = 1, leaves the determination I6 = 1 at YES, then determination of the memory hold detecting flag M10 is performed. This flag M10 is a flag that becomes "1" in the memory set state and "0" in the memory hold state. If it is a memory set, (M1
Since 0) = 1, subsequently, the area M21 for storing the apex value of the actual exposure time is initialized to '0'. Then, the "MEMO" segment is displayed (see FIG. 57). Then, the memory mode detection flag M11 is determined. This flag M11 is
This is an area for storing the shooting mode in the memory mode, that is, a mode constant of the direct auto memory mode or the spot auto memory mode. Now, since the constant C26 is stored in the flag M11 by the normal auto mode program, (M11) ≠ C2
1, (M11) ≠ C20. Here, C21 is an average direct auto mode constant, and C20 is a spot auto mode constant. Therefore, the level of the input port I2 is next determined. Since I2 = 0 in the average direct auto memory mode, the 29th
Branch to the program in the average direct auto mode in the figure. Here, first, the average direct auto mode constant C21 is stored in the shooting mode detection flag M12. Hereinafter, only the part peculiar to the memory mode will be described, and the description of the part common to the average direct auto mode will be omitted. In the state of the memory set, there is no difference from the average direct auto mode except that "MEMO" is displayed until the release. Now, assuming that the shutter is released, the determination of I10 = 1 is answered with yes,
Furthermore, the determination of I6 = 1 is answered with yes, and (M10)
= 0 is reached. Since it is in the state of the memory set now, the judgment of (M10) = 0 is passed without a judgment, and then I11
Whether the trigger is open or not is detected by the judgment of = 0. When the trigger opens, the determination of I11 = 0 is exited with YES, and the actual exposure time is counted. In this case, exposure control is based on average direct photometry. The counting of the actual exposure time is performed by executing the subroutine for counting the actual exposure time shown in FIG. Next, the program of this subroutine will be described. The outline of the counting method of the actual exposure time is as already described with reference to FIG. 26. However, once again, the actual exposure time is counted every twelve count pulses. This is done by doubling the cycle. By doing this,
The final count value itself becomes a value corresponding to an apex value with a weight of LSB 1/12 Ev. In this subroutine, first, the reference pulse cycle storage area M32
Then, the constant C60 is stored, and "0" is initialized in the reference pulse count number storage area M30. next,
The reference pulse cycle (M32) is stored in the area M31. Then, while decrementing the contents (M31) of area M31 one by one, this is stored in area M31,
Decrement is repeated until the content of area M31 becomes "0" by the determination of (M31) = 0. When the content of the area M31 becomes “0”, the determination of (M31) = 0 is answered in the affirmative and then the apex calculation value storage area M21 and the reference pulse count number storage area M30 of the actual exposure time are incremented by 1 respectively. To do. Next, the level of the exposure end signal input port I12 is detected. If exposure is not completed, I12 = 1, so I
After the determination of 12 = 0, the determination of (M30) = 12 is performed. This determination is to determine whether 12 pulses have been counted. If the count number is less than 12, the reference pulse period (M32) is again set in the area M31.
Return to the program that stores. Then, when this loop is repeated 12 times and (M30) = 12, this time, the reference pulse period (M32) is doubled and then the count number storage area M30 is reset to "0". , And returns to the program for storing the reference pulse period (M32) in the area M31 again. The above program is repeated until the exposure by direct photometry is completed, and when the exposure is completed, the determination of I12 = 0 is exited with a yes and return,
Return to the program shown in FIG. Therefore, the area M21 stores a value corresponding to the apex calculation value of the exposure time. Next, in order to indicate that the actual exposure time of the average direct auto shooting is held in memory, "0" is stored in the memory hold detection flag M10,
After executing the interval command,
Return to the program for mode discrimination shown in the figure.

In the subsequent first program in the memory set state, as in the case of the memory hold, after the determination of I6 = 1 in FIG. 28 is answered in the affirmative, the determination of (M10) = 0 is started. Since M10 = 0 in the memory hold this time, this determination is answered in the affirmative and the memory hold detection flag M11 is replaced by the shooting mode detection flag M12.
The content (M12) of is stored. Now, the flag M12
Since the average direct auto mode constant C21 is stored in, the constant C21 is set in the flag M11. Next, the shutter control signal output port O9 is set to "1" and the shutter control signal S16 is set to "H" level. Then, the judgment of (M11) = C21 starts,
As described above, since the content of the flag M11 is the constant C21, the determination is YES, and the content of the shooting mode detection flag M12 in the average direct auto mode program of FIG. The process branches to the step of transferring to M13. Now, since M10 = 0 in the memory hold state, the determination in the following (M10) = 0 is YES, the Sv-Av value (SV-AV) is stored in the area M19, and the Cv value CV is stored in the area M20. Stored. Next, the Cv value is input by the judgment of (M2) = 0 and (M2)
2) If ≠ 0, display "±" segment,
Otherwise, the display of the "±" segment is deleted. Then, the determination of (M10) = 0 is returned again with YES, and first, the Sv-Av value (M1) input when the memory is set.
And the Sv-Av value (M1
9) and the difference is stored in the area M19.
Next, the difference between the Cv value (M2) input at the time of memory setting and the Cv value (M20) input at the time of memory hold is obtained and stored in the area M20. Then, (M
21) + (M19) +4 (M20) + C40 to calculate the exposure time in the direct auto memory mode,
This is stored in the shutter time storage area M8. Here, the meaning of this expression will be described. As described above, (M21) is the apex calculation value of the actual exposure time by direct photometry. This value is Bv value, Sv-A
It is a value including v value and Cv value, and therefore (M21) +
(M19) +4 (M20) + C40 is an arithmetic expression that makes the exposure level the same as in direct photometry shooting in the memory set state, even if the aperture and film sensitivity are changed. Further, by adding 4 (M20), the memory hold can be corrected. The reason is as described above. Next, 1/4 {(M
0) + (M1)} + (M2) + C2 to calculate the Tv value for bar display. Here, (M0) is the average B immediately before the shutter is released in the memory set state.
The v value does not change as long as the memory is held.
Then, the subroutine f {(M3)} is executed to convert the calculated value (M3) into bar display data, and then the bar display is performed. In this bar display, the entire bar display is blinked (see FIG. 58). Next, the interval instruction to be executed is particularly necessary at the time of memory setting, and the purpose will be described here. The level of the input port I10 is "1" when the release signal S0 is input in synchronization with the shutter release, but in actuality, I10 = 1 is set during the rising transition of the movable reflecting mirror 31. There is. Since the metering of the display is performed by the reflected light of the mirror, if the input average Bv value (M0) is during this mirror rising transition, the display data at the memory hold and the actual data by the memory hold are displayed. The exposure time data does not match. Therefore, the Bv value held immediately before the release must be the value immediately before the mirror is raised. Roughly speaking, the program repeats the input of the average Bv value, the determination of the release, and the storage of the average Bv value data. The mirror 31 raises the time from the input of the average Bv value to the release determination. This problem can be solved by setting the time longer than the time from the start to the level of the input port I10 becoming "1". The execution of interval instructions is necessary for this. Next, when the release is performed in the average direct auto memory mode, the determination of I10 = 1 is exited with YES, and the level of the input port I6 is subsequently determined. Now, in memory mode, I6 = 1, so (M1
0) = 0 is entered, and since it is a memory hold, this determination is exited with YES, and then the shutter time storage area M
8 (M8) is set in the timer counter. The method of setting the timer counter is as described above. Further, since the subsequent programs have already been described, detailed description thereof will be omitted here.

Next, the spot auto memory mode will be described.
Since the spot auto mode is originally a memory metering, and the exposure is performed only based on the metering value input by manual operation, in principle, the spot auto memory mode does not input a new metering value. All you have to do is First, in the state of the memory set, only "MEMO" is displayed and there is no difference from the flow in the spot auto mode. The above-mentioned "MEMO" display is performed in the same manner as in the case of the direct auto memory, and therefore its explanation is omitted. Further, since the spot auto mode constant C20 is set in the memory mode detection flag M11, it is always shown in FIG. 31 through the judgment (M11) = C20 in the mode judgment program of FIG. 28. Branch to a program without spot input in spot auto mode. That is, in the spot auto memory mode, spot input is ignored. In addition, neither the highlight input nor the shadow input is detected. That is, in the program of FIG. 32, (M1
By exiting the judgment of 0) = 0 with Yes, I4 =
The discrimination of 1, I5 = 1 is ignored. Further, the bar display is made to blink. Except for what has been described above, the operation is the same as in the spot mode. The bar display will be collectively described later in detail.

Next, a case where the power of the strobe is turned on in the auto mode will be described. When the power of the strobe is turned on, the strobe power-on signal S14 becomes "H" level, and the input port I13 becomes "1". For this reason, in the mode discrimination program of FIG. 28, the determination I13 = 1 is exited with YES, and the program branches to the strobe auto mode program shown in FIG. Here, first, a positive pulse is output to the output ports O0 to O3 to reset each flip-flop circuit corresponding to the interface. Next, "1" is transferred to the memory hold detection flag M10 and the flag M10 is reset. Subsequently, the flash auto mode constant C30 is stored in the shooting mode detection flag M12. next,
The determinations of (M13) = C22 and (M13) = (M12) are performed to determine whether the power has just been turned on and whether the mode has just been switched. The display is reset (see FIG. 68). To reset this display,
The "AUTO" segment, the fixed point index, and the "60" segment at the time of strobe tuning are displayed respectively. This is because in the strobe auto mode, the deviation of the photometric value with respect to the strobe synchronization time of 1/60 seconds is displayed as points on the bar display segment row. Next, the average Bv value BV1 is stored in the Bv value storage area M0, the Sv-Av value (SV-AV) is stored in the Sv-Av value storage area M1, and the Cv value CV is stored in the Cv value storage area M2. Then, if there is correction based on the determination of (M2) = 0,
The "±" segment is displayed, and when there is no correction, the "±" segment display is deleted. Next, 1/4 {(M
0) + (M1)} + (M2) + C100, the deviation of the photometric value with respect to the shutter speed of 1/60 second is obtained, and this is stored in the point display data storage area M4. next,
By executing the subroutine g {(M4)}, the data (M
After converting 4) into display data, this is displayed as points on the segment column for bar display (see FIG. 68). Here, g {(M4)} is a subroutine for setting the data outside the display data range to the limit value.
It may be considered that only the limit set values C40 and C41 in {(M3)} are different. Therefore, this subroutine g
The detailed flow chart of {(M4)} is omitted here for illustration and description. Next, display blinking cycle storage area M
The display blinking cycle constant C35 is stored in 23. This constant C35 is underexposure after flash auto shooting,
This is a constant for determining the blinking cycle such as overexposure and proper exposure. Then, the program moves to the program of the subroutine WAIT1 (see FIG. 39), and the execution thereof is started. First, jump to the subroutine WAIT2 and set the constant C
After creating an interval corresponding to 35, the blinking display flag M22 is reversed and the process returns to the subroutine WAIT1. Subsequently, it is determined whether or not the flag M22 is "1". When (M22) = 1, a level determination for over, under, or proper display and a display program are executed. First, input port I
It is determined whether or not 14 is "1". When I14 = 1, it means that the exposure is overexposed. Therefore, the "+" segment is displayed (see FIG. 70) and the process returns. When I14 ≠ 1, the input port I15 is "1".
Then, it is judged whether or not If I15 = 1, it means that the exposure is underexposure, so the "-" segment is displayed (see FIG. 71) and then the process returns. If I15 ≠ 1, the strobe is appropriate and the "▲" segment is displayed. And return. And in the next program flow,
Since the sign of the flag M22 is inverted in the subroutine WAIT2, (M22) =-1 and "-",
The "+" segment display is erased. Furthermore, I16 =
When it is 1, the judgment of I16 = 1 erases the "▲" display and returns. The input ports I14, I15,
I16 is '1' only for about 2 seconds after strobe emission, so during this period, depending on the program flow, underexposure, overexposure, or "-"
The display of "+" and "▲" blinks respectively.
Also, if it is not about 2 seconds after the flash fires, "▲"
Only the display of is displayed continuously. After execution of the subroutine WAIT1, returning to the program shown in FIG. 33, subsequently, it is determined whether or not the shutter is released by the determination of I10 = 1. If it is not released, the program directly returns to the mode discriminating program of FIG. 28 through-and if it is released, the shutter control and the strobe control are performed by hardware as described above. The trigger is released by the judgment of = 0, and the
Return to the program for mode discrimination in the figure.

Next, the manual mode will be described. Now, when you select the manual mode to suit the shooting mode switching operation knob 21 to "MANUL" indicator, manual switch SW ₃ is closed, the input port I1 is '1'. Therefore, in the mode discriminating program of FIG. 28, the determination of I0 = 1 is answered no, the determination of I1 = 1 is answered yes, and the determination of I13 = 1 is started. Now, assuming that the power of the strobe is not turned on, I13 = 0,
Next, the level of the input port I2 for spot mode detection is judged. Now, if the spot mode is not selected and the normal manual mode is set, I2 = 0.
The program branches through-to the flowchart for the normal manual mode shown in FIG. Here, first, "1" is output to the output port O9. As a result, the trailing-curtain holding magnet MG ₁ is energized, and the trailing-curtain enters the holding waiting state. Next, the normal manual mode constant C23 is stored in the shooting mode detection flag M12. Next, (M13) = C22 and (M1
3) = (M12) is used to determine whether the power has just been turned on or the mode has been switched. If the power has been turned on or the mode has been switched, the variables and the display are reset. First, when the variables are reset, the bar display start point address is set in the bar display start address storage area M14.

Next, in resetting the display, "MANU" and the fixed point index are displayed (including "+" and "-" display) (see FIG. 61). Then, the contents of the shooting mode detection flag M12 (M1
2) is transferred. Next, areas M0, M1 and M2
The average Bv value BV1, the Sv-Av value (SV-AV) and the Cv value CV are stored in the table. Then, (M
2) = 0 is determined, "±" is displayed when the correction is input (see Fig. 62), and "±" is erased when the correction is not input. next,
Clear the display for the manually set time (M8).
The display may be cleared immediately before the display is updated at the manually set time (M8) described later. Next, in the area M8, the manually set second time input by the binary code is input. Since the weight is LSB1Ev at the time of manual setting, for the following display,
The content (M8) is tripled and stored in the area M8 again for the purpose of converting to the value of LSB1 / 3Ev. Then, the manually set time (M8) is displayed. In FIG. 61, the case where the manually set second time is set to 1/60 second is shown. That is, the DRA corresponding to the segments "1" to "2000" for displaying each shutter speed
There is a one-to-one correspondence between the address of the memory area of M85 and the manually set second. Next, the standard exposure level (6th
Calculation of bar display data of deviation for 1/60 second shutter speed in Fig. 1/4 {(M0) + (M1)} +
Perform (M2)-(M8) + C8 and set this as area M3.
Store at. Here, (M0) is the average Bv value, (M0
1) is an Sv-Av value, (M2) is a Cv value, (M8) is a manually set second, and C8 is a constant. Then, a subroutine h {(M3)} is executed to convert the calculated value (M3) into display data. Here, subroutine h
{(M3)} is a subroutine for limiting the deviation from the standard exposure level within the display data range when the deviation is outside the display data range.
3)}, it may be considered that only the limit set values C40 and C41 are different. Therefore, this subroutine h {(M
3)} detailed flowchart is omitted here. This subroutine h {(M
3)} fixes the data (M3) to the limit value when the deviation (M3) from the standard exposure level is larger than a certain value, and fixes the data (M3) to the limit value when the deviation is smaller than the certain value. To do. That is, the bar display is the 61st
It is performed within the range corresponding to the "+" and "-" segments shown in the figure. Next, the presence or absence of the shutter release is determined by the determination of I10 = 1. When the shutter release is not performed, the deviation (M3) bar is displayed, and then the program returns to the mode determination program shown in FIG. When the shutter is released, the exposure control program shown in FIG. Here, the timer counter is first set, but the value set in the counter is the manually set second time stored in the area M8. In this case, above
Z in the equation (3) becomes "0", and the timer counter is set by the same calculation as in the exposure control during spot auto. Since the flow of the following program is the same as that in the spot auto mode, its explanation is omitted here.

Next, a case where spot input is performed in the manual mode will be described. In manual mode spot input switch SW ₈ is turned on, if the spot input is performed, the spot mode detecting input port I2 is '1'. Therefore, in the mode discriminating program of FIG. 28, the judgment I2 = 1 branched toward the normal manual mode becomes yes, and then (M
13) = C20 is determined. Now (M13) = C
At 20, since the last shooting mode indicating that was spot auto mode, in this case, the output ports O0, O1 outputs a positive pulse to the spot mode detection flip-flop circuit (G _7, G ₉ ) and the spot input detection flip-flop circuits (G ₁₁ , G ₁₂ ) are reset. This has been described in the spot auto mode, but is to prevent the spot manual mode from entering the spot manual mode when the manual mode is directly selected. That is, when changing between the basic shooting modes of the auto mode and the manual mode, the mere auto mode or the manual mode is always selected, and the spot mode after the change is not set. Then, the output ports O0, O1
After the output of the positive pulse to, the mode is discriminated again by returning to the beginning of the mode discrimination program through-. On the other hand, if the immediately preceding shooting mode is not the spot manual mode, the determination of (M13) = C20 is answered no, and the level of the input port I3 is determined next. When the spot input switch SW ₈ is closed, the spot manual mode is selected, and at the same time, the spot input detection flip-flop circuits (G ₁₁ , G ₁₂ ) are set, so that I3 = 1.
Then, through-, the program branches to a program with spot input in the spot manual mode shown in FIG. Here, first, the spot B is stored in the Bv value storage area M0.
Store the v value BV2. Next, the shot mode manual mode constant C24 is stored in the shooting mode detection flag M12. Then (M13) = C22 and (M13) =
It is determined by (M12) whether the power has just been turned on or the mode has been switched. If the power has been turned on or the mode has been switched, the variables are reset, the display is reset, and the interface is reset. First, when the display is reset, "1" is stored in each of the overlap detection flag M5, the highlight input detection flag M6 and the shadow input detection flag M7. next,
The address of the bar display start segment is stored in the bar display start address storage area M14. Further, "0" is stored and reset in the spot input data number storage area M16. Next, when resetting the display,
"MANU", "SPOT", and fixed point index display (including "+" and "-" display) are performed (63rd display).
See figure). Subsequently, in a reset of the interface, the output port O2, O3 and outputs a positive pulse, the highlight input detection flip-flop circuit (G _15,
G ₁₆ ) and the shadow input detection flip-flop circuit (G ₁₉ , G ₂₁ ) are reset.

Next, the content (M12) of the shooting mode detection flag M12 is transferred to the shooting mode detection flag M13. As a result, (M1
3) = (M12), so variables, displays and interfaces are not reset. Next, the spot input data number storage area M16 is incremented by one. Then, the spot Bv value (M0) and the Sv-Av value (SV-AV) are stored in the register MBN and the area M1.
To store. Here, N of the register MBN is a value corresponding to the number of spot inputs, that is, the content of the area M16 (M
It is a value corresponding to 16) and becomes "1" at the first spot input. Therefore, the spot BV values obtained by a plurality of spot inputs are stored in separate registers. Then, the display at the manually set time (M8) is cleared. Next, the manually set time data (I8) set in the input port I8 is stored in the area M8. Then, set the manually set second (M8) to 3
The weight is doubled, the weight is converted, and the result is stored again in the area M8. Then, the contents of the area (M8) are displayed. In FIG. 63, the case where the manually set second time is set to 1/125 second is shown. Next, the standard exposure level (63rd
Calculation of deviation for 1/125 second shutter time)
{(MBN) + (M1)} − (M8) + C8,
This is stored in the register MTN. Here, the N of the register MTN is a value corresponding to the number of spot inputs, like the N of the register MBN. Subsequently, the subroutine h {(MTN)} is executed to convert the deviation (MTN) into display data, which is then displayed as points (63rd).
See figure).

Next, the bar display is performed based on the arithmetic mean value of the spot input values. If (M6) =-1 or (M7) =-1 in the highlight mode or the shadow mode, it will be described below. Canceling the direct spot input state without calculating the arithmetic mean value Fly to the program. Now, neither in the highlight mode nor in the shadow mode, (M6) = 1, (M7) = 1
Then, the average value of the spot Bv values (MBn) (n = 1 to N) input so far is Is stored in the area M3. Subsequently, the Cv value CV is stored in the area M2, and if (M2) ± 0, “±” is displayed (see FIG. 65), (M2) =
If it is 0, the display of "±" is deleted. Next, the calculation of the deviation of the exposure level obtained by the addition average value (M3) with respect to the standard exposure level 1/4 {(M1) + (M3)} + (M
2)-(M8) + C8 is performed and this is stored in area M3. Subsequently, the subroutine h {(M3)} is executed to convert the calculated value (M3) into bar display data. Then, outputs a positive pulse at the output port O1, flip-flop circuit for spot input detection (G _11, G ₁₂₎
Reset the spot input state by resetting. Subsequently, the presence or absence of the shutter release is determined by the determination of I10 = 1, and if not released, the deviation (M3) bar is displayed (see FIG. 64), and the mode determination shown in FIG. Return to the program. If it is released, the program branches to the exposure control program shown in FIG. Here, the manually set time (M8) is set in the timer counter, and the exposure control is performed based on this value. Then, the execution of the above-mentioned program is completed, and the program returns to the mode discriminating program of FIG. 28 through-.

Next, in the second and subsequent program flows after the spot mode is selected, if the spot mode is not released and there is no spot input, then I2 = 1 and I3 = 0. In the mode discrimination program,
If the determination of I2 = 1 is YES and the determination of I3 = 1 is NO, the process branches to the program without spot input in the spot manual mode shown in FIG.
Here, first, in the areas M1 and M2, Sv-Av is set.
Enter the value (SV-AV) and the Cv value (CV) respectively. Subsequently, the determination of (M2) = 0 is performed, and if there is correction, “±” is displayed, and if there is no correction, the display of “±” is erased. Next, the display of the manually set time (M8) is erased. Subsequently, after the manually set second data (I8) is stored in the area M8, the contents of the area M8 (M
8) is tripled and stored again in the area M8. Then, the manually set time (M8) is displayed (see FIG. 63). Subsequently, the display of all the spot input points (MTn) (n = 1 to N) is once erased for changing the display of the spot input points according to the change of the Sv-Av value.
Next, each spot Bv value (MBn) input by spot
Calculation of deviation from standard exposure level by (n = 1 to N) 1/4 {(MBn) + (M1)}-(M8) + C8 (n
= 1 to N) and register these in the register MTn (n = 1
To N) respectively. Next, each deviation (MTn)
Subroutine h {(MTn)} for (n = 1 to N)
Convert these to display data by executing
The data is stored again in the register MTn (n = 1 to N). Then, the point display of each deviation is performed based on each display data (MTn) (n = 1 to N). That is, the point display of the spot input is changed so that the exposure level is always constant, and then the highlight mode or the shadow mode is determined by the determination of (M6) =-1 and (M7) =-1. In the highlight mode or the shadow mode, the spot Bv value described later is input (M0 ← BV
Jump to program 2). If neither the highlight mode nor the shadow mode is selected, then Cv is added to the average value of the spot Bv values input by spot.
Enter the bar display program for standard exposure levels including values. First, the average value of spot Bv values (MBn) (n = 1 to N) input in spots And store this in area M3. Then 1/4
By {(M1) + (M3)} + (M2)-(M8) + C8, the deviation of the standard exposure level with respect to the addition average value of the spot-input spot Bv values is calculated and stored in the area M3. . Next, the deviation (M3) is converted into display data by executing the subroutine h {(M3)}, and then the deviation (M3) is displayed by a bar.

Next, the spot Bv value BV2 is stored in the area M0.
This is automatically performed regardless of the spot input operation, and is a Bv value for displaying the deviation of the current photometric point. Then, 1/4 {(M0) + (M1)}-(M8) between the previously input Sv-Av value (M1), manually set second data (M8) and constant C8.
+ C8 is calculated and stored in area M4. Next, the subroutine h {(M4)} is executed to convert the deviation (M4) into display data. Next, a program for detecting the overlap between the point display of the deviation of the current photometric point and the point display of the deviation due to the spot input is executed. The point display of the deviation of the current metering point and the point display of the deviation due to spot input are the same as in the spot auto mode, because the segment line for point display is used in common, so the deviation of the current metering point When changing the point display, if it overlaps with the point display of the deviation due to spot input, that display should be retained, and if it does not overlap, it should be deleted. The following program detects this overlap. First, (M5) = 1 is determined, and if the overlap detection flag M5 is '1', it is the first program flow after changing to spot mode, so the deviation of the current photometric point is still displayed. There is no need to worry about overlapping. Therefore, it jumps directly to the program for transferring the point display data (M4) to the flag M5 and stores the data (M4) in the flag M5. Thus, in the second and subsequent program flows, the flag M5 stores the display data of the deviation of the current photometric point obtained in the previous program flow. Therefore, in the program flow from the second time onward, the judgment of (M5) = 1 is passed without a judgment, and then (M4)
= (M5) is entered. When (M4) = (M5), it means that there is no change in the display of the deviation of the current photometric point, and therefore the program for direct data transfer (M5 ← (M4)) is entered. When (M4 ≠ (M5),
Since there is a change in the display of the deviation of the current photometric point, the display data (M5) of the deviation of the current photometric point currently displayed is the point display data (MTn) (n = 1 to N) is sequentially determined. And if
If (MTn) = (M5), then the data (M
The point display of 5) is performed, and if there is no (MTn) = (M5), the point display of the data (M5) is cleared. Then, the deviation (M
4) is transferred to the flag M5. Next, it is determined whether or not the shutter is released by the determination of I ₁₀ = 1. If the shutter is not released, the deviation (M5) of the current photometric point is displayed by blinking. Therefore, the display blinking cycle constant C50 is transferred to the display blinking cycle storage area M23, and thereafter the subroutine of FIG. 41 is executed. Execute WAIT3. The program flow of the subroutine WAIT3 and the purpose of the blinking operation have been described in detail in the spot auto mode, and therefore will be omitted here. On the other hand, if the shutter is not released, the program jumps to the exposure control program shown in FIG. 29 through-, and after this program is executed, the program returns to the mode determination program shown in FIG. 28 through-.

When the execution of the subroutine WAIT3 is completed, the program then shifts to the flowchart for highlight mode or shadow mode shown in FIG. 37 through-. Here, it is first determined whether I4 = 1 or not by the determination of I4 = 1. Assuming that highlight input has not been made, I4 = 0, so the determination is negative, and then I5 = 1 is used to determine whether or not a shadow input has been made. Now, if it is not a shadow input either, since I5 = 0, the determination is negative, and subsequently it is determined whether or not the highlight input detection flag M6 is "-1". Also, (M
6) If ≠ -1, then it is determined whether or not the shadow input detection flag M7 is "-1". At highlight input or shadow input, the input port I4 or I5 is set to "-1", which immediately becomes "0" in the first program flow in highlight mode or shadow mode. It will be reset. Therefore, the highlight mode state or the shadow mode state is stored and held in an internal flag called a highlight input detection flag M6 or a shadow input detection flag M7. Therefore, the flags M6 and M7 are determined here. Now, assuming that neither the highlight mode nor the shadow mode is set, (M6) = 1,
Since (M7) = 1, the program for processing in the highlight mode and the shadow mode does not pass, and I10 = 1 directly.
Then, it is determined whether or not the shutter is released. If it is not released, then I10 = 0, so the program returns to the mode discrimination program of FIG. 28 through-. If the shutter is released, I10 =
Since it is 1, the program branches to the exposure control program shown in FIG. Here, manually set second data (M8) is set in the timer counter, and exposure control is performed according to the contents of the timer counter. After the exposure is completed, the program returns to the mode discrimination program of FIG.

Next, the flow of the program when the highlight mode is selected in the spot manual mode will be described. Now, suppose that the program progresses, the point display of the deviation of the current photometric point is finished, and the point reaches as shown in FIG. Next, by the determination of I4 = 1, the level of the input port I4 for detecting the highlight input is determined. Now, assuming that the program flow is the first time after the highlight mode is selected, I4 = 1, so the determination is YES, and then "1" is stored in the detection flag M17 immediately after highlight input. It This flag M17 is a flag for detecting whether or not it is the first program flow after the highlight mode is selected, and when it is "1", it is the first program flow. Indicates that. Next, output mode O2
A positive pulse is output to reset the highlight input detection flip-flop circuits (G ₁₅ , G ₁₆ ). continue,
The sign of the highlight input detection flag M6 is reversed.
Now, without or closed after you close the shadow switch SW _10, and with the highlight switch SW ₉ was closed odd number of times, the flag M6 is '1' next to, (M
6) The judgment of 1 is exited without a judgment, and then "HIGH" is displayed. Also, if the highlight switch SW ₉ was closed even number of times, the flag M6 is '1', and the exits at YES determination of (M6) = 1, followed by "H
IGH "erasure of the display is carried out. This" after the erasure of the HIGH "display, fly to the program of the reset (M17 ← 0) of the highlight input immediately after the detection flag M17, which will be described later. Now, highlight switch SW ₉ is an odd number It has been closed and the message "HIGH" is displayed.
The highest brightness value MIN (MBn) of the spot input values (MBn) (n = 1 to N) is calculated and stored in the brightness value storage area M9. Next, by (M17) = 1, it is determined whether or not it is the first program flow after selecting the highlight mode. When (M17) = 1, it is the first program flow. Therefore, as in the case of the spot auto mode, first, the bar display of the deviation from the standard exposure level corresponding to the maximum brightness value MIN (MBn) is performed. Therefore, 1/4 {(M
1) + (M9)}-(M8) + C9, MIN (M
The deviation from the standard exposure level corresponding to Bn) is calculated and stored in the area M3. Then, after the deviation (M3) is converted into bar display data by executing the subroutine h {(M3)}, the bar display data is displayed. Then, the interval command is executed, and then 1/4 {(M
1) + (M9)} + (M2)-(M8) + C9 + 7 is used to calculate the deviation from the maximum brightness value MIN (MBn) to the standard exposure level corresponding to 21 / 3Ev minus crocodile, and the result is stored in area M3. Store. Here, '7' added to the arithmetic expression is data corresponding to 21/3 Ev. Next, the subroutine h {(M3)} is executed to convert the deviation (M3) into display data, which is then displayed in a bar (see FIG. 66). Then, the detection flag M17 is reset to "0" immediately after highlight input. next,
Reset the shadow input detection flag to "1". Then, it is determined whether or not the release is made by the determination of I10 = 1. If the release is not made, the program returns to the mode determination program of FIG. 28 through-, and if the release is made, the-is obtained through-. Return to the exposure control program shown in FIG. After the exposure control program is completed, the program returns to the mode determination program shown in FIG. In the program flow after the second time in the highlight mode, I4 = 0, so I4
= No decision is made, and the program of "HIGH" display is entered through the decision of (M6) = -1.
The highest brightness value MIN (MB
The bar display of the deviation from the standard exposure level corresponding to n) is not displayed, and it is 21/3 from the maximum brightness value MIN (MBn).
Only the bar display of the deviation from the standard exposure level corresponding to Ev minus gutter is performed.

Next, the flow of the program when the shadow mode is selected in the spot manual mode will be described. Now, it is said that the flow of the program has advanced to the point display of the deviation of the current photometry point, and has reached the point shown in FIG. Next, the determination of I4 = 1 is answered in the negative, and by the determination of I5 = 1, it is determined whether or not the shadow input. Now, assuming that the flow of the program is the first time after selecting the shadow mode, I5 = 1, so the determination is YES, and then "1" is stored in the detection flag M18 immediately after the shadow input. This flag M
Reference numeral 18 is a flag for detecting whether or not it is the first program flow after the shadow mode is selected, and when it is '1', it indicates the first program flow. Next, a positive pulse is output to the output port O3 to reset the shadow input detecting flip-flop circuits (G ₁₉ , G ₂₁ ). Then, the sign of the shadow input detection flag M7 is reversed. Now, without or closed after the closing highlight switch SW _9, no When the shadow switch SW ₁₀ was closed odd number of times, the flag M7 is '-1', and the determination of (M7) = 1 To exit, and then "SHDW" is displayed (see FIG. 67). If the shadow switch SW ₁₀ is closed an even number of times, the flag M7 will be '1', and the judgment of (M7) = 1 will be answered in the affirmative, followed by "S".
HDW "erasure of the display is carried out. This" after the erasure of the display of SHDW ", fly to the program of the reset of the shadow input immediately after the detection flag M18, which will be described later (M18 ← 0). Now, shadow switch SW ₁₀ is an odd number of times It is assumed that the display is closed and "SHDW" is displayed. The bar display of the deviation from the standard exposure level corresponding to the lowest luminance value MAX (MBn) is performed in the same manner as the above, and 21/3 Ev from the lowest luminance value MAX (MBn).
A bar display of the deviation from the standard exposure level corresponding to the plus line is displayed. Since I5 = 0 in the second and subsequent program flows in the shadow mode, the program enters the “SHDW” display through the determination of (M7) = − 1, and (M18) = 1 Depending on the judgment, the bar display of the deviation from the standard exposure level corresponding to the lowest brightness value MAX (MBn) is not displayed, and the bar display of the deviation from the lowest brightness value MAX (MBn) to the display exposure level corresponding to 2 2/3 Ev plus broth is displayed. Only is done.

To summarize the program flow of the highlight mode or shadow mode in the spot manual mode described above, first, in the mode selection, the highlight mode is selected when the highlight command button 15 is pressed an odd number of times in succession. When the shadow command button 16 is pressed an odd number of times in succession, the shadow mode is selected. If the button is pressed an even number of times in succession, either mode is released. Also,
In the first flow after selecting the highlight mode, the deviation of the spot input value from the standard exposure level corresponding to the daylighting brightness value is displayed by a bar, and then 21 / 3Ev minus the light input brightness value of the spot input value. A bar display of the deviation from the corresponding standard exposure level is displayed. In the subsequent second and subsequent flows, only the bar display of the deviation from the standard exposure level corresponding to 21 / 3Ev minus gutter from the maximum brightness value of the spot input value is performed. Also, in the first flow after selecting the shadow mode, after the bar display of the deviation from the standard exposure level corresponding to the minimum brightness value of the spot input value is displayed once, 2 2 / 3Ev plus is found from the minimum brightness value of the spot input value. A bar display of the deviation from the standard exposure level corresponding to is displayed. In the second and subsequent consecutive flows, only the bar display of the deviation from the minimum luminance value of the spot input value to the standard exposure level corresponding to 2 @ 2/3 Ev plus gauze is performed. When the execution of the program in the highlight mode or the shadow mode is finished, it is next determined whether or not the shirt is released. If not released, the program returns to the mode determination program. If it is released, the manually set second (M8) is set in the timer counter, and then exposure control is performed according to the contents of the timer counter, and then the process returns to the mode determination program.

Next, a program for flash photography in the manual mode will be described. When the flash is attached in manual mode and the power of the flash is turned on, the input port I13
Becomes '1'. Therefore, in the mode discrimination program of FIG. 28, the determination of I13 = 1 is YES, and −
Through, the program branches to the strobe manual mode program shown in FIG. Here, first, it outputs a positive pulse to the output port O0～O3, spot mode detection, spot input detection, the highlight input detection and the flip-flop circuits of the shadow input detection (G _7,
G ₉ ; G ₁₁ , G ₁₂ ; G ₁₅ , G ₁₆ and G ₁₉ , G ₂₁ ), respectively. Next, the flash manual mode constant C31 is stored in the shooting mode detection flag M12. Then, (M13) = C22 and (M13)
= (M12) is determined to determine whether the power has just been turned on or the mode has been switched. If the power has been turned on or the mode has been switched, the display is reset. In resetting this display, as shown in FIG. 73, "MA
NU "is displayed, and fixed point indexes except" + "and"-"are displayed. In the electric circuit, it has already been described that the display of ( ₁₎ is a strobe charging completion display, which is displayed by the light emission of the light emitting diode D ₁ . Not immediately after turning on the power, and
If it is not immediately after the mode is switched, the display is not reset and the display of the next manually set time (M8) is immediately erased. Then, the manually set time data (I8) is input to the area M8. Next, the data (M
After 8) is tripled, it is stored again in area M8. Then, the manually set second data (M8) is displayed. FIG. 73 shows a case where the manually set second time is set to 1/30 second. Next, in each area M0, M1 and M2, the average Bv value BV
1, Sv-Av value (SV-AV) and Cv value CV are input respectively. Then 1/4 {(M0) + (M1)} +
After calculating the deviation from the standard exposure level by (M2)-(M8) + C8, this result is stored in the area M4. Next, after the deviation (M4) is converted into bar display data by executing the subroutine h {(M4)},
This is point-displayed on the segment column for bar display (see FIG. 73). Next, it is judged by I10 = 1 whether or not the shutter is released. If not released, the program returns to the mode discriminating program shown in FIG. 28 through-, and if released, the second screen is displayed through-.
9 Branch to the exposure control program in FIG. In the exposure control program, the exposure is controlled based on the manually set time (M8), and then the program returns to the mode determination program.

Next, the flow of the off mode program will be described. In the off mode, neither the auto mode nor the manual mode is set, so I0 ≠ 1, I1 ≠ 1, and the second mode
In the mode discrimination program shown in FIG. 8, I0 = 1
And the judgment of I1 = 1 ends with no. Therefore, next, the entire display is erased, and subsequently, the off mode constant C22 is stored in the photographing mode detection flag M12. Next, the memory hold detection flag M10 is "1".
And a positive pulse is output to each of the output ports O0 to O3, and each flip-flop circuit (G ₇ , G ₉₎ for spot mode detection, spot input detection, highlight input detection, and shadow input detection is output. ; G ₁₁ ,
G ₁₂ ; G ₁₅ , G ₁₆ and G ₁₉ , G ₂₁ ) are reset respectively. Then, after a while, the process returns to the beginning of the mode discrimination program through-and the loop is repeated. It should be noted that the control of the shutter is performed by hardware by an electric circuit.

Next, the program of the subroutine for displaying the bar shown in FIG. 44 will be described. In this program, first, the level of the input port I6 is determined.
When the memory mode is selected, I6 = 1, and then M10 = 0 is determined. In memory mode, (M10) = 1 sets memory, (M10) = 0
It becomes memory hold. Assuming that the memory set is present, "MEMO" is displayed next. Then, it is determined whether or not the display data (M3) is underexposed data by the determination of (M3) = C40. If the result is YES, the bar display start address storage area M14 stores the start address (C40- Store 1),
After displaying "LONG", the process returns. (M
3) If C40 is not underexposed and the constant C55 is stored in the start address storage area M14.
Here, the constant C55 is a constant larger than the range of the bar display start point by one. By the way, regarding the address of the memory area of the DRAM 85 corresponding to the segment column for bar display and the segments of "OVER" and "LONG", if the segment of "OVER" is the address X, the leftmost segment corresponds to the address X + 1. As you move to the right, the number increases by one. Therefore, the rightmost segment corresponds to the address X + 34, and the "LONG" segment corresponds to the address X + 35. The address of the memory area of the DRAM 85 corresponding to the segment column for point display is also the same. When the segment corresponding to "OVER" is the address Y, the address of the memory area of the DRAM 85 corresponding to the segment moves to the right. Also increases by one address, and the area of the memory area in the DRAM 85 of the segment corresponding to the rightmost "LONG" is Y
It is at +35. Constant C5 to the above area M14
After the store of 5, 1 is subtracted from the address (M14),
The result is stored again in the area M14. Then, DR
"1" is stored in the memory area of the address (M14) of AM85. As a result, the segment forming the bar display corresponding to the memory area at the address (M14) of the DRAM 85 is colored. Next, it is determined whether or not the address (M14) is the address of the memory area of the DRAM 85 corresponding to the "OVER" segment by the determination of (M14) = C41, and if (M14) ≠ C41, then (M1
By determining 4) = (M3), it is determined whether or not the bar display has ended. When the bar display is finished, the routine returns as it is, and when the bar display is not finished, the program returns to the address subtraction program (M14 ← (M14) -1) again, and the next segment corresponding to the address (M14) is colored. On the other hand, if (M14) = C41, it means that the bar is displayed up to the leftmost segment, so next, the number obtained by adding 1 to the constant C41 is stored in the area M14 and "OVER" is displayed. And then return.
To summarize the flow of the above program, the bar display sequentially develops colors from the right to the segment corresponding to the bar display data (M3). However, since this program is executed instantly, the human eye perceives the entire bar display as if it were displayed at once.

Next, in the case of the memory hold, the determination of M10 = 0 becomes yes, and then the display blinking cycle storage area M23
The display blinking cycle constant C80 is stored in. Next, the subroutine WAIT2 shown in FIG. 40 is executed, a predetermined delay time is created, and the blinking display flag M
Flipped to 22. Then, it is determined by (M22) = 1 whether it is the coloring period or the erasing period. If it is the coloring period, the program below the "MEMO" display is executed. If it is the erasing cycle, the entire "MEMO" display and bar display are erased in an instant, and then the process returns. In the next program flow of the bar display subroutine, the sign of the flag M22 is reversed, so the erased "MEM"
The "O" display and the bar display are colored, or the "MEMO" display and the bar display that have been colored are erased, and by repeating this, in the memory hold,
"MEMO" and the entire bar display will be displayed blinking at a cycle determined by the constant C80.

On the other hand, in a mode other than the memory mode, since I6 = 0, the determination of I6 = 1 is negative, and then (M3) <
By the determination of (M14), it is determined whether the displayed data (M3) is smaller than the previously displayed data (M14). Assuming that the program flow for the first bar display after the mode change is set, the address of the memory area of the DRAM 85 corresponding to the bar display start segment is initially stored in the area M14. Therefore, normally, (M3) <(M14), and then “LONG” is displayed. Next address (M1
1) is subtracted from 4) and the result is stored again in area M14. Then, "1" is stored in the memory area of the address (M14) of the DRAM 85, whereby the rightmost segment of the segment column for bar display is colored. Next, after executing the interval command, (M14)
By the determination of = C41, the bar display is performed up to the leftmost segment, and it is determined whether or not the "OVER" segment is displayed. Here, the constant C41 is "OVE
The address of the memory area of the DRAM 85 corresponding to the R ″ segment is shown. When (M14) ≠ C41, then (M14)
By the determination of 14) = (M3), it is determined whether or not the bar display is completed. When (M14) ≠ (M3), “1” is subtracted from the address (M14) again, and the result is stored in the area M14. Thereafter, the same program as described above is executed, and when (M14) = C41, "O
Since the "VER" display has been made, the DR corresponding to the bar display start segment for the next bar display
The address (C41 + 1) of the memory area of AM85 is stored in the area M14. At this time, it goes without saying that the bar display extends to the leftmost segment. Further, if (M14) = (M3) when (M4) ≠ C41, the bar display ends, and the program directly proceeds to the following. Here, to summarize the mode of bar display, in the first bar display after the mode switching, the bar display starts from the rightmost segment and sequentially extends one segment at a time to a predetermined position. The interval command is a delay command for making it possible to confirm the movement of the bar display. In the next bar display, the bar display starts moving from the tip of the currently displayed bar display.
Next, by the judgment of (M3) = C41, the display data (M
It is determined whether or not 3) corresponds to overexposure, and in the case of Yes, the following program is executed to blink the "OVER" display. First, the blinking cycle constant C70 is stored in the display blinking cycle storage area M23. next,
The subroutine WAIT2 shown in FIG. 40 is executed to create a predetermined delay time and the blinking display flag M22.
Invert the sign of. Then, the content of the flag M22 is discriminated. When (M22) = 1, the "OVER" display is performed, and when M22 ≠ 1, the "OVER" display is cleared. Since the sign of the flag M22 is inverted every time the program flows, the "OVER" display blinks. When (M3) ≠ C41,
Only "OVER" is continuously displayed. After the display or deletion of "OVER", the program returns.

Next, the flow of the program when (M3) <(M14) is not described.

If (M3) <(M14), then (M
3)> (M14), display data (M
It is determined whether or not 3) is larger than the previously displayed data (M14). If (M3)> (M14) is not satisfied, the data to be displayed is the same as the previously displayed data, and therefore the process directly returns. Also, (M3)> (M1
In the case of 4), first, "0" is stored in the memory area of the address (M14) of the DRAM 85, and the leading segment of the bar display is erased. Next, after executing the interval command, it is next determined by (M14) = C40 whether or not the rightmost segment of the bar display has been erased. If (M14) = C40, the area is determined. DRAM corresponding to the start segment of the next bar display on M14
The address (C40-1) of the memory area 85 is stored, and the program at the subsequent stage is exited. Also, (M14) ≠ C
If it is 40, "1" is added to the address (M14), the area is stored in the area M14, and the address (M14) is updated. Next, by (M14) = (M3), it is determined whether or not the leading edge of the bar display has reached the position corresponding to the data (M3). If (M14) ≠ (M3), then again. DRA
"0" is stored in the memory area of the address of M85 (M14), and the program described above is repeated. A predetermined delay time is created by the execution of the interval command, the display of the segment constituting the bar display is erased at a speed at which the bar display is sequentially viewed from the left end, and the predetermined bar display is performed. Then, by the judgment of (M3) = C40, the display data (M
It is determined whether or not 3) corresponds to underexposure, and if it is underexposure, the "LONG" display blinks, and if not, the "LONG" display remains continuously displayed. This program is the same as the case of the above-described overexposure, and therefore its detailed description is omitted. To summarize the mode of the bar display, the area M1
4 shows the DRA corresponding to the segment at the top of the bar display
The address of the memory area of M85 is stored, and the bar display moves from the tip unless the mode is changed. Immediately after the mode is changed, the area M14 is initialized and the bar display starts from the rightmost segment.

As described above, according to the present invention, the exposure correction operation member is provided in the camera that stores the exposure element at the time of the first shooting and controls the exposure at the time of the subsequent shooting based on the exposure element, and stores the exposure correction operation member. Since the signal for correcting the exposure level is added to the exposed exposure element, it is possible to shoot at a desired exposure level. Therefore, the conventional drawbacks described at the beginning of the specification can be eliminated. Also,
Conventionally, the exposure correction is generally input by operating the same operation member as the film sensitivity, but in the present invention, the operation member for inputting the film sensitivity and the operation member for inputting the exposure correction are separately provided. Therefore, there is an effect that only the shutter speed can be changed without changing the film sensitivity value or the like according to the correction amount.

[Brief description of drawings]

FIG. 1 is a front view of a camera showing an embodiment of the present invention, FIG. 2 is a plan view of the camera shown in FIG. 1, and FIG. 3 is a view inside the camera shown in FIG. FIG. 4 is a front view of a photometric light-receiving device provided in the optical system shown in FIG. 3, and FIG. FIG. 6 is a block diagram showing an outline of a configuration of an electric circuit arranged in the camera shown in FIG. 6, FIG. 6 is a block diagram showing an internal configuration of a microcomputer as a central processing unit shown in FIG. FIG. 7 is an electric circuit diagram showing an interface around the microcomputer shown in FIG. 6, FIG. 8 is an electric circuit diagram of the head amplifier circuit shown in FIG. 5, and FIG. An electric circuit diagram of the analog exposure information introduction circuit and the second selection circuit shown in FIG. FIG. 0 is an electric circuit diagram of the strobe over / under determination circuit and the first comparison circuit shown in FIG. 5, and FIG. 11 is an electric circuit diagram of the power supply hold circuit shown in FIG. 12 is an electric circuit diagram of the trigger timing adjusting circuit shown in FIG. 5, FIG. 13 is an electric circuit diagram of the battery check circuit and the power source hold releasing circuit shown in FIG. 5, and FIG. Is an electric circuit diagram of the strobe determination circuit shown in FIG. 5, and FIG. 15 is an electric circuit diagram of the first selection circuit, magnet drive circuit and strobe control circuit shown in FIG. FIG. 16 is an electric circuit diagram of the timer circuit shown in FIG. 5, FIG. 17 is an electric circuit diagram of the D-A conversion circuit shown in FIG. 5, and FIGS. i) is output from the timer circuit shown in FIG. FIGS. 19A and 19B are time charts showing waveforms of various timer signals. FIG. 19A and FIG. 19B show display segment electrodes and display segment electrodes of the liquid crystal display plate forming the main body of the photographing information display device 39 shown in FIG. FIG. 20 is a plan view showing the back electrode, FIG. 20 is a plan view of the principal part showing the correspondence relationship between the display segment electrode and the back electrode shown in FIGS. 19 (A) and (B), and FIG. FIG. 22 is an electric circuit diagram of the liquid crystal drive circuit shown in FIG. 6, FIG. 22 is an electric circuit diagram of a main part showing the signal synthesizing circuit shown in FIG. 21, and FIG. FIG. 24 is an electric circuit diagram of a common signal output circuit in the liquid crystal drive circuit shown in FIG. 6 and FIG. 25 (a). ) To (m) are the respective elements in the liquid crystal drive circuit shown in FIGS. 21 to 24. FIG. 26 is a time chart showing the output waveform of the seed signal, FIG. 26 is a diagram showing a counting method at the shutter speed in the memory mode photographing, and FIG. 27 is an outline of the program in the microcomputer shown in FIG. FIG. 28 is a flow chart showing in detail the mode discrimination program in the flow chart shown in FIG. 27, and FIG. 29 shows the average direct auto photography mode program in the flow chart shown in FIG. FIG. 30 is a detailed flowchart, FIG. 30 is a detailed flowchart in the spot automatic shooting mode with spot input in the flowchart shown in FIG. 27, and FIG. 31 is a flowchart shown in FIG. No spot input in spot auto shooting mode FIG. 32 is a detailed flowchart for the case of highlight reference shooting mode and shadow reference shooting mode, which is executed subsequent to the flowchart in the spot auto shooting mode shown in FIG. 31 without spot input. FIG. 33 is a flow chart showing the program in detail, FIG. 33 is a flow chart showing the program in the strobe auto photographing mode in detail in the flow chart shown in FIG. 27, and FIG. 34 is a normal flow chart in the flow chart shown in FIG. 27. FIG. 35 is a detailed flowchart of the program in the manual shooting mode. FIG. 35 is a detailed flowchart of the flowchart shown in FIG. 27 when spot input is performed in the spot manual shooting mode. In the flowchart shown in FIG. 37 is a detailed flowchart in the spot manual shooting mode without spot input, and FIG. 37 is a highlight executed after the flowchart in the spot manual shooting mode without spot input in FIG. 36. FIG. 38 is a flowchart showing in detail the programs for the reference photographing mode and the shadow reference photographing mode. FIG. 38 is a flowchart showing in detail the program for the strobe manual photographing mode in the flowchart shown in FIG. 27. FIG. 40 is a flowchart showing a detailed program of the subroutine WAIT1, which is executed in the flowchart shown in FIG. 33, and FIG. 40 is a subroutine WAI shown in FIG. 39.
T1, a flowchart showing the detailed program of the subroutine WAIT2 executed in the subroutine WAIT3 shown in FIG. 41 and the bar display subroutine shown in FIG. 44, FIG. 41 is shown in FIGS. 31 and 36 above. 42 is a flow chart showing a detailed program of a subroutine WAIT3 executed in the flow chart shown in FIG. 42. FIG. 42 is a detailed program of a subroutine for counting actual exposure time executed in the flow chart shown in FIG. 29. FIG. 43 is a flow chart showing a sub-routine f {(M3)} executed in the flow chart shown in FIG. 28 to FIG. 38.
44 is a flow chart showing a detailed program of a subroutine for displaying a bar, which is executed in the flow charts shown in FIGS. 28 to 38, and FIGS. 45 to 47. The figures respectively show the display modes of the photographing information display device in the average direct auto photographing mode. FIG. 45 shows the Tv value bar display in the display range, and FIG. 46 shows the Tv value bar display. When it is over the display range, FIG. 47 shows the case where the bar display of the Tv value is under the display range, respectively. FIGS. 48 to 50 are the photographing information display devices in the spot auto photographing mode. Fig. 48 shows the respective display modes of Fig. 48, and Fig. 48 shows the case where the bar display of the average Tv value is made within the display range. When the bar display of the uniform Tv value is over the display range, FIG. 50 shows the case where the correction is applied, and FIGS. 51 to 54 show the spot reference photographing mode in the highlight reference photographing mode. FIG. 51 shows the display modes of the photographing information display device when is selected, and FIG. 51 shows a state where the bar display of the average Tv value is once extended to the position corresponding to the maximum brightness value, and FIG. From the state shown in the figure, the bar display of the average Tv value has moved by 21/3 Ev on the minus side, and in FIG. 53, the Sv-Av value is changed from the state shown in FIG. 54 is a state in which the bar display is shifted, FIG. 54 shows a state in which correction is added from the state shown in FIG. 53, and FIGS. 55 and 56 show the spot reference photography mode in the shadow reference photography mode. FIG. 55 shows states of display of the photographing information display device when selected, and FIG. 55 shows a state where the bar display of the average Tv value has once returned to the position corresponding to the minimum luminance value, and FIG. 56 shows FIG. 55. Fig. 57 to Fig. 59 show the state where the bar display of the average Tv value shifts by 2 2/3 Ev from the state shown in Fig. 5, respectively. Figs. 57 to 59 show the display of the photographing information display device in the direct auto memory photographing mode. FIG. 57 shows states of the memory set, and FIG.
FIG. 8 shows a state of memory hold, FIG. 59 shows a state of correction by memory hold, respectively. FIG. 60 shows a display mode of the photographing information display device in the spot auto memory photographing mode, 61th. FIG. 62 and FIG. 62 respectively show the display modes of the photographing information display device in the normal manual photographing mode. FIG. 61 shows a state in which the bar display of the deviation from the standard exposure level is made, and FIG. FIG. 63 to FIG. 65 respectively show the states in which the bar display of the deviation with respect to the exposure level is corrected, and FIG. 63 shows the display mode of the photographing information display device in the spot manual photographing mode. Shows a bar display of the arithmetic mean of the deviation from the standard exposure level.
FIG. 63 shows a state where spot input is newly performed from the state shown in FIG. 63, FIG. 65 shows a state where correction is added from the state shown in FIG. 64, and FIG. 66 shows a spot manual photographing mode. FIG. 67 is a diagram showing a display mode of the shooting information display device when the highlight reference shooting mode is selected, and FIG. 67 shows a display mode of the shooting information display device when the shadow reference shooting mode is selected in the spot manual shooting mode. FIGS. 68 to 72 respectively show the display modes of the photographing information display device in the flash auto photographing mode, and FIG. 68 shows a state in which deviation points from the standard exposure level are displayed. FIG. 69 is a state in which the correction is added from the state shown in FIG. 68, FIG. 70 is a state in which exposure is over after photographing, and FIG. 71 is a state after photographing. Out under the A state, the 72 figure the state which was a proper exposure after shooting, respectively, 73 is a drawing showing a display mode of the photographing information display device in a flash manual shooting mode. 5 …… Aperture value setting ring 7 …… Manual shutter time setting ring 10 …… Camera 11 …… Shutter release button 13 …… Memory command operation knob 14 …… Spot input button 15 …… Highlight command button 16 …… Shadow Command button 18: Film sensitivity setting dial 21: Shooting mode switching operation knob 22: Exposure compensation operation knob 39: Shooting information display device (shooting information display section) 41: Photometric light receiving device 50: Micro computer (CPU) BV1 ...... average luminance value CV ...... correction value D ₁ ...... charge completion display light-emitting diode according to the luminance value BV2 ...... spot metering by metering H0~H2 ...... common signal J0~J38 ...... segment drive signal PD ₁ ...... average photometric photovoltaic element PD ₂ ...... spot photometry photovoltaic element RE ₀ ~RE ₂ ...... back electrode EG ₁ ~SEG ₁₀₁ ...... segments (display region) SV-AV ...... calculation value of film speed value and the aperture SW ₁ ...... release switch SW ₂ ...... trigger switch SW ₃ ...... manual switch W ₄ ...... Auto Switch SW ₅ ...... Battery check switch SW ₆ ...... Memory switch SW ₇ ...... Clear switch SW ₈ ...... Spot input switch SW ₉ ...... Highlight switch SW ₁₀ ...... Shadow switch

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-51-117628 (JP, A) JP-A-52-58529 (JP, A) JP-A-57-30819 (JP, A) JP-A-54- 68631 (JP, A) JP-A-54-139732 (JP, A) JP-A-54-48532 (JP, A)

Claims (3)

[Claims] 1. A photometric device for measuring the brightness of a subject, an operating member for selecting an exposure level for storing and photographing mode, an information setting device for setting aperture value information and correction amount information, and the operating member. The exposure time during exposure control during film exposure in the first shooting after selecting the exposure level storage photography mode, and aperture value information during exposure control set by the information setting means and correction. Storage means for storing the amount information, a release operation member for manually releasing the exposure level memory shooting mode selected by the operation member, and unless the release level storage shooting mode is released by the release operation member, In the next and subsequent shootings, the exposure time, the aperture value information and the stored correction amount information stored in the storage means, and the subsequent and subsequent shootings Using the latest aperture value information and the latest correction amount information set by the information setting means, if the stored correction amount information and the latest correction amount information are the same, the same exposure as that at the time of the first shooting A calculation unit that calculates an exposure control value that becomes a level, and calculates an exposure control value that becomes an exposure level according to the difference when there is a difference between the stored correction amount and the latest correction amount. An exposure control device for a camera, comprising: exposure control means for performing exposure control based on the exposure control value. 2. A photometric means for measuring the brightness of an object and outputting the brightness information, an operation member for selecting an exposure level storing and photographing mode, and an information setting for setting exposure control element information and correction amount information. Means, a storage means for storing the brightness information used in the first shooting after operating the operation member to select the exposure level storage shooting mode, and the exposure selected by the manual operation member. A release operation member for manually releasing the level memory photography mode, and unless the release operation member releases the exposure level memory photography mode, the stored brightness information stored in the storage means in the next and subsequent photography, The exposure compensation is performed based on the latest exposure control element information and the latest correction amount information set by the information setting means at the time of the next and subsequent photographing. If the exposure control value is not performed, the exposure control value for obtaining the appropriate exposure level at the time of the first shooting is calculated, and if the exposure correction is performed, the exposure control value for obtaining the exposure level according to the latest correction amount information is calculated. An exposure control device for a camera, comprising: an arithmetic means for performing an arithmetic operation; and an exposure control means for performing an exposure control based on the exposure control value calculated by the arithmetic means. 3. The exposure control device for a camera according to claim 2, wherein the information input means inputs aperture value information and film sensitivity information as the exposure control element information.