JPH0664527B2 - Memory control circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a memory control circuit for controlling data reading in a memory system including a plurality of memory planes such as a graphic memory in a display device.

(B) Prior art In the graphic display, for example, Japanese Patent Laid-Open No. 59-
As disclosed in Japanese Patent No. 84295, the graphic memory is usually composed of a plurality of R, G, B, and I memory planes, and each memory plane is commonly connected to a data bus. And these multiple memory planes
Mapped on different address space of CPU, CP
For a U read request, data from the only memory plane is read onto the data bus.

(C) Problem to be Solved by the Invention In a system in which a plurality of memory planes are commonly connected to a data bus, unlike the conventional case, if these memory planes are mapped in the same address space of the CPU, all the planes are transferred from the CPU. However, it is possible to write the same data at the same time. However, when reading from multiple planes at the same time, data collision occurs on the data bus. Therefore, only one plane must be designated when reading.

Therefore, it is conceivable to have a bit corresponding to each plane, store plane selection data for selecting a plane by turning the bit on and off, and control the reading from the memory plane according to the content of this data. . However, the setting to the register is performed by software, and if this software mistakenly sets the plane selection data in which a plurality of bits are on to the register, the data collision on the data bus cannot be avoided.

(D) Means for Solving the Problem The present invention has a plurality of memory planes connected to a data bus and capable of simultaneous reading, and bits corresponding to the plurality of memory planes. A plane register that stores plane selection data for selection and a control circuit that controls reading of data from the plurality of memory planes according to the plane selection data are input from the plane register. Inserting a priority circuit for selecting and outputting only one on-bit according to a predetermined priority from a plurality of on-bits of the plane selection data between the plane register and the control circuit, It solves the problem.

(E) Action In the present invention, even if plane selection data for selecting a plurality of planes is erroneously set in the plane register due to a software error, the priority circuit selects only one plane for the control circuit. Since data is input, data collision on the data bus is prevented.

(F) Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention.
(1) is a 16-bit CPU, (2) is composed of four planes (2a) (2b) (2c) (2d) for I, R, G, B, and all planes are as shown in FIG. Graphic memory mapped on the same address space of CPU (1), (3) address bus ABUS, (4)-(8) 16-bit data bus DBUS, (9) address from CPU (1) And a read request signal RDRE according to the read command CMD
A decoder for outputting Q and strobe signals STBA to STBC, (10) is designated 4-bit color data CCI,
Color register for setting CCR, CCG, CCB, (11) indicates a mode register for storing mode data designating mode switching between comparison read mode and normal read mode, and (12) indicates a plane to be selected. A plane register for storing plane selection data PEI, PER, PEG, PEB, (13) is a signal RAS, a signal CAS, and an output enable signal OEI, OER according to the read request signal RDREQ and the mode data CMP / ▲ ▼. , OEG, OEB, latch pulse R
DLAT, clear signal RRCLR, timing signal IG
A sequencer circuit that outputs / ▲ ▼ and IR / ▲ ▼. In this embodiment, the graphic memory (2)
Is composed of a dual port DRAM.

Further, in FIG. 1, (14) is a read request signal RD.
Depending on REQ and mode data CMP / ▲ ▼
During normal read, plane selection data PEI, PE
A plane priority circuit that selectively outputs only one on-bit from a plurality of on-bits “1” of R, PEG, and PEB according to a predetermined priority order, and outputs the input plane selection data as it is during comparison read, ( 15)
Is the 4-bit output of the color register (10) input to the first input terminal and the timing signal IG /
Select signal CM according to ▲ ▼, IR / ▲ ▼
A selector that outputs as a PE and also selects the 4-bit output of the plane priority circuit (14) input to the second input terminal according to a timing signal and outputs as a signal PE. (16) is a 4-bit signal CAS. Output XP
It masks with EI, XPER, XPEG, XPEB, sends the masked signals CASI, CASR, CASG, CASB to the corresponding planes respectively, and outputs the input signal CMPE in the comparison read mode according to the mode data CMP / ▲ ▼. The signal CMPEN is output as it is, the latch pulse RDLAT is masked by the signal PE, the masked latch pulse RDLT is transmitted, and in the normal read mode, a signal of "0" level is output as the output signal CMPEN and the latch Pulse RDLA
The control circuit outputs T as it is as a latch pulse RDLT.

Further, (17) and (18) are bidirectional buffers, (1900) (1901) ~
(1915) is each bit output VR0, VR1, ..., VR of 16-bit parallel data read to the data buses (5) and (6).
Input 15 at each end and control circuit (16) at the other end
Exclusive OR for inputting signal CMPEN from
The gates (EX-OR gates), (2000) (2001) to (2015) have outputs C0, C1, ..., C1 of the EX-OR gates at one end.
The OR gates (2100), (2101) to (2115) each input 5 inputs their own outputs to the other ends of the OR gates (2000) (2001) to (2015), and the outputs I0, I1, ...,
I15 is a latch circuit that latches in response to a latch pulse RDLT, and these latch circuits have a clear signal RRCL.
The contents are cleared by R.

The operation of this embodiment will be described below with reference to the timing charts of FIGS. 2 and 3.

First, the comparative read operation shown in FIG. 2 will be described.

From the CPU (1) through the data bus DBUS, "1" indicating the comparison read mode is set as the mode data CMP / ▲ ▼ in the mode register (11), and the color register (1
The color data CCI to CCB of the specified color is stored in (0) and the plane selection data PEI to PEB is stored in the plane register (12).
Set. For example, I, R, B of all 4 planes
When selecting three planes, as shown in FIG. 2 (A) (A), as (PEI, PER, PEG, PEB),
Set (1,1,0,1). After setting these data, specify the address of the graphic memory (2) and
When a read command CMD is issued from PU (1), a read request signal RDREQ is output from the decoder (9) to the sequencer circuit (13).

Then, the sequencer circuit (13) outputs the request signal R
DREQ and "1" level mode data CMP / ▲
According to ▼, the signal RAS shown in FIG. 2 (F) is output commonly to all the planes (2a) to (2d), and the signal CAS shown in FIG. 2 (K) is output to the control circuit (16). . Furthermore, the second
As shown in the figures (U), (S), (S), and (S), the output enable signals OEB, OEG, OER, and OEI are output to the corresponding planes in a predetermined order in a time division manner. In synchronization with this signal, a 2-bit timing signal (IG / ▲
▼, IR / ▲ ▼) are sequentially changed in a predetermined order as (0,0) (1,0) (0,1) (1,1) as shown in Fig. 2 (SO) (TA). And output. Further, the sequencer circuit (13) outputs the latch pulse RDLAT four times as shown in FIG. 2 (d) in accordance with the time-divisional timing of the output enable signal.

Further, the control circuit (14) outputs the signal CAS to the outputs XPEI, XPER, XP of the plane priority circuit (14).
The masked CAS signals CASI, CASR, CASG, and CASB are masked by EG and XPEB, respectively, and sent to the corresponding planes.

Therefore, from the maximum four planes in which the CAS signal is active, B, G, R, and I are sequentially arranged in the order of 1 in each plane.
Data of 6 pixels is V on the data buses (5) and (6) in time division.
It is read as D _0-15 and VR _0-15 . For example, as in the above example, B,
When the three planes of R and I are selected, the parallel 16-bit data of each plane of B, R, and I is divided into the first, third, and fourth time divisions, as shown in FIG. It is read at various timings.

On the other hand, in the selector (15), the timing signal (IG / ▲
When ▼, IR / ▲ ▼) changes to (0,0) (1,0) (0,1) (1,1), the first output CMPEN as shown in FIG.
, Color data C corresponding to planes B, G, R, and I, respectively.
Since CB, CCG, CCR, and CCI are sequentially read one bit at a time, the EX-OR gates (1900) to (1915).
Then, parallel 16-bit data from CCB and B plane, parallel 16-bit data from CCG and G plane,
Parallel 16-bit data from CCR and R plane, CC
I and the parallel 16-bit data from the I plane will be detected in a time-sharing manner. Specifically, EX
-The outputs of the OR gates (1900) to (1915) are "0" when the input data match, and "1" when they do not match,
The match result of each of these bits is OR gate (2000)-(2015)
It is held in each of the latch circuits (2100) to (2115) via.

That is, the latch circuits (2100) to (2115) receive the signal RRCLR (see FIG. 2) before four coincidence detections for all planes.
(TE)) is input to clear the content, and after clearing, the result of matching detection between CCB and B plane data is first latched in response to the first latch pulse RDLT. If the latched content is "0" indicating a match, C
The coincidence detection result between the CG and the G plane data is latched according to the second latch pulse RDLT, and hereinafter, as long as the latch result is “0”, according to the third and fourth latch pulse RDLT. Then, the match detection result between CCR and R plane data and the match detection result between CCI and I plane data are sequentially latched. However, the latch circuit (2
100) to (2115) are connected to the feedback loops that feed back their own outputs via the OR gates in the previous stage, so that "1" indicating a mismatch even at least once in the four match detections is latched. Then, the mismatch result "1" remains held in the latch circuit regardless of the subsequent match detection result.

In other words, in the latch circuits (2100) to (2115) for 16 pixels,
"0" is held when the color of each pixel is the designated color, and "1" is held when it is not the designated color.

Therefore, the CPU (1) receives the color determination result for 16 pixels from the latch circuits (2100) to (2115) as a response to one read command.

By the way, as described above, in the selector (15), the timing signals (IG / ▲ ▼, IR / ▲ ▼) are (0,0) (1,0)
When it changes from (0,1) to (1,1), the plane selection data XPEB, XPEG, XPER, and XPEI are sequentially read to the second output PE, and this output causes the sequencer circuit (13) in the control circuit (16). ) Masking the latch pulse RDLAT. Therefore, the masked latch pulse RDLT
In the above, sending of the pulse corresponding to the non-selected plane is prohibited, and the match detection result of the non-selected plane is the latch circuit.
It will not be latched by (2100) to (2115).

For example, plane selection data (PEB, PEG, PE
R, PEI) is (1,0,1,1) as in the above example, the output PE is as shown in FIG. 2 (n), and the latch pulse RDLT of the latch pulse RDLT is as shown in FIG. 2 (ne). The second pulse is no longer transmitted, and therefore the latch circuits (2100) to (2115) hold the coincidence detection results of the three planes B, R, and I except the non-selected plane G.

Incidentally, FIG. 2 (T) shows an example in which the data of the R plane (2b) among the data of the B, R, and I3 planes of the nth pixel is different from the R plane bit CCR of the color data.
The output RDn of the nth latch circuit is the latch pulse RD.
In response to the third pulse of LT, it becomes "1" indicating a mismatch.

In the above, the embodiment for performing the pixel color determination has been described.
The pixel density determination can be performed in the same manner.

Next, the normal read operation shown in FIG. 3 will be described.

From the CPU (1) via the data bus DBUS to the mode register (11) as mode data CMP / ▲ ▼,
"0" indicating the normal read mode is set, and plane selection data for selecting a desired one plane is set in the plane register (12). After this setting, when the address of the graphic memory (2) is designated and the read command CMD is issued from the CPU (1), the read request signal RDREQ is sent from the decoder (9) to the sequencer circuit (13) as in the comparison read mode. Is output to.

However, in this normal read mode, the sequencer circuit (13) generates RAS and CAS signals having a pulse width shorter than that in the comparison read, as shown in FIG. Each plane (2a) ~ (2d) as shown in Fig. 3 (U)
Output enable signal O at the same timing.
Send EI to OEB. Furthermore, in this mode, the third
As shown in the figure (h), only one pulse of the latch pulse RDLAT is output and the timing signals IG / ▲ ▼, IR / ▲
▼ is not output.

Further, in the control circuit (16), the signal CAS is masked with the plane selection data XPEI to XPEB, and the masked CAS signals CASI to CASB are sent to the corresponding planes, as in the case of reading.

Therefore, parallel data is read from the graphic memory (2) from only one desired plane, and data is not read from the non-selected plane. Then, the read parallel data passes through the data bus (5), the bidirectional buffer (17), and the data bus (6), and each bit output is the EX-OR gates (1900) to (1915) as in the comparison read. ), But
Since the signal CMPEN fixed at the level "0" is input to the other ends of these gates, the parallel data read from the desired one plane of the graphic memory (2) is output to the output of the EX-OR gate. It will be output as is.

Also, the latch circuits (2100) to (2115) use the clear signal RRCL.
After clearing by R, each output of the EX-OR gates (1900) to (1915) is latched according to only one latch pulse RDLT, and as a result, the parallel data read from one plane is directly stored in the latch circuit (2100). ) To (2115).

Therefore, in this mode, just like a normal read,
As a response to the read command, the CPU (1) takes in the parallel data from the selected one plane as it is.

For example, plane selection data (PEI, PER, PE
(1,0,0,0) as a G, PEB) plane register (12)
When set to, EX-OR gates (1900) to (1915),
OR gate (2000) ~ (2015), latch circuit (2100) ~ (2115)
As shown in FIGS. 3 (a), 3 (b), and 3 (d), the parallel data from one plane (2a) is output to the output of FIG.

By the way, specifically, the plane priority circuit (14), as shown in FIG.
An AND gate (22) for inputting REQ and an inverted signal of the mode data CMP / ▲ ▼, and an output G ₀ of this AND gate (22) are commonly input to one end and an output from the plane register (12) to the other end. NAND gates (23), (24) and (25) for inputting PEI, PER, PEG and PEB respectively, and PER
And an output G ₁ are inputted into the AND gate (26), PEG and outputs G ₁ and G ₂ are inputted into an AND gate (27), and PEB and outputs G ₁ , G ₂ and G ₃ are inputted into an AND gate (28 ) And.

Therefore, if PEI is "1" (on), XPER, X
If PEG and XPEB are fixed to "0" (off) and PER is "1" at the same time, XPEG and XPEB
However, if PEG is "1", XPEB is "0".
Fixed to. That is, PEI, PER, PEG, PE
According to the priority order of B, only one ON bit of the four input bits is selected and output. Therefore, for example, FIG.
As shown in (a) and (b), plane selection data (PEI, P
Even if (1,0,0,1) is mistakenly set as (ER, PEG, PEB), the plane priority circuit (14) outputs only the PEI having the higher priority as an on-bit. , The data bus (5) is shown in FIG.
As described above, only the parallel data from one plane is read, and the collision on the data bus (5) is avoided.

(G) Effect of the Invention According to the present invention, even if erroneous data is set in the plane register by software, it is possible to reliably prevent data collision on the data bus, and to improve reliability. A highly reliable system can be built.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG.
FIG. 4 is a timing chart of the comparative read operation in the embodiment, FIG. 3 is a timing chart of the normal read operation in the embodiment, FIG. 4 is a concrete circuit diagram of the plane priority circuit, and FIG. 5 is a memory map of the graphic memory. is there. (1) ... CPU, (2) (2a) to (2d) ... graphic memory,
(4) to (8) ... Data bus, (10) ... Color register, (11) ... Mode register, (12) ... Plane register, (13) ... Sequencer circuit, (14) ... Plane priority circuit, (15) … Selector, (16)… Control circuit, (1900) to (1915)… E
X-OR gate, (2000)-(2015) ... OR gate, (2100)
-(2115) ... Latch circuit, (22) (26)-(28) ... AND gate, (23)-(25) ... NAND gate.

Claims (1)

[Claims] 1. A plurality of memory planes connected to a data bus and mapped on the same address space of a CPU,
Each having a bit corresponding to each of the plurality of memory planes,
A memory control circuit including a plane register that stores plane selection data for selecting a plane by turning the bit on and off, and a control circuit that controls reading of data from the plurality of memory planes according to the plane selection data. , A priority circuit that selects and outputs only one on-bit from a plurality of on-bits of the plane selection data input from the plane register in accordance with a predetermined priority order. A memory control circuit characterized by being inserted between them.