JPH0664529B2 - Rounding adder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention is applied when the output data word length (kbit. K <N) is limited with respect to the input data word length (Mbit.). The present invention relates to an adder circuit that outputs a rounding result according to a word length.

(Prior Art) In the two-input addition, when it is necessary to round the output data due to the relationship of the subsequent circuit, one of the following methods has been conventionally used.

(1) Truncation type addition method The configuration is shown in Fig. 5 (a). This is composed of a 2-input adder for inputting and adding an upper kbit from N-bit input data A and B to obtain a kbit sum and a carry, and a lower N-kbit truncation unit. With this configuration, since the lower part of the effective data word length is truncated from the input data, the upper kbit addition is performed, so the lower N-kb
It is not necessary to calculate the data for it. Therefore, the adder circuit and the calculation time can be reduced accordingly.

(2) Rounding type addition method The configuration is shown in Fig. 5 (b). This is a 2-input adder 1'for lower N-kbits for N-bit input data A and B.
And an upper kbit 2-input adder 2'and a half adder array 3 '. The 2-input adder 1'adds the lower N-kbits of the input data A and B, generates only the 1 _- bit of the carry C _{Nk and} the 1-bit of the sum S _Nk-1 from the most significant digit, and respectively adds the upper 2-inputs. Input to the least significant digit of the device 2 '. The 2-input adder 2'adds the upper kbits of the input data A and B, respectively, and the carry C _Nk from the lower 2-input adder _1'and the 4 data of the sum S _{Nk-1 to obtain} kbit.
Get the sum output of and the carry output from the most significant digit. Since the 2-input adder 2'has four inputs to the least significant digit,
Install the half adder array 3'in front of the input adder 2 ',
The configuration is such that addition is performed after the number of addition inputs is three or less. In this method, as a result, the input data word length (Nbit) is once added, and thereafter, in order to reduce the error, the sum S _Nk-1 of ₁ bit lower than that is added to the least significant digit of the effective data word length. Corresponding to the above, the rounding effect equivalent to rounding in the decimal number in the effective data word length is obtained. At this time, the rounding error becomes the minimum unbiased.

(Problems to be solved by the invention) However, in this conventional technique, in the case of (1), the method of completely truncating the lower order and the least significant digit C of the effective data block for compensating for the average value of the truncating section are used. There is a method of unconditionally adding 1 to _Nk to eliminate the deviation. In the former case, the error in the output result is large because the calculated value of the truncation part is unknown, and the result is deviated because the value of the truncation part is not compensated. In the latter case, the deviation disappears, but the error is still large.

In the case of (2), the addition is performed in two stages of a half adder and a two-input adder, and the two-input adder 2 ′ starts from the time when the most significant digit sum S _Nk−1 is calculated by the two-input adder 1 ′. Carry goes up from the least significant digit to the most significant digit. Therefore, the calculation time is slow because of the calculation time of the 2-input adder 1 '+ the calculation time of the 2-input adder 2'.

It had a drawback.

(Means for Solving Problems) In view of the above points, an object of the present invention is to provide a rounding adder which has both small rounding error and no deviation and which has both rounding result and high speed.

FIG. 1 is a conceptual diagram of the rounding adder of the present invention. Reference numeral 1 is a usual two-input adder, 11 is a sum of the most significant digit, and 12 is a carry sent from the most significant digit to the high order. Reference numeral 2 is a selection signal generation circuit, the output of which is connected to the 3-1 selector 4. A portion configured by the 2-input adder 1 and the selection signal generation circuit 2 corresponds to the rounding correction block in "Claims". Reference numeral 30 is a two-input adder that calculates the sum of inputs, 31 is the sum +1, and 32 is the sum +2. The 3-1 selector 4 selects one of the outputs of the two-input adders 30, 31, 32 by the output signal of the selection signal generation circuit 2. 2-input adders 30, 31, 32 and 3
-1 selector 4 corresponds to a valid data block in "Claims".

Generally, in carry carry adder, two adders are prepared for each block, and carry from the lower block respectively It is calculated in advance on the assumption that the above condition is satisfied, and one of the two assumed outputs is selected and output when the carry from the lower block is determined. The present invention applies this idea to a rounding adder. In other words, in order to minimize the rounding error (in other words, to obtain the same result as rounding in decimal), the highest digit of the rounding correction block must be The carry and the sum from must be added to the least significant digit of the valid data block. About the execution of the addition, the three states of the sum of the carry and Sam On the other hand, it is possible to employ a method in which the value of each valid data block is calculated in advance. Thereby,
A rounding result with a small error and an unbiased result can be obtained at high speed. This is a feature of the present invention.

In Figure 1, the input data A, B part A _H of the upper kbit corresponding to the output valid data word length, respectively, part A _L of the lower N-kbit for correction and rounding B _H, is divided into a B _L. The rounding correction portions A _L and B _L of the input data A and B are added by the 2-input adder 1, and the sum 11 of the most significant digit and the carry 12 sent from the most significant digit to the upper digit are calculated. These two signals (1 bit each) are added by the selection signal generation circuit 2, and the result becomes the selection signal of the 3-1 selector 4. On the other hand, the portions A _H and B _H corresponding to the effective data word lengths of the input data A and B are input to the 2-input adders 30, 31, and 32, and the 2-input adder 30 uses A _H + B _H and 2-input adder. In 31, A _H + B _H +
In the 1 and 2 input adder 32, A _H + B _H +2 is the 2 input adder 1
Is calculated in parallel with. The outputs of the 2-input adders 30, 31, 32 are input to the 3-1 selector 4, and the addition result of the selection signal generation circuit 2 is The output of the 2-input adder 30 in the case of 1, the output of the 2-input adder 31 in the case of 1, and the output of the 2-input adder 32 in the case of 2 becomes the output of the system.

(Embodiment) FIG. 2 shows an embodiment of the present invention, input 16 bits × 2, output 8 bits +
It is a carry adder configuration.

An arbitrary 8-bit adder can be used as the 2-input adder 1. The selection signal generation circuit 2 calculates the sum of the two inputs when the sum S ₇ of the most significant digit and the carry C ₈ carried from the most significant digit of the 8-bit two-input adder 1 are input. When the signal is output to the output line 20, the signal is output to the output line 21 when the signal is 1, and the signal is output to the output line 22 when the signal is 2 in the negative logic.
It is composed of an ENOR gate and a NAND gate.

The two-input adders 30, 31, 32 in FIG. 1 are common except for the carry calculation section, and sliced every 4 bits together with the 3-1 selector 4 in FIG. 1 to adder + selector block in FIG. We have reduced it to 51 and 52 to reduce the amount of hardware. By slicing every 4 bits, carry calculation can be performed in parallel for each block, and the speed can be increased.

Here, the input / output terminals of the adder + selector blocks 51 and 52 will be described. I at the end of the terminal name indicates a negative logic input / output terminal. A _{3 to} A ₀ and B _{3 to} B ₀ are input terminals of input data of 4 bits × 2, and S _{3 to} S ₀ are output terminals of 4 bits of the result.

Is an input terminal, and carry carried to the adder + selector block When In the case of 1, a signal is input to CI1I and in the case of 2, a signal is input to CI2I in negative logic.

Is an output terminal, and the carry carried to the next block is When When the signal is 1, the signal is output to CO1I, and when the signal is 2, the signal is output to CO2I in negative logic.

Adder + selector block 51 is the lower 4 bits of valid data
The addition result of minutes and the carry sent to the upper adder + selector block 52 are the three states of the output of the selection signal generation circuit 2. Each of them is calculated, and when the result of the selection signal generation circuit 2 is determined, one of them is selected and output. The adder + selector block 52 adds the result of addition of the upper 4 bits of valid data and the carry output to the adder + selector block.
Carry three states from 51 Calculate for each and adder + selector block 51
When one of the results is determined, one of them is selected and output.

FIG. 3 shows the CM of the adder + selector block 51, 52.
It is a configuration example in the OS. This part calculates in parallel the addition of A _H + B _H , A _H + B _H +1 and A _H + B _H +2 in the effective data word length. A _H + B _H is a normal adder, A _H + B _H
+1 can be realized by carrying a carry of 1 to the least significant digit of an ordinary adder. However, A _H + B _H
+2 must be added twice in the usual way of thinking. This is not a fast calculation, so 3 states for carry that can only take 2 states, 1 and It has a hardware configuration that can be calculated by taking Here, a carry of 2 corresponds to adding 2 to the reference digit by advancing from the lower order. According to this method, A _H + B _H +2 can be realized at high speed by moving the carry of 2 to the least significant digit. The hardware configuration will be described below.

CG in the figure is a carry generator, which calculates the carry carried to the next digit based on the input of each digit of the input data A and B and the carry carried from the previous digit. Carry carried to the next digit is carried to each adder + selector block. Assuming each, calculate for each of the three states.

Here, the input / output terminals of the carry generator CG will be described. ND and NR are input terminals, which are inputs for distinguishing the three states of the sum of input data A and B for each digit.
Of A _i and B _i To the input terminal NR of A _i and B _i Enter.

Is an input terminal, and carry carried to the adder + selector block When When 1, the carry carried from the previous digit is input to I1I in negative logic.

Is an input terminal, and when the carry carried to the adder + selector block is 2, the carry carried from the previous digit is If it is If it is 1, a signal is input to I21I, and if it is 2, a signal is input to I22I in negative logic.

Is an output terminal, and a carry carried to the block When In the case of 1, the carry carried to the next digit is output in negative logic at 01I.

Is an output terminal, and when the carry carried to the block is 2, the carry carried from the first digit is If it is When the value is 1, the signal is output to 021I, and when the value is 2, the signal is output to 022I in negative logic. In this way, the three states of the carry of each digit when the carry carried to the block is 2 are represented by three signal lines in order to omit the encoding and decoding circuits and to speed up the circuit.

Next, the operation of the circuit shown in FIG. 3 will be described. Input data A, B
Input each digit (take A ₁ and B ₁ as an example)
Is a NAND gate 501, NOR to indicate the three states of the sum.
Gate 502 takes NAND and NOR respectively,
Input to input terminals ND and NR of carry generator 503, respectively. Carry generator 503 has three possible states for carry input carried to adder + selector block. Calculated carry carry from the previous digit for each of Carry carried to the next digit by each input of ND and NR To calculate. The output of the NAND gate 501 and NOR
EOR from the output of gate 502 by EOR gate 504
(Equivalent to E ₁ of A ₁ and B ₁ ) to calculate a provisional sum that does not consider the carry from the lower order for each digit. After that, when the carry from the lower order for the adder + selector block is determined, the true carry carried from the previous digit to that digit is selected by the selector 505. If there is a carry, the temporary sum output is inverted, so the EOR of the temporary sum (output of the EOR gate 504) and the true carry (output of the selector 505) is set to the EOR gate 5.
Take by 06. Thereby, the true sum output of that digit can be obtained. Here, when a carry of 2 is input to the adder + selector block, the carry carried from the previous digit that affects the result of a certain digit is only 1 (the carry of 2 is based on that digit. To "1
It is equivalent to adding 0 _{2} ", so the effect goes above that digit and is not related to that digit itself.), The input to the selector 505 is the previous carry when the carry carried to the block is 2. It is sufficient to bring a signal from the negative logic output terminal 021I of the carry generator indicating that the carry carried from the digit is 1. The carry carried from the third digit of the adder + selector block to the next block is the carry for that block. When it is input, it is selected by the selectors 507, 508, and 509 from the output of the carry generator at the third digit, and when the carry carried to the next block is 2, it is C02I, when it is 1, it is C01I, When The signal is output in negative logic.

Here, the carry generator section will be described. Table 1 shows the correspondence between the carry carried from the previous digit (carry input) and the carry carried to the next digit (carry output) with respect to the value A _i , b _i of a certain digit of the input data A and B as a numerical value. It is a thing. Where carry input Is carry output Corresponding to, carry carried to adder + selector block Is valid, I1 corresponds to 01, and the carry carried to the adder + selector block is 1; I2 corresponds to 02; carry carried to the adder + selector block is 2 Is a valid value. In Table 1, for example, carry output Each output value in the left column of is the carry input In the case of, the value is output for each input value of the addition inputs A _i and B _i . Similarly, for example, the output values in the rightmost column of carry output 02 are addition inputs A when carry input I2 is 2.
It is a value output for each input value of _i and B _i .

A logical expression is provided between each carry output On and each carry input In and addition inputs A _i and B _{i in} Table 1. [X] is a maximum integer that does not exceed x.

This adder has three states: carry carried to adder + selector block Since the results are calculated in advance for each, the above correspondence Are separately configured with logic. Here, A _i from the correspondence table, addition input of B _i is A _i ∩B _i (D in Table 2 to be described later
Indicates. ) And A _i ∪ B _i (indicated as R in Table 2) are involved in the carry output, and this is used as an intermediate logic to replace the A _i and B _i with the carry generator. Used as input. Also, I2,02 must take three states, so I2 3 signals of 02, The three signals represent the status. And in I2 of Table 1 The state Then, the state of 1 Then, the state of 2 Express with. Also at 02 The state Then, the state of 1 Then, the state of 2 Express with. Table 2 shows an input / output logic correspondence table corresponding to the first table when the input / output terminals are defined as described above.

The input and output of the circuit of the configuration example are configured by negative logic. The correspondence is Has become. I at the end of the terminal name indicates a negative logic input / output terminal. Then, when the input / output terminals of the carry generator are determined as described above, the logical correspondence between the terminals and the carry input Table 3 shows a correspondence table of carry outputs corresponding to the second table when the selection signal and the intermediate logic inputs D and R are regarded as the selected signal.

here, 2 signals, I1I and ▲ ▼ signals, Since the three signals of ,, and are mutually exclusive, the logic in the carry generator can be expressed by the following equation.

FIG. 4 shows an example of the circuit configuration of the carry generator (CG) 503. This realizes the carry generation rules of the carry generator shown in Table 3.

here, The configuration of the carry generator of the digit is realized as follows. First, virtually from the -1st digit of the block Consider a carry that goes up to the number of digits. This has the same meaning as the carry carried from the previous block to that block, so the carry carried to the block is When When it is 1, I1 = 1, and when it is 2, I2 = 2. Since this adder performs calculations on the assumption of this in advance, it can be encoded as it is and sent. That is, from the -1st digit As All you have to do is create the logic of the carry generator for the digit. Then, of the block According to Table 3, carry carried from the first digit to the first digit is Becomes An example of this is shown in Figure 3. It is a carry calculation circuit from the first digit to the first digit.

(Effects of the Invention) As described above, according to the present invention, in an adder that limits and outputs the effective word length from the calculation result, the adder is composed of an upper effective data block and a lower rounding correction block. The sum of the carry output carried from the rounding correction block to the valid data block and the highest sum output of the rounding correction block can be obtained. For each of the three states, the calculation result of the valid data block is obtained in advance in parallel with the calculation of the rounding correction block, and one of the three states consisting of the carry and the sum of the rounding correction block is applicable when it is determined. Since one of the calculation results of the valid data block is selected and output, (b) the addition result of the data lower than the valid data is taken into consideration, so the error is small and there is no deviation.

(B) Since the calculation is performed in parallel, the processing speed is high.

And so on.

[Brief description of drawings]

FIG. 1 is a conceptual diagram of a rounding adder of the present invention, FIG. 2 is an embodiment in which the present invention is applied to a case of input 16 bits × 2, output 8 bits + carry, and FIG. 3 is a 4-bit adder in FIG. An example of the circuit configuration of the selector block, FIG. 4 is an example of the circuit configuration of the carry generator in FIG. 3, FIG. 5 (a),
(b) is an example of a conventional rounding adder. 1 …… 2 input adder, 11 …… Sam, 12 …… Carry, 2
...... Selection signal generation circuit, 30, 31, 32 …… 2-input adder,
4 …… 3-1 selector

Continuation of front page (56) Reference JP-A-52-112249 (JP, A) JP-A-60-129832 (JP, A) JP-A-60-129833 (JP, A) JP-A-58-92036 (JP , A)

Claims (1)

[Claims] 1. An adder for limiting and outputting a valid word length from a calculation result, which comprises an upper valid data block and a lower rounding correction block, and repeats from the rounding correction block to the valid data block. The sum of the carry output that rises and the highest sum output of the rounding correction block can be taken. For each of the three states, the calculation result of the valid data block is obtained in advance in parallel with the calculation of the rounding correction block, and one of the three states consisting of the carry and the sum of the rounding correction block is applicable when it is determined. A rounding adder characterized by selecting and outputting one of the calculation results of the valid data block.