JPH0664535B2 - Microcomputer system - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an interrupt technique in a microcomputer system, and is applied to a system having a microprocessor forcibly set to an initial state by a reset signal supplied from the outside, for example. Regarding effective technology.

BACKGROUND ART Microprocessors (hereinafter referred to as MPUs) include synchronous type and asynchronous type, but a conventional MPU is
Regardless of the synchronous method or the asynchronous method, the reset signal is synchronized with the rising or falling of the clock signal.
When the low level "L" of ▼ is recognized, the bus cycle being executed is interrupted to return to the initial state, and the reset sequence process is started.

However, for example, in a microcomputer system including a bus master board having an MPU and a peripheral device such as a memory board having a memory controlled by a control signal supplied from the bus master board via a bus, the reset signal as described above is used. Therefore, if the bus cycle is interrupted midway, a system inconvenience occurs. For example, when the program starts to run out of control during program development and the system is stopped by inputting the reset signal "L", the conventional system inputs the reset signal ▲ ▼ after entering the bus cycle. Then, the bus cycle is immediately interrupted, and the control signal such as the address strobe signal ▲ ▼ supplied to the MPU or the memory board is immediately raised (see FIG. 1).

However, in a memory board including a dynamic RAM, a row address / strobe signal ▲ ▼ and a column address / strobe signal ▲ ▼ are formed based on the address / strobe signal ▲ ▼ to access the memory. Therefore, if the address strobe signal ▲ ▼ falls in the bus cycle and then rises immediately, the length of the ▲ ▼ signal or ▲ ▼ signal becomes insufficient. Therefore, there is a possibility that a multiple selection state occurs, which may destroy the data in the memory or prevent normal data writing. If you want to know if this kind of memory data destruction is due to a program runaway or a hardware cause, or if you want to know how much data was written to memory, it is said that the memory data is corrupted. There is the inconvenience of not being able to do that.

In the above case, if a reset signal is input after the bus cycle starts, the MPU will continue until the bus cycle ends.
It is also conceivable to provide a circuit for latching various output signals from the memory with the address strobe signal on the memory board to guarantee the bus cycle. However, according to such a method, in a system having a large number of memory boards, it is necessary to provide a latch circuit or the like for each memory board, which increases the design burden and is disadvantageous in terms of overhead.

MP capable of forming address strobe signal
U is a P. of "Hitachi Microcomputer Data Book: 8-bit / 16-bit multi-chip" issued by Hitachi, Ltd. in September 1983. 653-P. 744
It is described in.

[Object of the Invention] The present invention focuses on the fact that a reset performed when a program goes out of control during program development does not necessarily require the MPU to be immediately initialized, unlike a power-on reset. Even if a reset signal comes in after that, only the bus cycle is guaranteed, and for example, it is to provide a system capable of preventing the destruction of the data written in the memory or the data being written.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[Outline of Invention] The outline of a typical invention disclosed in the present application will be described below.

That is, the bus cycle start signal output from the MPU and the reset signal supplied from the outside are sampled by clock signals having different half cycle phases, and whichever of the bus cycle start signal and the reset signal is sampled, whichever comes first. The generated signal is treated preferentially. When the bus cycle starts earlier, the reset signal is input to the MPU after waiting for the end of the bus cycle, and when the reset signal is earlier, the bus output from the MPU. By not transmitting the cycle start signal to the memory board, etc., when the reset signal is input after the bus cycle starts, the bus cycle in execution is guaranteed, and the dynamic RAM Achieve the above purpose of preventing data destruction It is intended.

[Embodiment 1] FIG. 2 shows an example of a schematic configuration of a bus master board when the present invention is applied to a microcomputer system having an MPU such as HD68000 manufactured by Hitachi, Ltd.

In the figure, 1 is not particularly limited, but is an asynchronous MPU such as HD 68000, and this MPU 1 is operated by the system clock φc supplied from the oscillation circuit 2, and an asynchronous reset signal ▲ ▼ is input to the reset terminal RS from the outside. Then, in synchronization with the rising edge of the clock φc, the clock φc is taken in and the bus cycle start signal such as the address strobe signal () is controlled.

In this embodiment, a normal reset signal () supplied from the outside is input to the data input terminal D of the D-type flip-flop FF ₁ . The system clock φc output from the oscillator circuit OSC is fed to the inverter INV at the clock terminal CLK of the flip-flop FF _1.
A sampling clock φs ₂ formed by inverting twice with ₁ and INV ₂ is applied.
Reset signal ▲ ▼ in synchronization with the rise of ₂
Is designed to take in. Flip-flop FF ₁
The clear terminal CLR of is connected to the power supply voltage Vcc through the pull-up resistor R and is always fixed at a high level. An output signal of the gate circuit G ₃ described later is applied to the preset terminal PR.

The output Q of the flip-flop FF ₁ is an invert N
It is supplied to one input terminal of the AND gate circuit G ₁ , and when the gate is opened by the other input signal (low level) of this gate circuit G ₁ , it is supplied to one input terminal of the inverted NOR gate circuit G ₂ . To the other input terminal of the gate circuit G ₂ , a reset signal having the highest priority such as a power-on reset signal is input, and the gate circuit G ₁ is opened to receive an ordinary reset signal ▲ ▼. When a power-on / reset signal is input, the output signal of the gate circuit G ₂ is set to low level and supplied to the reset terminal of the microprocessor MPU for resetting.

Further, a bus cycle start signal such as the address strobe signal () output from the microprocessor MPU is supplied to the data input terminal D of the D-type flip-flop FF ₂ . This flip-flop FF ₂
System clock signal φc
Is applied by the inverter INV ₁ to form a sampling clock signal φs _1, and the bus cycle start signal (▲ ▼) is taken into the flip-flop FF ₂ in synchronization with the rising of the sampling clock signal φs ₁ .

Therefore, the reset signal supplied from the outside
The bus cycle start signal (▲ ▼) output from ▼ and MPU are sampling clocks φs ₁ and φs _2.
And are taken in at a timing shifted by 1/2 cycle.

The clear terminal CLR terminal of the flip-flop FF ₂ has a pull-up resistance R as in the flip-flop FF _1.
It is connected to the power supply voltage Vcc via and is fixed at a high level. The output signal of the gate circuit G ₂ is applied to the preset terminal PR.

The output of this flip-flop FF ₂ and Q are
The gate circuit G ₁ and the gate circuit G ₃ described next
Are respectively supplied to the input terminals as gate opening / closing control signals.

The gate circuit G ₃ is composed of an inverter NAND circuit, and the bus cycle start signal (▲ ▼) output from the MPU is supplied to the other input terminal. The output signal of the gate circuit G ₃ is supplied to the peripheral device as a true bus cycle start signal ▲ ▼ pr.

Next, the operation of this embodiment will be described.

As described above, the reset signal ▲ ▼ and the bus cycle start signal (▲ ▼) are sampled in FF ₂ of the flip-flop FF ₁ by the sampling clock signals φs ₂ and φs _{1 which} are shifted by 1/2 cycle. ing. That is, in synchronization with the fall of the system clock signal φc, the bus cycle start signal (▲
)) And the reset signal ▲ ▼ are always sampled in synchronization with the rise of the system clock signal φc.

Therefore, when the reset signal ▲ ▼ is changed to the low level before the bus cycle start signal (▲ ▼) is changed to the low level, the output Q of the flip-flop FF ₂ is high because the PR of the flip-flop FF ₂ is low and the CLR is high. , And the output goes low. Therefore, the output of the gate circuit G ₃ (bus cycle start signal ▲ ▼ p
r) is set to the high level to enable the flip-flop FF ₁ and the low level of the reset signal ▲ ▼ is sampled in synchronization with the rise of the system clock signal φc. At this time, since the gate circuit G ₁ is opened by the output (low level) of the flip-flop FF ₂ , the reset signal is supplied to the reset terminal of the MPU through the gate circuits G ₁ and G ₂ and resets. When the output of the gate circuit G ₂ is changed to the low level, the preset terminal PS of the flip-flop FF ₂ is set to the low level, and the output Q of the FF ₂ is fixed to the high level.

Further, even if the bus cycle start signal changes to the low level at the same time as the sampling of the reset signal, after the 1/2 cycle of the sampling of the reset signal (low level),
Since the flip-flop FF ₂ is adapted to perform sampling of the bus cycle start signal, the flip-flop F ₂ is output by the low level output of the gate circuit G ₂ before that.
F ₂ is preset, sampling cannot be performed, the output Q of FF ₂ is fixed at high level, and the gate circuit G ₃ is closed.

As a result, once the reset signal is accepted, until the reset signal is released, that is, until the reset signal ▲ ▼ changes to the high level and is latched, the gate circuit G ₃ sends the bus cycle start signal ▲ to the peripheral device.
▼ Pr is never output.

On the other hand, as shown in FIG. 3, a bus cycle start signal (▲
The falling edge of ▼) is earlier than the rising edge of the reset signal ▲ ▼, and the low level of the bus cycle start signal (▲ ▼) is sampled earlier in the flip-flop FF ₂ in synchronization with the falling edge of the system clock signal φc. Suppose Then, the output Q of the flip-flop FF ₂ is changed to the low level, and the gate circuit G ₃ sends the bus cycle start signal ASpr to the peripheral device.
(Low level) is transmitted, and the output of the flip-flop FF ₂ is changed to High level to close the gate circuit G ₁ . Therefore, after that flip-flop F
The reset signal sampled by F ₁ is the MPU.
Cannot be transmitted to the reset terminal RS of. As a result, when the low level of the bus cycle start signal (▲ ▼) is sampled _first , the MPU is prevented from being normally reset until it rises to the high level and the gate circuit G ₁ is opened. The bus cycle performed is guaranteed.

However, in this embodiment, since the highest priority reset signal such as power-on reset is inputted from the gate circuit G ₂ , when this is inputted, MP is inputted.
U is immediately reset and the bus cycle is interrupted.

In the above embodiment, the output signal of the gate circuit G ₃ is supplied to the preset terminal PS of the flip-flop FF ₁ . Therefore, when the bus cycle start signal ▲ ▼ pr is supplied to the peripheral device, the flip-flop FF ₁
Output Q is fixed to high level and reset signal ▲
▼ is prevented from being sampled. As a result, the bus cycle start signal (▲ ▼) output from the MPU is changed from the low level to the high level and the output Q of the flip-flop FF ₁ is changed from the low level to the high level 1/2 cycle after the gate circuit G ₁ is opened. This prevents the MPU from malfunctioning due to the application of a signal that does not satisfy the condition of the "L" period defined in the reset terminal RS of the MPU when the state of changing to the level occurs.

However, in this embodiment, the sum of delay times in the flip-flop FF ₁ and the gate circuits G ₁ and G ₂ is 1/2.
The condition is required to be shorter than the cycle, and it is desirable that these circuits are composed of a TTL circuit or an ECL circuit that can operate at high speed.

Further, in the above-described embodiment, the MPU exchanges signals with the peripheral device by the handshake method, and when the bus cycle is earlier, until the end signal (DTACK) is returned from the peripheral device to the MPU. It is designed to wait for the reset signal to be fetched. Therefore, when the response from the peripheral device is correct due to the failure or runaway of the peripheral device, the MPU may enter the wait state and the reset signal may disappear during that time. Therefore, in the above-described embodiment, the bus monitoring circuit 10 having a built-in counter is provided, and the bus is monitored by this circuit, and the bus cycle start signal (▲ ▼ p
When r) is changed to the low level, the internal counter starts counting, and for example, when the end signal (DTACK) is not returned from the peripheral device even after several microseconds,
A bus error signal BERR is generated and supplied to the MPU to end the bus cycle.

When a reset signal is input by a normal switch, the pulse width of the reset signal is guaranteed to be several tens of microseconds or more, so that the end signal (DTACK) is not returned from the peripheral device as described above. Even in such a case, even if the reset signal is kept waiting during the bus cycle, the bus cycle is terminated before the reset signal disappears by the bus monitoring circuit 10, and the reset signal is accepted by the MPU.

Further, in the above-described embodiment, the D-type flip-flop FF ₁ performs sampling in synchronization with the reset signal ▲ ▼ supplied from the outside, but the sampling clock φs ₂ of the flip-flop FF ₁ is changed. If the rising and the change of the reset signal ▲ ▼ occur at the same time, the determination of the output Q of the flip-flop FF ₁ may be significantly delayed from the steady delay time. In that case, the D-type flip-flop as described above is used. May be connected in two stages to prevent malfunction due to delay in output change.

[Effects] (1) In a system having a microprocessor configured to forcibly cancel a bus cycle immediately when a reset signal is input during execution of the bus cycle,
The bus cycle start signal output from the MPU and the reset signal supplied from the outside are sampled with clock signals with a half-cycle phase shift, and whichever of the bus cycle start signal and the reset signal occurs earlier, whichever occurs first. Signals are handled with priority, and when the bus cycle starts earlier, wait for the end of the bus cycle to input the reset signal to the MPU, and when the reset signal is earlier, the bus cycle output from the MPU. Since the start signal is not transmitted to the memory board etc., if the reset signal is input after the bus cycle has started, the bus cycle being executed is guaranteed and the system is configured. The effect that can prevent the data destruction of the dynamic RAM That.

(2) The bus cycle start signal output from the MPU and the reset signal supplied from the outside are sampled by clock signals whose half-cycle phases are different from each other, and in either sampling of the bus cycle start signal and the reset signal, Priority is given to signals that occur quickly, and when the bus cycle starts earlier, the reset signal is input to the MPU after the end of the bus cycle, and when the reset signal is earlier, it is output from the MPU. Since the circuit that prevents the bus cycle start signal from being transmitted to the memory board or the like is provided in the bus master board including the MPU, a system configured by one bus master board and a plurality of memory boards or the like is provided. And a circuit that guarantees the bus cycle being executed on the memory board side. Kicking design is facilitated compared to the case, there is an effect that the overhead is reduced.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments and various modifications can be made without departing from the scope of the invention. Nor. For example, in the embodiment, MP
I explained that the system is composed of a bus master board equipped with U and a memory board.
The present invention is not limited to this.

[Field of Use] In the above description, the invention made by the present inventor is a field of use which is the background of the invention and is an asynchronous 6800.
Although the description has been given of the one applied to the microcomputer system using the 0-system MPU, the present invention is not limited thereto and can be applied to the system using the 8086-system asynchronous MPU or the synchronous MPU. It is a thing.

[Brief description of drawings]

FIG. 1 is a timing chart showing timings of various signals in a microcomputer system, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a timing chart thereof. 1 ...... MPU (microprocessor), 2 ...... oscillation circuit, 10 ...... bus monitor _circuit, FF 1, FF ₂ ...... flip-flop (sampling _circuit), G 1 ~G ₃ ...... gate circuit (signal transmission circuit) , INV ₁ , INV ₂ ... Inverter (clock generation circuit), OSC ... Oscillation circuit, ▲
▼ …… Reset signal, ▲ ▼ …… Bus cycle start signal (address strobe signal).

Claims (3)

[Claims] 1. A microcomputer including a microprocessor and peripheral devices connected to each other via a bus.
In the system, a reset circuit is provided between the sampling circuit and a reset terminal of the microprocessor, the sampling circuit taking in a reset signal for initializing the inside of the microprocessor in synchronization with the first clock signal. A first gate circuit for supplying and blocking a signal to and from the microprocessor; and a first gate circuit connected to a control signal output terminal of the microprocessor and indicating the start of a bus cycle output from the output terminal. A second gate circuit for supplying and blocking a control signal to and from the peripheral device, and a first control signal connected to a control signal output terminal of the microprocessor and output from the output terminal. When it is taken in in synchronization with the second clock signal having a phase different from that of the first clock signal, Also, the reset signal passed through the first gate circuit is received, and which of the reset signal and the first control signal is earlier is detected, and when the reset signal is earlier, the second gate is detected. Includes a priority determination circuit that forms a second control signal that shuts off the circuit, and a third control signal that shuts off the first gate circuit when the first control signal is earlier, and a timer counter However, by monitoring the signal indicating the start of the bus cycle, the counter counts the duration of the bus cycle, and if the end signal is not returned from the peripheral device And a bus monitoring circuit for supplying a signal for terminating the bus cycle, and a microcomputer.
system. 2. The priority determination circuit comprises a flip-flop having a data input terminal, a clock input terminal, a state control input terminal, a non-inverting output terminal and an inverting output terminal, and the data input terminal includes the first flip-flop. A control signal is input to the clock input terminal, the second clock signal is input to the state control input terminal, and a reset signal passing through the first gate circuit is input to the state control input terminal. The output signal from the terminal is configured to be supplied to the first gate circuit and the second gate circuit as second and third control signals, respectively. Microcomputer system. 3. The microcomputer system according to claim 1, wherein said first control signal indicating the start of a bus cycle is an address strobe signal.