JPH0664539B2 - Data processing device testing method - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test method for a data processing device, and more particularly to a test method using a test command sequence of a large-scale data processing device having an acceleration logic. The present invention relates to a test method for a data processing device suitable for enabling a reduction in analysis time by localizing.

[Conventional technology]

In a test system that confirms the normality of functions in a data processing device, one expected value is prepared for one piece of test data, the test data is executed by the device under test, and the processing result is compared with the expected value. Was common.

However, with the increase in scale of the data processing apparatus, a method of forming test data by a test instruction sequence, which is a set of a plurality of ordered instructions, and one expected value for the test instruction sequence has been adopted. . In this case, the conventional test method is as follows. Each test instruction sequence is executed on the device under test to confirm the normality of the device. The processing result of each test instruction sequence execution is compared with its expected value, and if they do not match, it means that the test instruction in the test instruction sequence has an error. When an abnormality is detected in the execution result of a certain test instruction sequence, which test instruction in the test instruction sequence caused the error is manually investigated.

This test method has a problem that it takes a lot of time for the investigation because the investigation is done manually and the investigation result depends on the ability of the investigator. In order to determine the test instruction that caused an error, it is necessary to refer to the assemble list, execute the test instruction sequence that gives an abnormal result multiple times, or change the instruction and data by patching. It was

As a test method to solve the above problems, a soft simulator for the device under test is provided in the test system, and the test instruction sequence is executed by the device under test according to the test data.If it does not end normally, then error analysis is performed. In the processing, there is a method in which one instruction is cut out from a test instruction sequence and executed by both the soft simulator and the device under test, and the results are compared. FIG. 4 shows an example of the processing flow of this system. According to this, it is possible to easily recognize which test instruction in the test instruction sequence was not processed normally. The test method is described in detail, for example, in JP-A-61-43351.

[Problems to be solved by the invention]

Generally, in a large-scale data processing device or the like, an acceleration logic typified by advanced control theory pipeline control is used in order to realize high-speed processing. In this type of data processing device, an instruction sequence having an order is not serially executed, but execution of a subsequent instruction is started in the middle of execution of a preceding instruction. Multiple instructions are executed in parallel.

When the above test method is applied to the test of the data processing device having such an acceleration logic, the following problems occur. Execution of the test instruction sequence in the test target device during the test is performed in parallel while the instructions that form the test instruction sequence are organically combined with each other and executed in parallel. Since the instructions are cut out one by one and executed one by one, the execution environment of the test instruction sequence changes. For example, in the test instruction sequence, an instruction that is continuously executed by the preceding instruction is rewritten, or an instruction that is executed by using the execution result of the preceding instruction is used. Even if an error is detected in the execution of an organically combined instruction sequence that affects the execution of a (conflict condition), the error analysis processing will organically combine the instructions that make up this test instruction sequence. Ignore and cut and execute one instruction at a time. For this reason, the same result as when the instructions constituting the test instruction are sequentially executed is obtained, and the problem that the error cannot be pointed out accurately occurs.

An object of the present invention is to solve the above-mentioned problems and, even in a data processing device having an acceleration logic, when an abnormality is detected in the execution of the test instruction sequence due to the processing peculiar to the acceleration logic, a test instruction that has an error occurs. It is an object of the present invention to provide a test method for a data processing device, which enables a user to directly determine the data processing time and reduce the time required for manual investigation.

[Means for solving problems]

According to the present invention, the test instruction sequence and the test data are taken out one by one and accumulated, and in the process of accumulation, the instruction sequence accumulated up to that time is sequentially processed by both the test target data processing device and the simulation processing unit. It is characterized by executing and comparing the execution results.

[Action]

One instruction is taken out from the test instruction sequence and accumulated,
Each time, the instruction sequence accumulated up to that point is executed by both the test target device and the simulation processing unit, the execution results are compared, and an abnormality is detected in the execution result of the test instruction sequence accumulated up to a certain point. If there is no abnormality in the result of the instruction sequence accumulated / executed until immediately before, and the abnormality is detected by accumulating the instruction in the instruction sequence, the occurrence of the abnormal condition is limited to the relevant instruction. It is possible to analyze the contents.

〔Example〕

An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a block diagram of an embodiment of a test system for implementing the test method of the present invention. In FIG. 1, the test system 1 includes a test data storage unit 5 and a control unit 11. The test data storage unit 5 stores a random number value 2, a test instruction string and test data 3, expected value data 4, and the like. The control unit 11 generates a test instruction sequence and test data and controls the execution of the test. The control data generation unit 6, the test data setting unit 7, the simulation processing unit 8, the test result determination unit 9, and the error output unit 10 are provided. Have.

The test data generator 6 generates a test instruction sequence 3a and test data 3b based on the random value 2. The test data setting unit 7 includes a test instruction string 3a and test data 3b.
Is supplied to the simulation processing unit 8 and the test target device 12. The test instructions and test data on the test target device 12 are the test instruction sequence 3a and the test data 3b.
It is set while accumulating one instruction for each. The simulation processing unit 8 pseudo-executes the function of the test target device 12 based on the test instruction sequence and the test data received from the test data setting unit 7, and creates an execution result as expected value data 4. The test result determination unit 9 compares the expected value created by the simulation processing unit 7 with the execution result of the test instruction sequence with the execution result of the test instruction sequence executed by the test target device 12, and when a mismatch occurs. It detects an abnormality. When the test result determination unit 9 detects an abnormality, the error output unit 10 separates the test instruction string and the test data as an error message into an expected value and an execution result of the test target device 12 and outputs the result.

The data processing device 12 which is the device to be tested is a general data processing device, and includes a test data memory area 13 for storing the test instruction sequence 13a and the test data 13b passed from the test system 1 and a test instruction sequence 13a. It includes a test execution unit 14 that executes according to the test data 13b. In general, the test data memory area 13 is on the main storage device, and the test execution unit 14 is the central processing unit itself.

FIG. 2 shows the processing flow of this embodiment. First, prior to the start of the test, the test instruction sequence 3a and the test data 3b are generated by the process 201.
The test data 3b is generated by the test data generator 5 based on the random value 2.

In process 202, the test data setting unit 6 fetches one instruction from the test instruction string and the test data 3 and sets it in the test data memory area 13 of the device under test 12. In process 203, the test data setting unit 7 retrieves the command set in the test data / memory area 13 of the test target device 12 from the test command sequence / test data 3, and the simulation processing unit 8 executes the command. Process 2
In 04, the execution result in the simulation processing unit 8 is saved as expected value data 4. In step 205, the test instruction sequence 13a set in the test data memory area 13 of the device under test 12 is executed on the test execution unit 14 according to the test data 13b. In process 206, the test result determination unit 9 compares the expected value saved in process 204 with the result executed in process 205, and the test execution unit based on the instruction string set in the memory area 13 of the device under test 12 Verify normality of execution at 14. If it is normal, it is checked in step 207 whether the execution of all the instructions in the test instruction sequence is completed. If it is not completed, the process 20 is executed.
Return to 2.

By repeating the processes 202 to 207, the test instruction sequence is accumulated in the memory area 13 of the test target device 12, and the execution of the accumulated test instruction sequence is repeated on the test execution unit 14. At the same time, the exact same test instruction sequence is executed by the simulation processing unit 8 of the test system 1 to confirm the normality.
This will be described in more detail with reference to FIG.

FIG. 3 shows the transition of the test instruction sequence 13a on the test data memory area 13 in the test target device 12 when the processes 202 to 207 are repeatedly executed. In the first execution of the process 202, the memory area 13
, An instruction string of only one instruction is set as indicated by 220, and an instruction code for generating a trap (generally a software controllable interrupt) is filled in the remaining area to indicate the end of the test instruction. In the second execution of the process 202, the two instruction sequences having the sequentiality are set in the memory area 13 as indicated by 221 and the instruction code that causes the trap to indicate the end of the test instruction sequence in the remaining area. Is filled. In the state where the process 202 is executed n times, an instruction string consisting of n instructions having sequentiality is set in the memory area 13 as indicated by 222, and the remaining area is trapped to indicate the end of the test instruction string. The instruction code that generates

The memory area 13 of the device under test 12 is processed by the process 202.
The same test instruction sequence that is stored in the test system 1 is used in the simulation mode of the process 203.
Is executed by the simulation processing unit 8 and the execution result is saved as expected value data by the process 204. Next, a test instruction sequence based on the same test data as that executed in the simulation mode of the process 203 is executed on the test execution unit 14 by the process 205 using the command sequence of the memory area 13 of the device under test 12.

In this way, in the state of 222 in FIG. 3, the normality of the execution of the instruction sequence consisting of n test instructions in the test target device 12 is checked in the test result judging section 9 in the process 206. As a result, when an abnormality is detected, the error output unit 10 outputs in step 209 that the error is the result of executing the instruction sequence accumulating n test instructions, and the cause is investigated in step 210. . In this case, since the execution by the instruction sequence composed of up to n-1 test instructions was normal, the cause of the abnormality can be pursued by localizing to the nth accumulated test instruction n. .

If no abnormality is detected even when the test instructions accumulating n test instructions are detected, it is checked in step 208 whether the execution of the test instruction sequence including all the instructions has been completed. If not, the process returns to step 202, Further, the next ordered test instruction sequence such as n + 1 is created in the test data memory area 13 of the device under test 12.

By repeating the above processing, it is possible to confirm the normality of the operation of the test target device 12 in a state in which the test instruction sequence is composed of a plurality of test instructions having order, while accumulating the number of test instructions one by one. Therefore, even when an abnormality is detected, the content of the abnormality can be analyzed only in the accumulation instruction.

Further, processing 201 to processing 207 and processing 209, 21
It is checked in processing 208 that 0 has been executed a predetermined number of times, and if it has not reached the predetermined number of times, it is repeatedly executed. However, when the test instruction string and the test data are generated from the random number value, by changing the random number value of the test start , It is always possible to test with different content.

In the above process, the test instruction sequence, the test data 3, and the expected value 4 may not be generated from the random number value but may be incorporated in the test system in advance. In this case, it is not necessary to provide the test instruction sequence and test data generation processing of the processing 201. The simulation processing unit 8 is for executing a pseudo test instruction sequence to obtain an expected value, and the test target device 12 is provided in the test system 1.
The method of providing a software simulator that satisfies the individual instruction specifications of the above, the method of executing an actual data processing device whose operation normality has been confirmed other than the test target device, or the operation mode of the test target device If the operation is guaranteed, any method of fixing the mode of the device under test 12 and executing the method is possible. Further, it can be used as an error analysis process when a test instruction sequence is executed and an abnormality is detected.

〔The invention's effect〕

As is clear from the above description, according to the present invention, when n test instructions are accumulated and an abnormal result of the execution of the test instruction sequence is detected, execution is performed by accumulating up to n-1 test instructions. Was normal, it is possible to pursue the cause of the abnormality by localizing it to the n-th accumulated test instruction. Moreover, since it is possible to execute a test instruction sequence composed of a plurality of consecutive test instructions having an order, it is possible to obtain a further effect as a test of a data processing device having an acceleration logic.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a test system for implementing the test method of the present invention, FIG. 2 is a flow chart for explaining the process of FIG. 1, and FIG. FIG. 4 is a diagram showing the transition of the test instruction sequence accumulated in the memory area, and FIG. 4 is a flowchart for explaining the conventional test method. DESCRIPTION OF SYMBOLS 1 ... Test system, 5 ... Test data storage part, 6 ... Test data generation part, 7 ... Test data setting part, 8 ... Simulation processing part, 9 ... Test result determination part, 10 ... Error output part, 11 ... Control part, 12 ... Device to be tested, 13 ...
Test data / memory area, 14 ... Test execution unit.

Claims (1)

[Claims] 1. A test system having a test data storage unit for storing a test instruction sequence and test data having an order, and a simulation processing unit for quasi-executing the test instruction sequence. A method of testing normality, comprising a process of sequentially extracting one instruction from the test instruction sequence and test data stored in the test data storage unit and accumulating the same in a memory of the data processing device, Every time one instruction is stored in the memory of the data processing device, a step of executing all the stored instructions in the memory up to that time in the data processing device; a test instruction sequence and a test in the test data storage unit; Extracting from the data instructions for execution by the data processing device and executing the instructions by the simulation processing unit; A step of comparing the execution result of the data processing apparatus with the execution result of the simulation processing section to determine the normality of the execution in the data processing apparatus; Testing method for data processing equipment.