JPH0664584B2 - Vector sum operation unit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vector operation device, and more particularly, to an operation device for performing a sum operation of vector elements.

2. Description of the Related Art Generally, a vector arithmetic device is configured to perform element-corresponding arithmetic operations among a plurality of vectors.
Therefore, when the total sum of the elements of one vector is obtained, special addition means is provided in addition to the addition means corresponding to the normal vector element, or the addition means corresponding to the normal vector element is used. .

Problems to be solved by the invention Therefore, it is necessary to simultaneously supply different elements in one vector as data to the vector addition means, and it is necessary to provide control means and data output means therefor. It will be. As a result, the hardware of the arithmetic unit becomes large and the control becomes complicated. or,
In the latter case, in order to output another element from the vector storage means at the same time, it generally requires a long time to output, and the operation means occupancy time becomes longer than the operation corresponding to an element between a plurality of ordinary vectors, It also causes a decrease in the performance of the vector operation device.

The present invention has been made in order to solve the above-mentioned problems inherent in the prior art. Therefore, the object of the present invention is to have a structure in which the addition and the addition means corresponding to normal vector elements can be shared, It is an object of the present invention to provide a novel vector operation device capable of executing the total sum of vector elements with one instruction without causing performance deterioration in the configuration.

Means for Solving Problems When the vector sum operation device of the present invention obtains the sum of M vector elements (M is a positive integer, M = 2 ^m : m is a positive integer) included in the vector , Two vector storage means for storing partial vectors each consisting of vector elements of the same element, vector addition means for sequentially performing addition between the vector elements sequentially output from each of the vector storage means, and this vector addition Data distribution means for evenly distributing the addition result vector elements sequentially output from the means to the two vector storage means, the first processing for obtaining the m from the M, and the vector addition means for the number of additions 2 ^m-1 2 ^m-1 and the second process for
And a control unit that performs a third process of performing the second process by subtracting 1 from the m each time the addition is completed.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, this embodiment shows vector storage means 100, 200.
And vector elements are transferred to the vector addition means 300 through the data buses 10 and 20, respectively. Data bus 1
Reference numerals 1 and 21 are data buses for transferring vector elements from the outside to the vector storage means 100 and 200, respectively. The vector addition means 300 transfers the addition result of the vector elements to the data distribution means 400 via the data bus 30, and the data distribution means 400 alternately transfers the elements of the addition result vector to the vector storage means 100, 200 through the data buses 40, 41. To do. Calculation means 50
0 has control buses 50, 51, 52, 53. The control bus 50 stores the number of effective vector elements in the vector addition operation as vector storage means 100, 200, vector addition means 300, and data distribution means 400.
To the vector element, and the addition corresponding to the vector element is performed according to the number of elements. The control bus 51 receives the end of the vector addition operation, the control bus 52 receives the effective number of vector elements of the vector for which the sum is added, and the control bus 53 is a bus which notifies the end of the calculation of the vector sum.

Next, referring to FIG. 2, the calculation means 500 includes an encoder 51.
It includes a 0, -1 counter 520, a decoder 530, and a "0" comparator 540. The encoder 510 receives the effective number of elements M of the vector for summing given by the control bus 52, sets ^m to M = 2 ^{m in the} −1 counter 520, and the decoder 530 outputs −1.
It has a function of outputting 2 ^{m -1} from the control bus 50 as the number of effective vector elements for vector addition operation according to the value m of the counter 520.

Next, the operation of this embodiment having the above configuration will be described in detail. Referring to FIG. 3, a vector A represents a vector for which a sum is taken. The number of vector elements is now "8"
For example, as shown in FIG. 4, the vector storing means 100 and 200 are set as the partial vectors vector B and vector C, respectively, and the -1 counter 52
"3" is set to 0. Here, the decoding means 530
More effective vector element number "4" of the vector addition operation is output to the control bus 50, the elements of the addition result vector are alternately distributed by the data distribution means 400 after the vector addition operation is executed, and the vector storage means 100 and 200 are set as shown in vector B'and vector C ', respectively. At the same time, the -1 counter 520 counts and the counter value is updated to "2" (where ai, j represents the addition result of the vector elements ai and aj, and similarly ai, j and ak, l).
The addition result of is expressed as ai, j, k, l. ).

Then, the vector addition operation is repeated until the value of the -1 counter 520 becomes "0" by the effective number of vector elements of the vector addition operation output from the decoding means 530 as in the present case. As a result, as shown by the vector B ″ in FIG. 4, a _{1,2,3,4,5,6,7} which is the total sum of the vector A in this case is set in the vector storing means 100,
The fact that the sum of the vectors has been obtained by the "0" comparator 540 is output to the outside via the control bus 53.

To perform a normal vector element-aware addition, add the vector elements of the vectors you want to add to the data buses 11, 21.
It is needless to say that they are externally stored in the vector storage means 100 and 200 respectively, and their outputs are subjected to addition corresponding to vector elements by the vector addition means 300 and output, and then stored in arbitrary storage means. That is.

EFFECTS OF THE INVENTION As can be seen from the above results, according to the present invention, by adding the data distribution means 400 and the calculation means 500 to the ordinary vector operation device, the total sum of the vector A, which is one instruction, can be obtained. The effect is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG.
FIG. 4 is a detailed block diagram of the calculation means 500 shown in FIG. 1, FIG. 3 is a diagram of a vector for obtaining the total sum, and FIG.
It is a figure for demonstrating operation | movement of one Example shown in the figure. 100, 200 ... Vector storage means, 300 ... Vector addition means, 400 ... Data distribution means, 500 ... Calculation means, 510 ... Decoder, 520 ... -1 counter, 530 ... Encoder, 540 ...
"0" comparator, 10, 11, 20, 21, 30, 40, 41 ... Data bus, 50, 51, 52, 53 ... Control bus

Claims (1)

[Claims] 1. When calculating the sum of M vector elements (M is a positive integer and M = 2 ^m : m is a positive integer) contained in the vector, each sub vector is composed of the same number of vector elements. Are stored in the vector storage means, vector addition means for sequentially performing addition between the vector elements sequentially output from each of the vector storage means, and addition result vector elements sequentially output from the vector addition means. Data distribution means for evenly distributing to the two vector storage means, first processing for obtaining the m from the M, and number of additions 2 ^m-1
Control for performing a second process for causing the vector adding means to perform the addition and a third process for performing the second process by subtracting 1 from the m each time the 2 ^m-1 times of addition are completed And a vector sum calculating device.