JPH0664851B2 - Data identification device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data discriminating device for a magneto-optical disk device for recording / reproducing a PCM signal.

2. Description of the Related Art In recent years, a magneto-optical disk device has been actively developed as a large-capacity data file device capable of high-density recording / reproduction, and a data identification device for a reproduction signal also reproduces a clock in the reproduction signal at high speed and has a high capacity. A phase synchronizer capable of stable tracking has been developed. The recording / reproducing characteristics of the magneto-optical disk device are described in, for example, the Japan Society for Applied Magnetics Vol.8.N.
o.5, 1984.pp 355-360 "Recording and reproduction of magneto-optical disk"
Since the second-order distortion is large and easily fluctuates as shown in (1), for example, the 2/7 modulation shown in FIG.
55-26494, etc.) so that the signal modulated by the modified modulation is recorded and reproduced, and the duty cycle between each "1" becomes 50% for the 2/7 modulated signal (a). Na
The DC-free 2/7 modulation signal (b) is recorded. In this case, the reproduction signal data may be discriminated at the rising points at which each zero crosses, so that the discrimination of data with less deterioration of discrimination margin due to the secondary distortion can be performed.

Hereinafter, a conventional data identification device as described above will be described with reference to the drawings. FIG. 6 shows the structure of a conventional data identification device, and FIG. 7 shows the signal wave meter of each part.

In FIG. 6, 1 is a level comparator, 2 is a one-shot multivibrator, 3 is a phase comparator, 4 is an RS flip-flop, 5 is a reduction wave device, and 6 is a voltage controlled oscillator.

First, the level comparator 1 represents the zero crossing point of the input signal 2
Output a value signal. One-shot multi-vibrator 2
Is activated by the rising edge of the output signal of the level comparator 1 and outputs a pulse having a pulse width of 1/2 of 0.5T [sec] which is the bit interval of 2/7 modulation. (In this case, the bit interval of the signal before modulation is T [seconds].) The RS flip-flop 4 sets "1" at the rise of the output signal of the level comparator 1 and outputs the voltage controlled oscillator 6. It is a flip-flop that sets and outputs "0" at the rising edge of.
The phase comparator 3 outputs the phase difference between the output of the one-shot multivibrator 2 and the output of the RS flip-flop 4, and the low pass wave filter 5 reduces the phase difference signal which is the output of the phase comparator 3. Output. The voltage controlled oscillator 6 is a voltage controlled oscillator having an output of the low pass filter 5 as an input and a free-running frequency of 2 / T [Hz], and outputs an oscillation output to the RS flip-flop 4. In the above series of operations, the phase comparator 3 operates only when a zero crossing point is generated by the rising edge of the input of the level comparator 1, and the reproduction is synchronized with the phase of the zero crossing point by the rising edge of the input signal. The clock signal is obtained as the output of the voltage controlled oscillator 6.
Further, the output of the level comparator 1 may be taken as the identification data.

Problems to be Solved by the Invention However, in the above-described configuration, the pulse width variation of the pulse output by the one-shot multivibrator 2,
That is, since the jitter is added to the phase fluctuation at the zero-crossing point of the input signal, this pulse width jitter cannot be ignored especially under a high transfer rate, and there is a problem that the data discrimination margin is deteriorated.

In view of the above problems, the present invention provides a data identifying device capable of highly stable clock reproduction without deterioration of the data identifying margin.

Means for Solving the Problems In order to achieve this object, the data identification device of the present invention comprises:
It is composed of an analog-digital converter, a delay device, a phase calculator, a digital-analog converter, a low pass filter, and a voltage controlled oscillator.

Operation According to the present invention, the input signal is sampled and quantized in synchronization with the voltage controlled oscillator according to the above configuration, and the phase difference between the zero crossing point and the voltage controlled oscillator is calculated and output with reference to the two consecutive quantized values. By doing so, phase comparison with an extremely small error due to the jitter of the device is performed.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a basic configuration of a data identification device in an embodiment of the present invention, FIG. 2 shows signal waveforms or values of respective parts, and FIG. 3 is a waveform for explaining the operation of a phase calculator. FIG. 4 and FIG. 4 are detailed views of the relevant parts. Hereinafter, in each drawing, the same components as those in FIG. 6 showing the conventional example are designated by the same reference numerals and omitted.

In FIG. 1, 7 is an analog-digital converter, and 8
Is a converter, 9 is a phase calculator, and 10 is a digital-analog converter. FIG. 4 is a block diagram showing the details of the delay device 8, the phase calculator 11, and the digital-analog converter 10. 11 is a phase calculation ROM, 12 is an inverter, and 13, 14 and 15 are
An AND gate, 16 is a subtractor.

The operation of the data identification device configured as described above will be described below.

First, the analog-digital converter 7 samples the input signal in synchronization with the voltage controlled oscillator 6, samples and quantizes it, and outputs a binary signal represented by two's complement. The delay device 8 delays the output of the analog-digital converter 7 by one cycle using the output of the voltage controlled oscillator 6 and outputs the delayed signal. The phase calculator 9 selectively outputs the input signal when a zero crossing point occurs due to the rising of the input signal between two consecutive sampling values obtained by the output of the analog-digital converter 7 and the output of the delay device 8. And the output of the voltage controlled oscillator 6 is calculated and output, and "0" is output when the zero crossing point does not occur. The digital-analog converter 10 converts the output of the phase calculator 9 into an analog signal and outputs it. The operation of the phase calculator 9 is, as shown in FIG. 3, the phase calculation force φe when the zero crossing point occurs between the output S ₂ of the analog-digital converter 7 and the output S ₁ of the delay device 8. Is linearly interpolated from the output signals S ₁ and S _{2 at the} zero crossing point, and is output as in the following equation.

However, if S ₁ <0, S ₂ ≧ 0 and the calculation result of the above equation is limited to three values of “−1”, “0” and “1” in order to simplify the configuration related to phase calculation, As shown in FIG. 4, the configurations of the delay device 8, the phase calculator 9, and the digital-analog converter 10 can be easily realized. In FIG. 4, the inverter 12 and the AND gate 13 detect and output that a rising zero crossing point has occurred between the two points of the output signals S ₁ and S ₂ , and the above phase calculation output φe calculated by the phase calculation ROM 11 is The output of the AND gate 13 is used to perform switching operation by the AND gates 14 and 15. In this case, if the phase calculation ROM 11 is φe> 0, P = “1”, N
= “0” is output and when φe = 0, P = “0”, N =
When "0" and .phi.e <0, P = "0" and N = "1" are output. Further, the outputs P and N of the phase calculation ROM 11 are AND gates.
Since it is switched by 14 and 15 and subtracted by the subtractor 16,
In the above series of operations, when the phase calculation result φe is positive, it is "1", when it is zero, it is "0", and when it is negative, it is "-1", and it is obtained from the subtracter 16 as the output of the digital-analog converter 10. . Further, as can be easily understood, if the resolution of the calculation result of the equation (1) is increased, the accuracy of phase comparison will be increased. The analog-digital converter 7, the delay device 8, the phase calculator 9, and the digital-analog converter 10 described above enable the phase comparison between the input signal and the output of the voltage suppression oscillator 6, and the output of the data discriminating device. In this case, the output of the voltage controlled oscillator 6 which is the reproduced clock signal may be taken as the most significant bit of the output of the analog-digital converter 7 which is the identification data signal.

As described above, according to the present embodiment, by performing the phase comparison by the digital signal processing, it is possible to perform the phase comparison with high stability and an extremely small error due to the jitter of the device. Furthermore, by performing phase calculation in ROM, it is possible to easily add an additional function such as outputting "0" to the phase calculation result and stopping the tracking operation of the device when the input signal level is below a specific value. .

EFFECTS OF THE INVENTION According to the present invention, by providing an analog-digital converter, a delay device, a phase calculator, and a digital-analog converter, it is possible to perform highly stable phase comparison by digital signal processing and extremely small device jitter. Further, since the reference period for phase comparison is the period of the voltage controlled oscillator, it is possible to realize an excellent data discriminating device capable of performing phase comparison at the reference period adapted to the frequency fluctuation of the input signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a data identification device in an embodiment of the present invention, FIG. 2 is a waveform diagram showing signal values of respective parts of FIG. 1, and FIG. 3 is an explanation of phase comparison operation of FIG. 4 is a block diagram showing the details of the main part of the same, FIG. 5 is a waveform diagram of a recording / reproducing signal, FIG. 6 is a block diagram showing the configuration of a conventional data identification device, and FIG. FIG. 7 is a waveform diagram showing signals of respective parts of FIG. 5 ... Reduction wave transformer, 6 ... Voltage controlled oscillator, 7 ... Analog-digital converter, 8 ... Delay device, 9 ... Phase calculator, 10 ... Digital-analog converter, 11 ... Phase calculation ROM, 12 …… Inverter, 13,14,15 …… AND gate,
16-subtractor.

Claims (1)

[Claims] 1. An analog-to-digital converter for sampling an input signal at a specific clock and quantizing it to output a binary signal, and an output of the analog-to-digital converter delayed by one cycle in synchronization with the clock and output. Delay device,
The output of the analog-digital converter and the output of the delay device are used as inputs, and when a zero crossing point occurs between two consecutive sampling values obtained thereby, the position of the phase of the input signal and the clock phase are selectively selected. A phase calculator for calculating and outputting the phase difference, and a digital-analog converter for converting the output of the phase calculator into an analog signal and outputting the analog signal,
The digital-analog converter is provided with a low-pass filter that low-pass outputs the low-pass wave, and a voltage-controlled oscillator that oscillates and outputs the clock using the output of the low-pass filter as an input, and the clock is a regenerated clock. A data identification device which outputs as a signal and outputs the sign bit of the analog-digital converter as identification data.