JPH0664856B2 - Digital signal recording / reproducing device - Google Patents

Description

The present invention relates to a digital signal recording / reproducing apparatus applied to a digital data recorder.

"Background technology and its problems" It is possible to record and reproduce a test signal to check whether the recording / reproducing path of a digital data recorder is normal, or to extract a part of the reproduced data and analyze it.
This is a preferable function as a data recorder. As hardware that realizes this function, a data selector may be provided in the recording signal path and the reproduction signal path.

However, when the computer is used to generate a test signal, compare the reproduced test signal with an expected value signal, or analyze a part of the reproduced data, the transmission rate and the computer rate of the digital signal to be recorded or reproduced. Is different from the transmission rate of the data output by or received by the computer, and thus it is often difficult to switch by the selector. Usually, the transmission rate of the recorded or reproduced digital signal is higher than the transmission rate of the data of the micro computer.

Therefore, an object of the present invention is to make it possible to easily exchange recording data or reproduction data with a computer, and to easily test a recording / reproduction path and analyze reproduction data. The purpose is to provide a device.

[Outline of the Invention] First buffer memory for storing digital signals, first interface section, recording circuit to which digital signals read from first buffer memory are supplied, and output of recording circuit to recording medium Recording / reproducing means for reproducing the digital signal from the recording medium and supplying it to the reproducing circuit, a second buffer memory in which the output of the reproducing circuit is stored, a second interface section, and a first interface section. And a microprocessor coupled to the second interface unit, wherein the first interface unit is smaller than the first buffer memory coupled to perform direct memory access with the first buffer memory. A first memory for controlling writing and reading of the third memory of the capacity and the first buffer memory
And a second interface unit, which is coupled to the second buffer memory for direct memory access and has a smaller capacity than the second buffer memory and a fourth memory. In the case where the second control circuit for controlling the second buffer memory and the comparing means for comparing the specified address information with the address information of the reproduction data are provided, and the specified address information and the address information of the reproduction data match. The digital signal recording / reproducing apparatus is characterized in that the second control circuit prohibits the write operation to the second buffer memory and transfers the reproduction data of the matched address information to the microprocessor. .

[Embodiment] An embodiment in which the present invention is applied to a digital data recorder will be described below. In FIG. 1 showing the overall configuration of this embodiment, reference numeral 1 denotes an A / D converter to which analog data is supplied. The A / D converter 1 has
The external clock CKW is supplied and digital data of one sample, for example, 8 bits, is input from the A / D converter 1 to the buffer memory 2. When the analog data is video data, the output data of the A / D converter 1 which is converted into a component signal and digitalized for each component signal is external clock.
The data is written to the buffer memory 2 by CKW and is read from the buffer memory 2 by the system clock CKS from the clock generation circuit 3 inside the data recorder. The external clock CKW is well controlled and highly accurate so that it does not drift with temperature. The digital data read from the buffer memory 2 is supplied to the redundant code generation circuit 4.

Reference numeral 5 indicates an interface. Interface 5
Generates a control word as an identification signal during recording, and this control word is supplied to the redundant code generation circuit 4. In the interface 5, an address control for controlling the addresses of the small capacity memory and the buffer memory 2 is provided. The interface 5 stores data from an external host computer, for example, graphics data, in the buffer memory 2 regardless of the recording operation, and also acts as an intermediary when pulling up input digital data from the buffer memory 2 to the host computer.

The redundant code generating circuit 4 performs shuffling for converting the order of data to a different one from the original one in units of the length of one scan recorded by one scan of the rotary head, and the shuffling 1 The error correction code is encoded on the scan data. As the error correction code, for example, a product code that uses a Reed-Solomon code as each error correction code in the vertical direction and the horizontal direction can be applied. The block address of the recorded data is also formed by the redundant code generation circuit 4,
It is inserted for each block of recorded data.

The output data of the redundant code generation circuit 4 is supplied to the encoder 6. The encoder 6 performs channel encoding of recording data and insertion of block synchronization signal,
The recording data divided into four channels is taken out from the output of the encoder 6. As the channel encoding, for example, (8-9) conversion for converting 1 sample 8 bits into 1 sample 9 bits can be used. The output of each channel of the encoder 6 is the recording amplifier 7A, 7B, 7
Rotating head through C, 7D and rotating transformer (not shown)
It is supplied to 8A, 8B, 8C and 8D and recorded on the magnetic tape 9.
The processing of the digital data read from the buffer memory 2 or the memory of the interface 5 described above is performed by the system clock CKS.

FIG. 2 shows a recording pattern of the magnetic tape 9 in this embodiment. The rotating heads 8A, 8B, 8C, 8D scan the magnetic tape 9 wound around the tape guide drum obliquely from the lower side to the upper side, and four tracks 10A, 10B, 10B, 10B, which are parallel in one scanning operation. 10C and 10D are formed. Magnetic tape 9
Audio tracks 11A, 11B, 11C and a control track 11D are provided along the longitudinal direction of the. The audio track 11C is incremented by 1 for each frame, a sequence number which is a different number is recorded for each track, and a servo signal is recorded in the control track 11D.

Data processing is performed in units of 1 scan data. FIG. 3A shows one scan of recorded data output from the redundant code generation circuit 4. 0 for 1 skiyan
Includes 512 blocks from th to 511 th. 51
Of the 2 blocks, 32 blocks are redundant codes,
Two blocks are control words and 478 blocks are digital data. The control word is one block consisting of a sequence number and a user's code for each scan of recorded data, and the same one is double recorded as two blocks. this
The recorded data of 512 blocks is recorded on four tracks with the data rate set to 1/4. As shown in FIG. 3B, one block is a 128-byte code including a 4-byte CRC code (a cyclic code, which is a redundant code for error detection). At the beginning of each block, in the encoder 6, a 2-byte block synchronizing signal SYNC, a 2-byte block address AD and an identification signal ID are added as shown in FIG. 3C.

On the audio track 11C, SMPTE time code is recorded, and the user's bit of this time code is used for the sequence number and the tape mark. FIG. 4 shows the tape format of this embodiment.
The directory is recorded at the beginning of the recording section of the magnetic tape 9. In the directory, file information recorded on the magnetic tape 9, for example, data name, person name, start position sequence number, and end position sequence number are recorded. After this directory, multiple files are recorded. A header is inserted at the beginning of one file, and a plurality of blocked digital signals are recorded after this header. In Hezda,
Information about the file's block (this block is composed of multiple scan data) is recorded. As a tape mark recorded on the audio track 11C, BOT indicating the beginning of the recording section of the magnetic tape 9, BOF indicating the beginning of the file, BOB indicating the beginning of the block, EOB indicating the end of the block, EOF indicating the end of the file. Is used.

A signal reproduced from the magnetic tape 9 by the rotary heads 8A, 8B, 8C, 8D is a rotary transformer (not shown) and a reproducing amplifier 12.
A, 12B, 12C, 12D are respectively supplied to the PLL circuit 13,
The circuit 13 extracts the clock from the reproduction data of each track. The output of the PLL circuit 13 is supplied to the decoder 14. The decoder 14 is a circuit for extracting a block synchronization signal,
It has a TBC, a channel decoder, etc. for removing fluctuations in the time axis, and at the output of the decoder 14, reproduced data returned to one channel is obtained. This reproduced data is supplied to the error correction circuit 15.

The error correction circuit 15 is composed of a delaying circuit for returning the data arrangement to the original order and a correction circuit for performing error correction in the vertical and horizontal directions twice. At the output of the error correction circuit 15, reproduced digital data to which 1-bit error flag is added for each sample data is taken out and supplied to a buffer memory 16 and an interface 17. The error flag has a low level in the case of sample data in which no error is detected or the error has been corrected, and has a high level in the opposite case, that is, sample data containing an error. Among the reproduced data, the error flag is at a low level, that is, valid sample data is written in the buffer memory 16 and the memory of the interface 17. Digital data is written to the buffer memory 16, and a control word is written to the memory of the interface 17.

This writing is performed by the system clock CKS from the clock generation circuit 3. On the other hand, the reading of the buffer memory 16 and the memory of the interface 17 is performed by the external clock CKR. In Interface 17,
An address controller for controlling the address of the buffer memory 16 is provided. The reproduced digital data read from the buffer memory 16 is the D / A converter.
It is supplied to 18, converted into analog data by the external clock CKR, and output. When the reproduction data is video data, the component signal is converted into the three primary color signals and then returned to the analog signal. This external clock CK
R is the same as the external clock CKW used during recording and is a well-managed and extremely stable clock signal. Further, the external clocks CKR and CKW do not overflow in the buffer memory 2 and the buffer memory 16 when processing one scan of data,
It has a lower frequency than the system clock CKS.

The interface 17 takes in control data at the time of reproduction and also acts as an intermediary when pulling up reproduction data having a sequence number matching the sequence number designated by the user to the host computer. Reference numeral 19 denotes a microprocessor provided in the above-mentioned processor for processing the data on the recording side and the reproducing side, and a data, control and address bus 20 is provided between the microprocessor 19 and the interfaces 5 and 17. It is provided.

Reference numeral 21 denotes a system controller of this embodiment, in which a data, control and address bus 22 is provided between the system controller 21 and the microprocessor 19.
Further, the system controller 21 is a host computer.
Connected with 27. The system controller 21 is provided with a microprocessor 23, and the microprocessor 23
A key panel 24 is provided in association with the. Further, the system controller 21 is provided with a CRT display 25 and a keyboard 26 in association with the microprocessor 23.

The key panel 24 of the system controller 21 is provided with a key for remotely controlling the tape running operation of the data recorder, a key for generating a control word, a key for specifying an operation mode, and the like. The system controller 21 generates a remote control signal for controlling the tape running operation. System controller 21
The microprocessor 23 is an external host processor 27.
And is coupled via interface 28.

In order to record the directory or header in the above-mentioned tape format, the contents to be written are decided by the program on the microprocessor 23 side of the system controller 21 and transmitted to the microprocessor 19 via the data and address bus 22. By the program of this microprocessor 19, the contents are written in the memory of the interface 5, and the contents of the memory of the interface 5 are written in an appropriate area of the buffer memory 2. After writing the directory or header in the buffer memory 2 in this way, the microprocessor 23 of the system controller 21 controls the data recorder, searches for a desired recording position, and records the contents of the buffer memory 2 at this position. .

When you want to change the contents of the directory or header, first the program on the microprocessor 23 side searches for the directory or the position of the desired header, stores the data in the buffer memory 16, and then the interface memory 16 stores the data. Transfer to 17 memory. The microprocessor 19 reads the contents of the memory of the interface 17 byte by byte, transfers them to the memory of the interface 5, and transfers the contents of the memory of the interface 5 to the buffer memory 2. The above operation is repeated a plurality of times to complete the transfer from the buffer memory 16 to the buffer memory 2. Then, the program of the microprocessor 19 deletes or inserts the contents of the buffer memory 2 to change the contents. The changed directory or header is recorded at the target position on the magnetic tape 9.

Compared with the buffer memories 2 and 16, the memories in the interfaces 5 and 17 have a small capacity. Further, these memories are composed of a relatively high speed dynamic RAM, for example, so that input data can be written in real time, and operate by the system clock CKS.

FIG. 5 is a block diagram for explaining the processing of recorded data and reproduced data according to the embodiment of the present invention. In FIG. 5, reference numeral 31 denotes a small-capacity memory provided in the recording-side interface 5, and 32 is a buffer controller provided in the interface 5 for controlling the buffer memory 2. 33 indicates a small capacity memory provided in the interface 17 on the reproducing side, and 34 indicates the interface 17
Is a buffer controller for controlling the buffer memory 16. With buffer controllers 32 and 34,
Direct memory access (DMA) is performed between the buffer memory 2 and the memory 31 and between the buffer memory 16 and the memory 33.

The buffer controller 32 includes control signals RO ₁ and TR ₁ from the microprocessor 19 and an address signal AD ₁
And are supplied. The buffer controller 34 is supplied with the control signals RO ₁ and TR ₂ from the microprocessor 19 and the address signal AD ₂ . Memory 31 and memory
33 is coupled to the microprocessor 19 via the bus 20. The interface 17 is provided with registers 35 and 36 connected to the bus 20. One register 35
Stores the sequence number designated by the microprocessor 19, and the other register 36 stores the reproduction sequence number read from the memory 33. The contents of these registers 35 and 36 are supplied to the comparison circuit 37, and the output of this comparison circuit 37 is supplied to the buffer controller 34.

The operation of testing the recording / reproducing path from the buffer memory 2 to the buffer memory 16 in the above-described embodiment will be described.

First, a program on the microprocessor 23 is selected by operating the keys on the key panel 24, and a command for generating a test signal is given to the microprocessor 19 by operating the keyboard 26 associated with the CRT display 25. The microprocessor 19 runs a program according to the inventive command, and writes a test signal in the memory 31. As this test signal, an M series, a ramp waveform, a pulse series of maximum frequency, etc. can be generated. At the same time, the microprocessor 19 generates an expected value signal corresponding to the test signal to be used and stores it in the data memory.

The test signal stored in the memory 31 is transferred to the buffer memory 2. In this case, the address signal AD ₁ and the control signal TR ₁ from the microprocessor 19 are supplied to the buffer controller 32, and the test signal is transferred at high speed to the start address and end address of the buffer memory 2 determined by the address signal AD _1. It When all the test signals have been transferred, the control signal RO ₁ from the microprocessor 19 causes the buffer memory 2 to be in the read-only state, that is, the write-inhibited state and the read-only state, and the output of the buffer memory 2 receives the test signal. To be This test signal is recorded on the magnetic tape 9.

Also, write the above-mentioned test signal to the memory 31 and
Repeat the operation with the transfer from 31 to the buffer memory 2,
The test signal may be written in all of the buffer memory 2, and then the read-only state may be set to use all the recording signals of one scan as the test signal.

The buffer memory 16, the memory 33 and the buffer controller 34 on the reproducing side also perform the same operation as described above. The reproduction data of the address designated by the address signal AD ₂ supplied from the microprocessor 19 to the buffer controller 34 is transferred to the memory 33 at high speed by the control signal TR ₂ . At the time of this data transfer, the buffer memory 16 is set to the read-only state. The reproduction test signal fetched in the memory 33 is picked up by the microprocessor 19 and collated with the expected value signal. With this, the error status of the recording / playback path is measured, and the result is measured by the microprocessor.
It is transferred to 23 and displayed on the CRT display 25, or output by a printer (not shown).

Similar to the above-mentioned test, data is written from the external host processor 27 to the memory 31 via the microprocessor 23 and the microprocessor 19, and the data is transferred from the memory 31 to the designated address of the buffer memory 2 at high speed. However, it can be recorded on the magnetic tape 9. On the contrary, the data of the designated address of the buffer memory 16 can be transferred at high speed to the memory 33 and can be pulled up from the memory 33 to the external host processor 27 via the microprocessor 19.

As described above, when the reproduction data written in the buffer memory 16 is transferred to the memory 33 and pulled up to the microprocessor 23 via the microprocessor 19, the sequence number added for each scan can be used. .

When a sequence number is designated by the key panel 24 of the system controller 21, this designated sequence number is transmitted to the microprocessor 19 via the bus 22. The microprocessor 19 registers this designated sequence number in the register 35.
To load. When the system controller 21 makes the reproduction state, the reproduction sequence number obtained from the reproduction data is taken into the register 36. When the contents of both registers 35 and 36 match, the comparison circuit 37 outputs a match pulse to the buffer controller 34. With this coincidence pulse, the buffer controller 34 prohibits the write operation of the buffer memory 16. After this, the contents of the buffer memory 16 are transferred to the memory 33 by DMA, and the contents of the memory 33 are pulled up to the microprocessor 19.

In this way, the playback data of the specified sequence number can be loaded to the microprocessor 19 at any time, so that the host processor 27 can pull up and analyze peculiar data among the measurement data, or to use the host processor.
It is possible to view a desired still image in the reproduced video data by using 27.

[Advantage of the Invention] According to the present invention, since the memory for exchanging data with the buffer memory and the DMA and the buffer memory and the microprocessor are interposed, the recorded data or the reproduced data stored in the buffer memory is stored. Can be pulled up to the microprocessor in a very short time, and predetermined data can be stored in the buffer memory from the microprocessor in a very short time. Therefore, it is possible to easily record or reproduce digital signals other than the original recorded data, such as graphics data from the host processor or test signals generated by the microprocessor, and the functions of the digital data recorder. Can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall construction of an embodiment of the present invention, FIGS. 2 and 4 are schematic diagrams used to explain a tape pattern of an embodiment of the present invention, and FIG. FIG. 5 is a schematic diagram used to explain a configuration of recording data according to one embodiment
The figure is a block diagram of the essential portions of an embodiment of the present invention. 2,16 …… Buffa memory, 5,17 …… Interface,
9: Magnetic tape, 19,23: Microprocessor, 21
...... System controller, 27 …… Host processor,
31,33 …… Memory, 32,34 …… Buffer controller.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Kaichi Yamamoto 6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation (56) References JP-A-58-54464 (JP, A)

Claims (1)

[Claims] 1. A first buffer memory for storing a digital signal, a first interface section, a recording circuit to which the digital signal read from the first buffer memory is supplied, and an output of the recording circuit. Recording and reproducing means for reproducing the digital signal from the recording medium and supplying the digital signal to the reproducing circuit, a second buffer memory for storing the output of the reproducing circuit, and a second interface section. A microprocessor coupled to the first interface unit and a second interface unit, the first interface unit coupled to the first buffer memory for direct memory access, The third, which has a smaller capacity than the first buffer memory
Memory and a first control circuit for controlling writing and reading of the first buffer memory, and the second interface unit is coupled to the second buffer memory for direct memory access. In addition, the fourth buffer having a smaller capacity than the second buffer memory
Memory and a second control circuit for controlling the second buffer memory, and a comparison means for comparing designated address information with the address information of the reproduced data, the designated address information and the reproduced data When the address information matches, the second control circuit prohibits the write operation to the second buffer memory and transfers the reproduced data of the matched address information to the microprocessor. Digital signal recording / reproducing device.