JPH0665228B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention [relates] relates the active layer is stacked-type semiconductor device stacked two or more layers on a substrate, more particularly stacked-type static random access memory (S tatic R andom A ccess M emo
ry, hereinafter referred to as “SRAM”) cell structure.

[Usually conceivable laminated structure and its problems]

FIG. 2 shows a conceptual diagram of a two-layer structure of a complementary SRAM cell. This figure as an example, a part of the layers of the multi-laminate type semiconductor integrated circuit [hereinafter Laminated LSI (L arge S cale I ntegration ) and referred]. A lower portion (lower layer) and an upper portion (upper layer) 1 of the one-dot chain line 1 in the center of the figure correspond to the kth active layer and the (k + 1) th active layer, respectively. Here, k is a layer number of the active layer and is an integer of 1 or more. 11,21,3
1,41 is an n-type MOSFET.
Called TL1, TL2, TL3, TL4. Similarly, 12 and 22 are p-type MOSFETs,
Called TU1 and TU2 respectively. TL1 and TU1 pair and TL2 and TU2
Of the pair form a first complementary inverter and a second complementary inverter, respectively, and the input terminal of one inverter is connected to the output terminal of the other inverter. 13a,
Reference numerals 13b and 13c respectively denote a lower layer output line and an upper layer output line of the first inverter, and vertical wirings connecting 13a and 13b, and 13a, 13b and 13c are collectively referred to as an output line of the first inverter. Similarly, 14a,
Reference numerals 14b and 14c denote lower input lines and upper input lines of the first inverter, and vertical wirings connecting 14a and 14b.
14c is generically called the input line of the first inverter. On the other hand, 23a, 23b, and 23c are lower-layer output lines and upper-layer output lines of the second inverter, and vertical wirings connecting 23a and 23b.
b and 23c are collectively referred to as the output line of the second inverter. Similarly, 24a, 24b, and 24c are the lower-layer input line and the upper-layer input line of the second inverter, and the vertical lines connecting 24a and 24b.
24c is generically called the input line of the second inverter. 32
And 42 are bit line pairs, and 52 is a word line.

Next, a general method for realizing the stacked SRAM of FIG. 2 will be outlined below. First, as a first step, a lower active layer (for example, an active layer with k = 1) is formed by a normal integrated circuit process using a normal single crystal silicon substrate. However, in this case, it is desirable to use a low resistance, high melting point metal or the like as the wiring material. Next, as a second step, in order to electrically connect the lower layer device and the like to the device in the upper active layer (eg, k = 2 active layer) to be created next,
Vertical wiring 13c, 14c, 23c, 24c is created. Finally, as a third step, well-known SOI (S ilicon o n
Using I nsulator) technique, an SOI layer is formed on the underlying active layer, the SOI layer, making the device, the upper layer of the active layer.

Next, another method for constructing the SRAM of FIG. 2 will be outlined.
First, the active layers of the upper layer (k = 2) and the lower layer (k = 1) are
At the same time, it is formed by using the above-mentioned first step and second step. Then, in some cases, dicing to a desired chip size is performed, the upper and lower active layers are superposed, and the elements in the upper and lower active layers are electrically connected to each other by using a technique such as diffusion welding. , Connect via vertical wiring.

As is clear from the above description, the stacked SRAM cell has an excellent feature that it can be highly integrated as compared with a normal planarly arranged SRAM cell. However, as shown in FIG. 2, there are at least four vertical wirings connecting the upper and lower active layers in a single cell. This causes the yield deterioration of the integrated SRAM LSI.

[Purpose of the present invention]

An object of the present invention is to provide a structure of a new stacked SRAM cell in which four vertical wirings required in the stacked SRAM cell are halved to improve the area factor and the yield.

[Configuration of the present invention]

The present invention relates to transistors TL1 and TL2 formed in a k-th active layer (k is an integer of 1 or more) of a multi-layer semiconductor integrated circuit in which active layers are laminated and a TL in the (k + 1) -th active layer.
At least at least transistors TU1 and TU2 having polarities different from that of TL1 and TL2, respectively, and a first complementary inverter composed of TL1 and TU1 and TL
2 and TU2 to form a second complementary inverter, and using two vertical wirings connecting the kth active layer and the (k + 1) th active layer to each other, one by one, the output line of the first inverter and the The output line of the second inverter is formed, and the input lines of TL1 and TU1 that form the first inverter are connected via the output line of the second inverter, and TL2 and T that form the second inverter.
The semiconductor memory device is characterized in that the input line of U2 is connected through the output line of the first inverter.

〔Example〕

FIG. 1 shows a schematic view of a stacked / complementary SRAM cell of the present invention. This figure shows a part of layers of a laminated LSI having a multilayer structure. The lower part of the dashed-dotted line 1 in the center of the figure (lower layer)
And the upper part (upper layer) of 1 corresponds to the kth active layer and the (k + 1) th active layer, respectively. Here, k is a layer number of the active layer and is an integer of 1 or more. 11,21,31,41 is n type M
OSFET is simple, so in the following, TL1, TL2, TL3, T respectively
Similarly, 12 and 22 are p-type MOSFETs called L4, and TU1 and T
Call it U2. The pair of TL1 and TU1 and the pair of TL2 and TU2 form a complementary inverter 1 and a complementary inverter 2, respectively. Reference numerals 13a, 13b, and 13c denote lower-layer output lines, upper-layer output lines, and vertical wirings connecting 13a and 13b, respectively, which are collectively referred to as the output lines of the inverter 1. Similarly, 23a, 23b, and 23c are lower wiring, upper wiring, and 23a and 23b of the inverter 2, respectively.
23a, 23b, and 23c, which are vertical wirings connecting the two, are collectively called an output line of the inverter 2. Reference numerals 15a and 15b are lower and upper layer input lines of the inverter 1, respectively, and 25a and 25b are lower and upper layer input lines of the inverter 2, respectively. 32 and 42 are bit line pairs, and 52 is a word line.

Next, a stacking process for stacking the upper layer and the lower layer will be briefly described. First, metal bumps such as Al or Au are provided at predetermined positions on the upper and lower layers. Next, the upper layer and the lower layer are opposed to each other, and the predetermined metal bumps are brought into contact with each other, and heat and pressure are applied to the upper and lower metal bumps, so that the upper and lower metal bumps are thermocompression bonded and electrically connected to each other. To form. The conditions for thermocompression bonding are, for example, Au with an area of about 100 square microns.
For Au bumps of the same size as the bumps, sufficient electrical connection is made by applying a pressure of about 60 mg · f per bump for about 30 minutes in an N ₂ atmosphere at about 300 ° C.

As is clear from FIG. 1, the output line (23
a, 23b, 23c) also serves as a part of the input line of the inverter 1, and the output line (13a, 13b, 13c) of the inverter 1 also serves as a part of the input line of the inverter 2. Therefore, while the inverter of the stacked SRAM cell shown in FIG. 2 has vertical wirings independently for the input line and the output line, the stacked SR of the present invention is used.
The AM cell inverter need only have one vertical wire. Therefore, the number of vertical wiring lines per cell is four in the SRAM cell of FIG. 1, whereas it is two in the SRAM cell of the present invention, which can be reduced to half. Therefore, not only the area factor can be improved, but also the yield can be dramatically improved.

As described above, the stacked / complementary SRAM cell of the present invention is
Although the SFET is used for description, the present invention is not limited to this. That is, FE of bipolar transistor and GaAs
Other types of active elements such as T and materials other than silicon may be used.

〔The invention's effect〕

As described above, the number of vertical wirings of the SRAM cell of FIG. 2 is two, whereas the number of vertical wirings of the SRAM cell of FIG. Therefore, the area factor is improved and the yield is improved.

[Brief description of drawings]

FIG. 1 is a block diagram of a stacked / complementary SRAM cell of the present invention, and FIG. 2 is a block diagram of a conventional stacked / complementary SRAM cell.
In both figures, 11,21,31,41 are n-type MOSFETs and 12,22 are p-types.
MOSFET, 13a, 13b, 13c, 23a, 23b, 23c are output lines, 15a, 15b, 2
5a, 25b, 14a, 14b, 14c, 24a, 24b and 24c are input lines, 32 and 42 are bit line pairs, 52 is a word line, and 1 is a boundary line between the upper active layer and the lower active layer.

Claims (1)

[Claims] 1. Transistors TL1, TL2 and (k + 1) th active layer formed in a kth active layer (k is an integer of 1 or more) of a multi-layer semiconductor integrated circuit in which active layers are laminated in multiple layers. At least transistors TU1 and TU2 having polarities different from those of TL1 and TL2, and forming a first complementary inverter composed of TL1 and TU1 and a second complementary inverter composed of TL2 and TU2,
Also, the output line of the first inverter and the output line of the second inverter are formed by using two vertical wirings that connect the kth active layer and the (k + 1) th active layer to each other to form the first inverter. TL2 which forms the second inverter by connecting the input lines of TL1 and TU1 via the output line of the second inverter
And a TU2 input line is connected via the output line of the first inverter.