JPH0666063B2 - Sequence controller - Google Patents

Description

The present invention relates to a sequence control device using a central processing unit (hereinafter referred to as CPU).

Generally, a microcomputer is used for controlling machines in various fields such as industrial machines, office machines, household appliances, and the like.
When the sequence control of the machine is executed by the microcomputer, the control is usually performed by controlling the input / output port of the microcomputer by programming. Conventionally, this type of control microcomputer is often composed of a single CPU, and all controls are serially executed by a single task program. Therefore, programming is all-event check-type micro-computer control that checks all events, issues input / output commands every time there is necessary control, and returns to the beginning of the program when the necessary control is completed. .

In such a control method, not only the same input / output control is repeated because the control is executed serially, but also the judgment of the event becomes complicated and the programming is very difficult in the control which processes in parallel at the same time. It was In addition, when the control specifications are changed, the control parts other than the changed parts are often affected, and there is a drawback that the programmer is overloaded.

In view of the above points, an object of the present invention is to provide a sequence control device capable of reducing the load on the input / output control in the control executed by the microcomputer (CPU).

According to the present invention, the first information specifying the slave CPU executed by the master CPU, the second information indicating the processing contents such as ON of the controlled object controlled by the slave CPU, and the third information indicating the control time thereof are provided. The control information of the predetermined format including is sent to the slave CPU, and the first among the plurality of slave CPUs is sent.
The slave CPU designated by this information executes the input / output control of the designated control target for the designated control time according to the second information and the third information. In addition, by using the control information in a predetermined format, unified input / output control can be realized and the master
The load on the CPU can be reduced.

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a processor configuration for realizing the present invention. Here, the master CPU 11 is, for example, Intel | 8085,
Slave CPUs 21, 22 and 23 are also CPUs by Intel | 8741. These CPUs use Intel's single board computer SBC 569. In the embodiment of the present invention, these computers are used for controlling, for example, a copying machine, the first slave CPU 21 controls the input / output of the operation unit, and the second slave CPU 22 controls the reader for reading originals. The third slave CPU 23 controls the input / output of the printer. Both slave CPUs 22 and 23 are equipped with four I / O expanders 31-37 and 41-47, respectively. The master CPU 11 has a plurality of sequence control task groups and a real-time monitor function for managing these tasks. Master CPU 11 and slave CPUs 21, 22 and 23
The I / O protocol with each of the above is performed through the data bus buffer (DBB) in each slave CPU. The interrupt is performed by supplying the 20 ms clock interrupt signal 53 from the program interval timer (| 8253-5) 51 to RST7.5 of the master CPU 11. This interrupt is an interrupt counted when @WAIT of the execution control macro described later in FIG. 3 is issued. Via the programmable interrupt controller (| 8259A) 61, the interrupt signal 63 from the slave CPU 21 and the drum clock pulse interrupt signal 65.
Is supplied to the master CPU 11. The interrupt signal 63 from the slave CPU 21 is generated when a data transfer request is issued from the operation unit (keyboard) 71. The drum clock pulse interrupt signal 65 is a clock interrupt signal that depends on the rotation angle of the photosensitive drum (not shown) of the printer, and is counted when the @IWAIT macro command of FIG. 3 described later is issued. Interrupt. Thereby, the timing of sequence control is determined. Further, the 20 ms clock interrupt signal 53 from the interval timer 51 is also supplied to both slave CPUs 22 and 23. This is an interrupt counted by both slave CPUs 22 and 23 when the input / output control macro @TSET of FIG. 5 is issued.

This sequence control device is configured by the above processor configuration, and its functions are roughly classified into real-time parallel processing and an input / output control function. Hereinafter, it will be simply referred to as a monitor. The function of this monitor will be described below.

This monitor can design and code processing programs required for various applications on a task-by-task basis by the real-time parallel processing function. The multiplicity of task running levels in this monitor is 2, which corresponds to the interrupt level and the program level (P level). The task has three states of execution, stop, and standby, and all are in a stop state when the power is turned on. Task execution is ENTR
It is done by the macro and is in the execution WAIT macro. Further, in reality, the task is made to wait for execution even by an interrupt, but in any case, it is automatically restarted by releasing the factor. In the P-level task, the above-mentioned real-time parallel processing is possible, and only when one task is stopped or waited, the monitor's round-robin scanning (input port, memory By checking with a flag), the next request task is sequentially activated and becomes the execution state.

Figure 2 shows the task state transitions. Here, the solid line indicates that each tax is an execution control macro (ENTR, STOP, WAIT, IWAIT, ESCP)
Shows the state transition when the is issued, and the dotted line shows the state transition automatically performed by the monitor. When a task in the stopped state is ENTR (entered) by another task, it becomes the runnable state. When the task being executed issues a STOP macro, it enters a stopped state, and when it issues a WAIT or IWAIT macro, it enters a wait state, E
Executing the SCP (escape) macro puts it in an executable state. When the waiting task is timed up, the monitor is automatically enabled. In addition, the task in the READY state becomes RUNNING by the monitor's automatic round-robin scanning.

FIG. 3 shows the format and function of the execution control macro.
When each macro is issued from each task, control is transferred to the monitor by the restart command (RST), the monitor judges each macro, and executes the contents indicated in the function. @WAIT is counted by a timer interrupt for every fixed time, and @IWAIT is counted by the monitor by an external interrupt at a constant interval (in this embodiment, a pulse proportional to the rotation of the drum of the copying machine).

The input / output control function assigns an identification number (ordinal) for commonly recognizing each point of the input port, output port, and soft flag across both software and hardware, and turns them on (ON) and off. The input / output control macros that turn off and check (check) make it extremely easy to manage input / output commands or flags by the application program. That is, the monitor receives the input / output control macro instruction by the application program and transfers the processing information (ON, OFF, CHECK, etc.) and the identification number to the slave CPUs 21, 22, 23. These slave CPUs store the processing information corresponding to the identification number in the RAM area in each slave CPU, and execute the input / output control by constantly refreshing the processing information.

FIG. 4 shows a conceptual diagram of the identification number (hereinafter referred to as “ornal”). Ordinary is a number that enables common recognition by associating the terminal numbers, sensors, actuators, etc. recognized on the hardware side with the port numbers, I / O addresses, and bit numbers recognized on the software. Is. Furthermore, the concept is to extend the control points of the processor in general by adding flags that are formed only on software other than the I / O port. As shown in FIG. 4, an ordinary is assigned to the memory RAM of the slave CPUs 21, 22, 23. That is, the byte number in RAM (BYTE NO)
And bit number (BIT NO) as shown in Fig. 4. In this embodiment, 4 bytes (32 points) are assigned to each of the input port (Di), the output port (Do) and the flag.

FIG. 5 shows an input / output control macro instruction for controlling these externals. The slave CPUs 21 to 23 are recognized as the first, second, ... In the macro parameters of FIG. When each task issues these I / O control macros, the monitor decodes the macro instruction and executes the contents indicated by the function.
That is, these pieces of information are delivered from the monitor to the slave CPUs 21 to 23, and the slave CPUs 21 to 23 control the ordinary on the RAM. Information is delivered by an interrupt from the master CPU 11 to the slave CPUs 21 to 23.
21 to 23 RAM at program level other than interrupt level
Input / output control is performed by constantly reflecting the above information to the I / O port (Di and Do only). In FIG. 5, @TSET is a macro instruction that turns on the oral for a specified time, and each task does not have to wait until the off of the oral after issuing this macro instruction. @TSET
The slave CPU which received the instruction of turns on the specified external, counts the time by the timer interrupt of the T1 terminal (Fig. 1), and turns off the external after the specified time. Therefore, since each task is executed by the master CPU 11, it is not necessary to count the time, and a plurality of timers can be set. With the above input / output macro instruction, each task
It realizes unified input / output control regardless of O port and soft flag.

[Brief description of drawings]

FIG. 1 is a block diagram showing a processor configuration for realizing a sequence control device according to the present invention, FIG. 2 is a state transition diagram of a task, and FIG. 3 is a diagram for explaining the format and function of an execution control macro. 4, FIG. 4 is a conceptual diagram of the identification number (ordinal), and FIG. 5 is a diagram for explaining the input / output control macro instruction. 11 …… Master CPU, 21 to 23 …… Slave CPU, 51 …… Interval timer, 53 …… Clock interrupt signal, 61 …… Programmable interrupt controller, 63 …… Interrupt signal, 65 …… Drum clock pulse Interrupt signal.

Continuation of the front page (56) Reference JP-A-54-50329 (JP, A) JP-A-55-36830 (JP, A) JP-A-56-86574 (JP, A) JP-A-55-59579 (JP , A) JP-A-56-14306 (JP, A) JP-A-56-42804 (JP, A)

Claims (1)

[Claims] 1. A master CPU for managing tasks in sequence control, and a plurality of slave CPUs that perform input / output control according to control information from the master CPU and control different control targets, respectively. CPU is the first to specify the slave CPU to execute
Control information of a predetermined format including second information indicating the control target controlled by the slave CPU and third information indicating the control time of the slave CPU.
To the slave CPU designated by the first information, the slave CPU and the third information of the control information from the master CPU.
A sequence control device which executes input / output control of a designated control object for a designated control time according to the information of 1.