JPH0666283B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a silicon (Si) selective epitaxial layer and a metal silicide electrode in contact therewith. The present invention relates to a manufacturing method of simultaneously forming in a self-aligning manner.

(Prior Art) Technological progress has been remarkable for high integration and high speed of bipolar LSI and the like. In the so-called selective epitaxial growth technique in the element isolation process, a relatively thick insulating film (oxide film) is formed on a Si substrate, and the insulating film is etched and opened almost vertically by the RIE (reactive ion etching) method. This is a technique for forming an element active region in a self-aligned manner on a silicon single crystal region where an opening is exposed as a separation portion by a selective epitaxial growth method. Since such a selective epitaxial growth method facilitates high integration and high speed of semiconductor elements, it has been generally used. The conventional selective epitaxial growth method of silicon is generally a vapor phase growth method. For this selective epitaxial vapor phase growth, methods such as reduction of SiCl ₄ with hydrogen, thermal decomposition of SiH ₂ Cl ₂ or SiH ₄ , which are conventionally used for forming an epitaxial layer of a highly integrated planar bipolar device, are used.

However, in the above method, impurity gas such as PH ₃ or C
The concentration of gas containing halogen elements such as l and Br determines the selectivity. For example, when an element active region containing a high concentration of an impurity element is to be formed, a higher impurity concentration causes a part of the element to adhere to the element isolation portion, resulting in lower selectivity.

Also, a high temperature of 1000 ° C or higher is required as the optimum growth temperature. Therefore, changes in the impurity concentration caused by so-called auto-doping during growth, out-diffusion of impurities in the substrate, and the like pose a serious problem. In particular, when forming a high-speed bipolar device, the impurity concentration distribution in the depth direction and the junction depth largely control the device characteristics. Therefore, it is necessary to minimize the change in the impurity concentration distribution during the manufacturing process.

(Problems to be Solved by the Invention) In the conventional selective epitaxial growth technique, the vapor phase growth method is generally used, but the optimum growth temperature is 1000 as described above.
There is a problem that a high temperature of not less than 0 ° C. is required, and selectivity is lowered when an epitaxial layer having a high impurity concentration is formed.

On the other hand, if the solid phase growth method is used, epitaxial growth is possible even at a relatively low temperature. It is reported that SOI growth (Si on Insulator) is possible at about 600 ℃ when using amorphous silicon (J. of APPl.Phys., 54 , 1983, 2847).
There is.

There is a strong market need for higher integration and higher speed of semiconductor devices. Therefore, further development of self-alignment technology and establishment of a selective epitaxial growth method with a low optimum growth temperature are important issues.

The object of the present invention is a semiconductor which can be applied to a fine device such as a high-speed bipolar device and which can perform selective epitaxial growth of silicon at a relatively low temperature and at the same time form a metal silicide layer in contact with this epitaxial growth layer. A method of manufacturing a device is provided.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a silicon single crystal region exposed on a main surface of a substrate (including a Si substrate, an SOI substrate, etc.) with a constituent element of 68 atoms.
% (Atomic percentage), a step of forming an amorphous film composed of Si and the remaining metal, and heat treatment to make the amorphous film into an MSi ₂ -type crystalline metal silicide and at the same time silicidation. And selectively epitaxially growing unused silicon on the surface of the silicon single crystal region, wherein both the crystalline metal silicide film and the selective epitaxial growth layer are used as constituent film layers of the device. And a method for manufacturing a semiconductor device.

(Operation) The metal element M contained in the amorphous film needs to be a metal such as Ti, W, Mo, Ta, Co, Ni, Fe, Cr capable of forming an MSi ₂ type metal silicide. . In the silicide, which is a metal compound of the above metal and Si, there is no metal silicide that is richer in Si than the MSi ₂ type metal silicide and is thermodynamically stable. Accordingly, the amorphous film of the remaining metal with Si 68 atom% or more contains a stoichiometrically excessive amount of Si atoms.

When an amorphous film of the above constituent elements is deposited on the Si single crystal region and heat-treated, a crystalline metal silicide is produced and at the same time, the excess Si atoms not used for silicidation are:
Epitaxial growth is selectively performed on the surface of a Si single crystal with low crystal growth energy. The heat treatment temperature at this time depends on the type of metal silicide, but a relatively low temperature of 900 ° C. or lower is sufficient.

If necessary, N-type or P-type impurity ion implantation is performed on the surface of the amorphous film, and the amorphous film is selectively removed by etching while leaving the Si single crystal region. An N-type or P-type selective epitaxial layer having a metal silicide electrode can be formed in a self-aligned manner, which is a preferred embodiment.

Also, if the number of Si atoms contained in the amorphous film is less than 68 atom%, according to the trial results, it may not be possible to obtain a Si epitaxial layer having a thickness that is substantially usable, which is unsuitable. .

(Example) The Example of this invention is described below with reference to drawings.
The sectional view shown in FIG. 1 shows an embodiment for explaining the basic configuration of the present invention. First, as shown in FIG. 1A, an insulating film 2 (for example, Si
After forming an O ₂ film), an opening whose side wall is substantially perpendicular to the substrate surface is provided in the insulating film 2 by a photo-etching method including RIE to obtain an exposed surface 1a of the Si single crystal region.

Next, as shown in FIG. 7B, an amorphous film containing 68 atom% or more of Si and the remaining metal as constituent elements, for example, 75 atom% of Si,
An amorphous film 3 containing 25 atom% of Mo is formed by a sputtering method or the like. For the sputtering method, for example, Si 75 atom
%, And a hot press molded product of a mixture having a composition of Mo 25 atom% was used as a target. Next, ion implantation 4 of N-type impurities (for example, As) is performed on the surface of the amorphous film 3.

Next, as shown in FIG. 3C, the amorphous film other than the region including the opening of the insulating film is removed by etching by a known RIE method. Next, heat treatment is performed. The heat treatment conditions differ depending on the type of metal silicide formed by the heat treatment, but a relatively low temperature of 900 ° C. or lower is sufficient. When the amorphous film is composed of Si and Mo, heat treatment at 800 ° C. for about 90 minutes in an N ₂ atmosphere is suitable.

By this heat treatment, the amorphous film becomes a crystalline MoSi ₂ film 6, but it is stoichiometrically not used for forming the MoSi ₂ film.
% Excess Si is present. This is because there is no thermodynamically stable Mo silicide that is richer in Si than MoSi ₂ type metal silicide, so it precipitates as crystalline Si, and especially in the region where single crystal Si is exposed, due to the difference in crystal growth energy, Epitaxially grows on single crystal Si. At this time, the thickness of the epitaxial layer 5 is about 700Å when the amorphous film thickness is 3000Å. Further, since the N-type impurities ion-implanted into the surface of the amorphous film are substantially evenly distributed in the epitaxial layer during the heat treatment, the epitaxial layer becomes N-type and a PN junction is formed between the epitaxial layer and the P-type Si substrate 1. It is formed.

FIG. 2 shows an embodiment in which the present invention is applied to the emitter portion of a self-aligned bipolar transistor having a lead base electrode. A high-concentration shallow P-type base 12 is provided on an N-type collector region 11 formed on a semiconductor substrate. A polycrystalline silicon layer 13 doped with P-type impurities is connected to the base region through an opening of an insulating film 14. The polycrystalline silicon layer 13 is a lead base electrode and is covered with an insulating film 17.

The present invention is applied to the formation of the emitter region. That is, the insulating film 17 is opened by dry etching to expose a part of the P-type base region 12 of silicon single crystal. Next is Si 75atom
%, W 25 atom% amorphous film is formed by the sputtering method. Next, ion implantation of N-type impurities is performed to etch away the amorphous film other than the region including the opening.
Heat treatment is performed at 0 ° C. for about 120 minutes. By this heat treatment,
An epitaxial layer 15 containing N-type impurities and a tungsten silicide (WSi ₂ ) electrode 16 are formed. Reference numeral 18 is an insulating film, and reference numerals 19 and 20 are conductive films (Al) serving as a base electrode and an emitter electrode, respectively.

The base / emitter is separated by the insulating film 17, and the epitaxial layer 15 is used as an emitter region, so that the base / emitter junction surface is substantially flat. The heat treatment conditions for the epitaxial growth are as described above, and since the impurity distribution of the P-type base region 12 hardly changes by such heat treatment, a shallow base-collector junction, that is, a small base width can be maintained. Also, since tungsten silicide, which has a lower resistance (for example, about 1 digit) than the conventionally used polycrystalline silicon, serves as the emitter electrode,
It also has an effect of reducing the emitter resistance, which is very advantageous for speeding up the transistor.

The above is an example in which the present invention is applied to a high-speed bipolar transistor.However, the present invention can form a selective epitaxial layer that bonds with metal silicide in a self-aligned manner as long as there is a region where single crystal Si is exposed. Its application range is extremely wide.

For example, as shown in FIG. 3, a single crystal silicon layer grown through an opening on an insulating film 22 covering a silicon substrate 21.
23 are provided. An element having the metal silicide electrode 26 and the selective epitaxial layer 25 on the exposed single crystal region can be easily formed by selectively opening the insulating film 24 attached to the single crystal silicon layer 23.

Furthermore, since the interface between the selective epitaxial layer and the metal silicide is also formed in a self-aligned manner, even when attempting to form a Schottky barrier diode using this interface, the Schottky characteristic of the interface between the metal silicide and Si is used. A diode having a barrier height can be formed with good reproducibility.

The thickness of the selective epitaxial layer which is a self-aligned layer can be easily controlled by the composition and thickness of the amorphous film which is a starting material, and by using this as an element active region,
It is very advantageous not only for high integration of elements but also for high speed operation.

[Effects of the Invention] As described above, according to the method for manufacturing a semiconductor device of the present invention, it is possible to perform selective epitaxial growth of silicon at a low temperature of 900 ° C. or lower and simultaneously form a metal silicide layer in contact with this epitaxial layer. Becomes In the manufacturing method of the present invention, the selective epitaxial layer is formed in a self-aligned manner on the silicon single crystal region exposed on the main surface of the substrate, and the metal silicide layer is formed in contact with the selective epitaxial layer in a self-aligned manner. Therefore, by using the present invention, the miniaturization of the element is further improved, and the higher speed of the element can be obtained with the miniaturization of the element.

[Brief description of drawings]

FIG. 1 is a sectional view showing a manufacturing process for explaining the basic structure of a manufacturing method of the present invention, FIG. 2 is a sectional view of an embodiment of a semiconductor device to which the present invention is applied, and FIG. FIG. 9 is a cross-sectional view when applied to a single crystal silicon film on an insulating film. 1,11,21 …… Silicon substrate, 1a …… Exposed surface of silicon single crystal region, 2,14,17,18,22,24 …… Insulating film, 3 …… Amorphous film, 5,15,25 …… Selected epitaxial layer, 6,16,26 …… Metal silicide.

Claims (1)

[Claims] 1. A step of forming an amorphous film composed of silicon having a constituent element of 68 atom% or more and the remaining metal on a silicon single crystal region exposed on the surface of a substrate, and a heat treatment to form the amorphous film. Forming a film of MSi ₂ -type crystalline metal silicide and at the same time selectively epitaxially growing silicon not used for silicidation on the surface of the silicon single crystal region, the film of the crystalline metal silicide and the selective epitaxial growth A method for manufacturing a semiconductor device, characterized in that each of the layers is used as a constituent film layer of an element.